JPH0542157B2 - - Google Patents

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Publication number
JPH0542157B2
JPH0542157B2 JP61029361A JP2936186A JPH0542157B2 JP H0542157 B2 JPH0542157 B2 JP H0542157B2 JP 61029361 A JP61029361 A JP 61029361A JP 2936186 A JP2936186 A JP 2936186A JP H0542157 B2 JPH0542157 B2 JP H0542157B2
Authority
JP
Japan
Prior art keywords
catalyst
hole
layer
printed wiring
wiring board
Prior art date
Legal status (The legal status is an assumption and is not a legal conclusion. Google has not performed a legal analysis and makes no representation as to the accuracy of the status listed.)
Expired - Lifetime
Application number
JP61029361A
Other languages
Japanese (ja)
Other versions
JPS62186594A (en
Inventor
Takashi Shin
Hidefumi Oonuki
Tomoaki Asano
Sunao Yasui
Current Assignee (The listed assignees may be inaccurate. Google has not performed a legal analysis and makes no representation or warranty as to the accuracy of the list.)
NEC Corp
Original Assignee
Nippon Electric Co Ltd
Priority date (The priority date is an assumption and is not a legal conclusion. Google has not performed a legal analysis and makes no representation as to the accuracy of the date listed.)
Filing date
Publication date
Application filed by Nippon Electric Co Ltd filed Critical Nippon Electric Co Ltd
Priority to JP2936186A priority Critical patent/JPS62186594A/en
Publication of JPS62186594A publication Critical patent/JPS62186594A/en
Publication of JPH0542157B2 publication Critical patent/JPH0542157B2/ja
Granted legal-status Critical Current

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  • Production Of Multi-Layered Print Wiring Board (AREA)

Description

【発明の詳細な説明】 〔産業上の利用分野〕 本発明は多層印刷配線板およびその製造方法に
関し、特に高密度実装のために導体層が分割して
設けたスルホールを一部に有する多層印刷配線板
に関する。
[Detailed Description of the Invention] [Field of Industrial Application] The present invention relates to a multilayer printed wiring board and a method for manufacturing the same, and particularly to a multilayer printed wiring board in which a conductor layer has divided through holes in some parts for high-density packaging. Regarding wiring boards.

〔従来の技術〕[Conventional technology]

従来の多層印刷配線板の一つでは、部品挿入用
の孔は勿論、経由孔(以下バイア・ホールと称
す)も、貫通孔を穿設させて無電解めつき等の手
段により孔壁に導体層を設けることにより形成す
る。
In a conventional multilayer printed wiring board, not only holes for inserting components but also via holes (hereinafter referred to as via holes) are made by drilling through holes and attaching conductors to the hole walls by means such as electroless plating. Formed by providing layers.

また、従来の多層印刷配線板(以下、多層板と
略称)の他の一つでは、その高多層化に伴い、一
部の内層に埋込みバイア・ホールを設ける設計も
採用されつつある。
In addition, in another type of conventional multilayer printed wiring board (hereinafter abbreviated as multilayer board), as the number of layers increases, a design in which embedded via holes are provided in some of the inner layers is also being adopted.

近年、電子機器の性能上および経済上のニーズ
から実装の高密度化の試みがなされている。この
ためにIC,LSI等の電子デバイスの高集積化、高
速化が進められていることは勿論、これらを実装
する多層板についても高密度化が進められてい
る。
In recent years, attempts have been made to increase the packaging density of electronic devices due to performance and economical needs. For this reason, not only are electronic devices such as ICs and LSIs becoming more highly integrated and faster, but the multilayer boards on which these devices are mounted are also becoming more dense.

多層板の高密度化のために2つの試みが設計的
になされている。すなわち、その第1の試みは導
体層数を増加させる高多層化の試みであり、第2
の試みは格子パターン間に多くの配線を通すこと
である。しかし、第1の試みでは層間の導体層を
接続するバイア・ホールの増加になる。第2図の
ように特にこのバイア・ホール5を多層板に貫通
孔として設けた場合には、前述の第2の試みの配
線数が著しく制限される。そのためバイア・ホー
ル5を小径化することで対応しているが、高多層
化に伴つて板厚も増加し、板厚/孔径の比(アス
ペクト比)が増加し、多層板の製造性を著しく阻
害している。また、超高密度化が必要な分野で
は、10層以上の多層化を図り、内層にバイア・ホ
ールを設けた、いわゆる埋め込みバイア・ホール
が採用されているが、性能的には満足しても経済
的にみると全てのニーズを満足するものではなか
つた。
Two attempts have been made to increase the density of multilayer boards. In other words, the first attempt was to increase the number of conductor layers, and the second was an attempt to increase the number of conductor layers.
The attempt is to pass many wires between the grid patterns. However, the first attempt results in an increase in via holes connecting the interlayer conductor layers. Particularly when the via hole 5 is provided as a through hole in the multilayer board as shown in FIG. 2, the number of wiring lines in the above-mentioned second attempt is significantly limited. This has been dealt with by reducing the diameter of the via hole 5, but as the number of layers increases, the plate thickness also increases, and the ratio of plate thickness/hole diameter (aspect ratio) increases, significantly reducing the productivity of multilayer plates. It's hindering. In addition, in fields that require ultra-high density, so-called buried via holes, which are multi-layered with 10 or more layers and have via holes in the inner layers, have been adopted, but they are not satisfactory in terms of performance. From an economic point of view, it did not satisfy all needs.

また、多層板でも特に、オフイス・オートメー
シヨン機器(OA機器)等で需要の増大が予測さ
れる5〜10層の多層板において前述の問題を解決
する必要が生じている。
Furthermore, there is a need to solve the above-mentioned problems in multilayer boards, especially in multilayer boards with 5 to 10 layers, whose demand is expected to increase in office automation equipment (OA equipment) and the like.

このための一つの試みとして“メイキング
100000サーキツトフイツトホエアアツトモスト
6000フイツトビフオア(Making 100000
Circuits fit where at most 6000 fit before;
Electronic,August2,1979年)”で、第3図C
に示すブラインド・バイア・ホール、すなわち非
貫通孔によつて配線の収容性を向上させている。
As an attempt to achieve this goal, “Making”
100000 Circuits Fastest Where Most
Making 100000
Circuits fit where at most 6000 fit before;
Electronic, August 2, 1979), Figure 3C
The blind via holes shown in Fig. 1, i.e., non-through holes, improve the wiring capacity.

〔発明が解決しようとする問題点〕[Problem that the invention seeks to solve]

しかし、製造上から考慮すると“レーザーイン
エレクトロニクス(Lasers in Erectoronics;
Circuit Manufacturing ,July,1981年)”あ
るいは、“カツパープレーテイングアドバンスト
マルチレイヤーボード(Copper Plating
Advanced Multilayer Boards;IPC,1976年
Fall Meeting)”で紹介されているように、レー
ザまたはドリルによつて第3図Aの如き多層板1
に第3図Cのようにブラインド・バイア・ホール
5−1,5−2を片面ずつ穿設するという非能率
が伴う。
However, from a manufacturing perspective, “Lasers in Erectoronics”
Circuit Manufacturing, July, 1981)” or “Copper Plating Advanced Multilayer Board (Copper Plating Advanced Multilayer Board)”
Advanced Multilayer Boards; IPC, 1976
As introduced in ``Fall Meeting'', the multilayer plate 1 as shown in Figure 3A is removed by laser or drilling.
However, as shown in FIG. 3C, blind via holes 5-1 and 5-2 are formed on each side, which is inefficient.

さらにレーザによる穿設では、第3図Bのよう
に、多層板1のバイア・ホールが穿設されるべき
位置P−2の最外層の銅箔をエツチング除去した
後、バイア・ホールを穿設説する工程が必要とな
る欠点がある。
Furthermore, in laser drilling, as shown in FIG. 3B, the outermost copper foil of the multilayer board 1 at the position P-2 where the via hole is to be drilled is removed by etching, and then the via hole is drilled. There is a drawback that a detailed process is required.

またバイア・ホールを穿設した後、その内壁を
含む全面に無電解めつきで導体層を形成するが、
第3図Dの最外層の絶縁層1a−1,1a−2間
が厚い場合、均一な導体層の形成が難しく信頼性
上好ましくない。
In addition, after drilling a via hole, a conductive layer is formed on the entire surface including the inner wall by electroless plating.
If the distance between the outermost insulating layers 1a-1 and 1a-2 in FIG. 3D is thick, it is difficult to form a uniform conductor layer, which is unfavorable in terms of reliability.

本発明の目的は、このような従来多層板の構造
上の欠点を解消した多層印刷配線板およびその製
造方法を提供することにある。
An object of the present invention is to provide a multilayer printed wiring board and a method for manufacturing the same that eliminates the structural defects of conventional multilayer boards.

〔問題点を解決するための手段〕[Means for solving problems]

本発明によれば、予め導体回路パターンを表裏
両面に設けた触媒入りのめつき付着可能な絶縁板
の1組をそれぞれ最外側に配置し、その内側に触
媒入りプリプレグ層を配置し、更にその内側に予
め多層印刷配線板の表裏導通用の貫通孔の位置
に、その貫通孔の直径より大なる同心円にくり抜
いた孔部を設けた触媒無し絶縁板を配置し、加熱
加圧して前記触媒無し絶縁板のくり抜き孔部を前
記触媒入りプリプレグ層から流出した触媒含有樹
脂で充填し多層化基板を形成する工程と、 前記多層化基板の表裏両面に前記表裏導通用の
貫通孔と、内層導体パターン接続用の貫通孔の位
置に一定の逃げを設け、所望の部分に触媒無しの
絶縁樹脂層を被着する工程と、 前記表裏導通用の貫通孔と内層導体パターン接
続用の貫通孔を穿設する工程と、 前記多層化基板を無電解めつきし、表裏両面の
触媒無し絶縁樹脂層から露出している部分と、貫
通孔内壁の触媒入り絶縁層に導体層を形成する工
程とを有することを特徴とする多層印刷配線板の
製造方法が得られる。
According to the present invention, a pair of insulating plates containing a catalyst and capable of being attached by plating, each having a conductive circuit pattern on both the front and back sides, is arranged on the outermost side, a prepreg layer containing a catalyst is arranged inside the insulating plate, and A catalyst-free insulating plate with holes cut out in concentric circles larger than the diameter of the through-holes is placed in advance at the positions of the through-holes for front-to-back conduction of the multilayer printed wiring board, and heated and pressurized to eliminate the catalyst. forming a multilayered substrate by filling the hollowed-out hole portion of the insulating plate with the catalyst-containing resin that has flowed out from the catalyst-containing prepreg layer; and forming the through-holes for front and back conduction and the inner layer conductor pattern on both the front and back surfaces of the multilayered substrate. A process of providing a certain clearance at the position of the through hole for connection and applying an insulating resin layer without a catalyst to the desired part, and drilling the through hole for front and back conduction and the through hole for connecting the inner layer conductor pattern. and a step of electroless plating the multilayered substrate to form a conductive layer on the portions exposed from the catalyst-free insulating resin layer on both the front and back surfaces and the catalyst-containing insulating layer on the inner wall of the through hole. A method for manufacturing a multilayer printed wiring board is obtained.

〔実施例〕〔Example〕

以下、本発明の一実施例を図面で説明する。 An embodiment of the present invention will be described below with reference to the drawings.

第1図Eは本発明の多層板の実施例を示し、無
電解銅めつきに対して触媒となる金属パラジウム
等を均一に分散含有した触媒有り積層板1a−
1,1a−2および触媒有りプリプレグ層1b
が、触媒無し絶縁板3により上下に分離され、貫
通孔となるバイア・ホール5内にリング状に分離
した導体層7−1,7−2を有する。
FIG. 1E shows an embodiment of the multilayer board of the present invention, in which a catalyst-containing laminate 1a-1 containing metal palladium, etc., which acts as a catalyst for electroless copper plating, is uniformly dispersed.
1, 1a-2 and prepreg layer 1b with catalyst
is vertically separated by a catalyst-free insulating plate 3, and has conductor layers 7-1 and 7-2 separated in a ring shape within a via hole 5 serving as a through hole.

次に本発明による多層板の製造方法の実施例
を、第1図A〜Eを参照して詳細に説明する。
Next, an embodiment of the method for manufacturing a multilayer board according to the present invention will be described in detail with reference to FIGS. 1A to 1E.

第1図Aは積層構成を示し触媒有り積層板1a
−1,1a−2の表裏両面に公知の印刷、エツチ
ング法により所望する回路パターン2−1〜2−
4を形成した多層板を最も外側に配し、その内側
に触媒有りプリプレグ層1b−1,1b−2を配
し、さらにその内側に多層板の部品挿入用の孔が
穿設されるべき位置P−1に部品挿入用の孔の直
径より大きい同心円にくり抜いた孔を設けた、触
媒なし絶縁板3を組合わせ、加熱・加圧して一体
化成形し、第1図Bの多層板を得る。
Figure 1A shows a laminated structure, and a laminated plate 1a with a catalyst.
Desired circuit patterns 2-1 to 2- by known printing and etching methods on both sides of -1 and 1a-2.
4 is placed on the outermost side, prepreg layers 1b-1 and 1b-2 with catalyst are placed on the inside thereof, and holes for inserting parts of the multilayer board are to be drilled inside the multilayer board. P-1 is combined with catalyst-free insulating plate 3, which has concentrically hollowed holes larger than the diameter of the holes for inserting parts, and is integrally formed by heating and pressurizing to obtain the multilayer plate shown in Figure 1B. .

次に、多層板1の表面に不必要な導体層が形成
されないように、第1図Cのように、絶縁性と耐
薬品性とを有する永久マスク層4を所望部分に被
着形成する。
Next, in order to prevent unnecessary conductor layers from being formed on the surface of the multilayer board 1, a permanent mask layer 4 having insulating properties and chemical resistance is formed on desired portions as shown in FIG. 1C.

次に、第1図Dのように、部品挿入用のバイ
ア・ホール6および内層接続するバイア・ホール
5をドリルにより穿設する。
Next, as shown in FIG. 1D, a via hole 6 for inserting components and a via hole 5 for connecting the inner layer are drilled.

次に、全面に無電解銅めつきを施すと、第1図
Eのように、露出した導体層上およびバイア・ホ
ール5,6の内壁に銅めつき導体層7が形成さ
れ、特にバイア・ホール5では、触媒無し絶縁板
3により銅めつき導体層7が1−2層を接続する
導体層7−1と3−4層を接続する導体層7−2
に離間した多層板が得られる。
Next, when electroless copper plating is applied to the entire surface, a copper-plated conductor layer 7 is formed on the exposed conductor layer and on the inner walls of the via holes 5 and 6, as shown in FIG. 1E. In the hole 5, a copper-plated conductor layer 7 is formed by a catalyst-free insulating plate 3, a conductor layer 7-1 connecting layers 1-2 and a conductor layer 7-2 connecting layers 3-4.
This results in a multilayer board spaced apart.

〔発明の効果〕〔Effect of the invention〕

以上説明したように、本発明により、レーザ等
の特殊な手段、あるいは一面ずつ非貫通孔を穿設
する非量産的な従来手段によらず孔を穿設できる
ので生産性が著しく向上し、さらに内層接続の信
頼性の向上が図れ、配線収容性が著しく向上した
高密度な多層印刷配線が得られる効果がある。
As explained above, according to the present invention, it is possible to drill holes without using special means such as a laser, or non-mass-produced conventional means of drilling non-through holes one by one, thereby significantly improving productivity. This has the effect of improving the reliability of inner layer connections and providing high-density multilayer printed wiring with markedly improved wiring accommodation.

【図面の簡単な説明】[Brief explanation of the drawing]

第1図A,B,C,D,Eは本発明の一実施例
を工程順に示す断面図、第2図は従来例の一つの
断面図、第3図A,B,C,Dは従来例の他の一
つを工程順に示す断面図である。 1……多層印刷配線板、1a−1……1−2層
を形成する触媒有り積層板、1a−2……3−4
層を形成する触媒有り積層板、1b,1b−1,
1b−2……触媒有りプリプレグ層、2−1〜2
−4……1−4層の導体パターン、3……触媒無
し絶縁板、4……永久マスク層、5,6……バイ
ア・ホール、5−1,5−2……1−2層、5−
6層間を接続するブラインド・バイア・ホール、
7,7−1,7−2……無電解銅めつきによる銅
めつき導体層、P−1……部品挿入用の貫通孔の
穿設される位置、P−2……バイア・ホールが穿
設される位置。
Figures 1A, B, C, D, and E are sectional views showing an embodiment of the present invention in the order of steps; Figure 2 is a sectional view of a conventional example; and Figure 3 A, B, C, and D are sectional views of a conventional example. FIG. 7 is a sectional view showing another example in order of steps. 1...Multilayer printed wiring board, 1a-1...Laminated board with catalyst forming 1-2 layers, 1a-2...3-4
Laminated plate with catalyst forming layers, 1b, 1b-1,
1b-2...Prepreg layer with catalyst, 2-1 to 2
-4... 1-4 layer conductor pattern, 3... Insulating plate without catalyst, 4... Permanent mask layer, 5, 6... Via hole, 5-1, 5-2... 1-2 layer, 5-
Blind via holes connecting 6 layers,
7, 7-1, 7-2...Copper-plated conductor layer by electroless copper plating, P-1...Position where a through hole for inserting components is drilled, P-2...Via hole Location to be drilled.

Claims (1)

【特許請求の範囲】 1 予め導体回路パターンを表裏両面に設けた触
媒入りのめつき付着可能な絶縁板の1組をそれぞ
れ最外側に配置し、その内側に触媒入りプリプレ
グ層を配置し、更にその内側に予め多層印刷配線
板の表裏導通用の貫通孔の位置に、その貫通孔の
直径より大なる同心円にくり抜いた孔部を設けた
触媒無し絶縁板を配置し、加熱加圧して前記触媒
無し絶縁板のくり抜き孔部を前記触媒入りプリプ
レグ層から流出した触媒含有樹脂で充填し多層化
基板を形成する工程と、 前記多層化基板の表裏両面に前記表裏導通用の
貫通孔と、内装導体パターン接続用の貫通孔の位
置に一定の逃げを設け、所望の部分に触媒無しの
絶縁樹脂層を被着する工程と、 前記表裏導通用の貫通孔と内層導体パターン接
続用の貫通孔を突設する工程と、 前記多層化基板を無電解めつきし、表裏両面の
触媒無し絶縁樹脂層から露出している部分と、貫
通孔内壁の触媒入り絶縁層に導体層を形成する工
程とを有することを特徴とする多層印刷配線板の
製造方法。
[Scope of Claims] 1. A set of catalyst-containing insulating plates capable of being attached with plating, each having a conductor circuit pattern on both the front and back surfaces, is placed on the outermost side, a catalyst-containing prepreg layer is placed on the inside thereof, and A catalyst-free insulating plate is placed inside the multilayer printed wiring board, and the catalyst-free insulating plate has a concentric hole cut out in a concentric circle larger than the diameter of the through-hole at the position of the through-hole for conduction between the front and back sides of the multilayer printed wiring board. forming a multilayered substrate by filling the hollowed-out hole of the non-insulating plate with the catalyst-containing resin that has flowed out from the catalyst-containing prepreg layer; and forming the through-holes for front and back conduction and the inner conductor on both the front and back surfaces of the multilayered substrate. A step of providing a certain amount of clearance at the position of the through hole for pattern connection and applying an insulating resin layer without a catalyst to the desired part; and a step of electroless plating the multilayered substrate to form a conductor layer on the portions exposed from the catalyst-free insulating resin layer on both the front and back surfaces and the catalyst-containing insulating layer on the inner wall of the through hole. A method for manufacturing a multilayer printed wiring board, characterized by:
JP2936186A 1986-02-12 1986-02-12 Multilayer printed wiring board and manufacture of the same Granted JPS62186594A (en)

Priority Applications (1)

Application Number Priority Date Filing Date Title
JP2936186A JPS62186594A (en) 1986-02-12 1986-02-12 Multilayer printed wiring board and manufacture of the same

Applications Claiming Priority (1)

Application Number Priority Date Filing Date Title
JP2936186A JPS62186594A (en) 1986-02-12 1986-02-12 Multilayer printed wiring board and manufacture of the same

Publications (2)

Publication Number Publication Date
JPS62186594A JPS62186594A (en) 1987-08-14
JPH0542157B2 true JPH0542157B2 (en) 1993-06-25

Family

ID=12274041

Family Applications (1)

Application Number Title Priority Date Filing Date
JP2936186A Granted JPS62186594A (en) 1986-02-12 1986-02-12 Multilayer printed wiring board and manufacture of the same

Country Status (1)

Country Link
JP (1) JPS62186594A (en)

Families Citing this family (6)

* Cited by examiner, † Cited by third party
Publication number Priority date Publication date Assignee Title
JP2582142B2 (en) * 1988-04-27 1997-02-19 日本電信電話株式会社 Matrix switch board, matrix switch board connection pin, and method of manufacturing matrix board
JPH1174651A (en) 1997-03-13 1999-03-16 Ibiden Co Ltd Printed wiring board and its manufacture
JP4482613B2 (en) * 2009-12-24 2010-06-16 新光電気工業株式会社 Manufacturing method of multilayer wiring board
JP5751090B2 (en) 2011-08-22 2015-07-22 ソニー株式会社 Speaker device
US10820427B2 (en) 2013-03-15 2020-10-27 Sanmina Corporation Simultaneous and selective wide gap partitioning of via structures using plating resist
US9781844B2 (en) 2013-03-15 2017-10-03 Sanmina Corporation Simultaneous and selective wide gap partitioning of via structures using plating resist

Citations (2)

* Cited by examiner, † Cited by third party
Publication number Priority date Publication date Assignee Title
JPS5443568A (en) * 1977-09-12 1979-04-06 Fujitsu Ltd Multilayer printed board
JPS5868999A (en) * 1981-10-21 1983-04-25 富士通株式会社 Method of producing multilayer printed circuit board

Patent Citations (2)

* Cited by examiner, † Cited by third party
Publication number Priority date Publication date Assignee Title
JPS5443568A (en) * 1977-09-12 1979-04-06 Fujitsu Ltd Multilayer printed board
JPS5868999A (en) * 1981-10-21 1983-04-25 富士通株式会社 Method of producing multilayer printed circuit board

Also Published As

Publication number Publication date
JPS62186594A (en) 1987-08-14

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