JPH0541499A - Manufacture of semiconductor device - Google Patents
Manufacture of semiconductor deviceInfo
- Publication number
- JPH0541499A JPH0541499A JP3195137A JP19513791A JPH0541499A JP H0541499 A JPH0541499 A JP H0541499A JP 3195137 A JP3195137 A JP 3195137A JP 19513791 A JP19513791 A JP 19513791A JP H0541499 A JPH0541499 A JP H0541499A
- Authority
- JP
- Japan
- Prior art keywords
- film
- polyimide resin
- photosensitive polyimide
- forming
- resin film
- Prior art date
- Legal status (The legal status is an assumption and is not a legal conclusion. Google has not performed a legal analysis and makes no representation as to the accuracy of the status listed.)
- Withdrawn
Links
Classifications
-
- H—ELECTRICITY
- H01—ELECTRIC ELEMENTS
- H01L—SEMICONDUCTOR DEVICES NOT COVERED BY CLASS H10
- H01L2224/00—Indexing scheme for arrangements for connecting or disconnecting semiconductor or solid-state bodies and methods related thereto as covered by H01L24/00
- H01L2224/01—Means for bonding being attached to, or being formed on, the surface to be connected, e.g. chip-to-package, die-attach, "first-level" interconnects; Manufacturing methods related thereto
- H01L2224/10—Bump connectors; Manufacturing methods related thereto
- H01L2224/11—Manufacturing methods
- H01L2224/113—Manufacturing methods by local deposition of the material of the bump connector
- H01L2224/1133—Manufacturing methods by local deposition of the material of the bump connector in solid form
- H01L2224/1134—Stud bumping, i.e. using a wire-bonding apparatus
-
- H—ELECTRICITY
- H01—ELECTRIC ELEMENTS
- H01L—SEMICONDUCTOR DEVICES NOT COVERED BY CLASS H10
- H01L2224/00—Indexing scheme for arrangements for connecting or disconnecting semiconductor or solid-state bodies and methods related thereto as covered by H01L24/00
- H01L2224/01—Means for bonding being attached to, or being formed on, the surface to be connected, e.g. chip-to-package, die-attach, "first-level" interconnects; Manufacturing methods related thereto
- H01L2224/10—Bump connectors; Manufacturing methods related thereto
- H01L2224/11—Manufacturing methods
- H01L2224/1147—Manufacturing methods using a lift-off mask
- H01L2224/11474—Multilayer masks
-
- H—ELECTRICITY
- H01—ELECTRIC ELEMENTS
- H01L—SEMICONDUCTOR DEVICES NOT COVERED BY CLASS H10
- H01L2224/00—Indexing scheme for arrangements for connecting or disconnecting semiconductor or solid-state bodies and methods related thereto as covered by H01L24/00
- H01L2224/01—Means for bonding being attached to, or being formed on, the surface to be connected, e.g. chip-to-package, die-attach, "first-level" interconnects; Manufacturing methods related thereto
- H01L2224/10—Bump connectors; Manufacturing methods related thereto
- H01L2224/11—Manufacturing methods
- H01L2224/1147—Manufacturing methods using a lift-off mask
- H01L2224/1148—Permanent masks, i.e. masks left in the finished device, e.g. passivation layers
Landscapes
- Wire Bonding (AREA)
- Formation Of Insulating Films (AREA)
- Semiconductor Memories (AREA)
Abstract
Description
【０００１】[0001]
【産業上の利用分野】本発明は半導体装置の製造方法に
関する。近年，半導体集積回路は高密度化の傾向にある
が，メモリ回路を有する半導体集積回路においては，α
線照射によるソフトエラーが問題となっている。BACKGROUND OF THE INVENTION 1. Field of the Invention The present invention relates to a method of manufacturing a semiconductor device. In recent years, semiconductor integrated circuits tend to have higher densities, but in semiconductor integrated circuits having memory circuits, α
The soft error caused by the beam irradiation is a problem.
【０００２】α線の発生源として，チップを封止するセ
ラミックパッケージの構成材料であるセラミック材料が
知られている。高速，高密度化に対応した実装方式とし
て，ＴＡＢ(Tape-Automated Bonding)方式や Chip on C
hip を含むＣＣＢ(Controlled Collapse Bonding) 方式
の需要が増加してきており，それに対応してメモリ回路
を有する半導体集積回路上に，金（Ａｕ），半田等の突
出電極（バンプ）を形成することが必要となってきてい
る。As a source of α rays, a ceramic material which is a constituent material of a ceramic package for sealing a chip is known. TAB (Tape-Automated Bonding) method and Chip on C are available as a mounting method for high speed and high density.
The demand for CCB (Controlled Collapse Bonding) method including hips is increasing, and correspondingly, protruding electrodes (bumps) such as gold (Au) and solder can be formed on a semiconductor integrated circuit having a memory circuit. It is needed.
【０００３】図２(a), (b)は金バンプを形成したチップ
の上面図と断面図の例で，(a) は上面図, (b) はＡ−Ａ
断面に沿う断面図であり，１はＳｉ基板，1aはメモリセ
ル,２はＡｌ配線，９は突出電極であって金バンプ，11
は保護膜を表す。2 (a) and 2 (b) are examples of a top view and a cross-sectional view of a chip on which gold bumps are formed. (A) is a top view and (b) is AA.
1 is a Si substrate, 1a is a memory cell, 2 is an Al wiring, 9 is a protruding electrode and is a gold bump, 11
Represents a protective film.
【０００４】ところで，突出電極（バンプ）の構成材料
である金（Ａｕ）あるいは半田もα線の発生源となる。
そこで，保護膜11の一部にα線を減衰，吸収する層を設
けることが行われている。By the way, gold (Au) or solder, which is a constituent material of the protruding electrode (bump), also serves as a source of α rays.
Therefore, a layer that attenuates and absorbs α rays is provided in a part of the protective film 11.
【０００５】[0005]
【従来の技術】図３(a) 〜(e) は従来例を示す工程順断
面図である。以下, これらの図を参照しながら, 従来例
について説明する。2. Description of the Related Art FIGS. 3A to 3E are sectional views in order of steps showing a conventional example. The conventional example will be described below with reference to these drawings.
【０００６】図３(a) 参照 Ｓｉ基板１は素子の形成された基板で，1aはメモリセル
を表す。２は配線で例えばＡｌ配線である。全面に保護
膜としてＰＳＧ膜３を形成する。レジストマスク（図示
せず）を用いてＰＳＧ膜３をエッチングし，バンプ形成
領域に開孔3aを形成する。開孔3aはメモリセル領域外に
ある。See FIG. 3 (a). A Si substrate 1 is a substrate on which elements are formed, and 1a is a memory cell. Reference numeral 2 is a wiring, for example, an Al wiring. A PSG film 3 is formed on the entire surface as a protective film. The PSG film 3 is etched using a resist mask (not shown) to form openings 3a in the bump formation region. The opening 3a is outside the memory cell region.
【０００７】図３(b) 参照 全面に非感光性ポリイミド樹脂を２μｍの厚さに塗布し
て非感光性ポリイミド樹脂膜10を形成し，レジストマス
ク（図示せず）を用いて非感光性ポリイミド樹脂膜10を
エッチングして開孔10a を形成する。See FIG. 3B. A non-photosensitive polyimide resin film 10 is formed by coating a non-photosensitive polyimide resin on the entire surface to a thickness of 2 μm, and a non-photosensitive polyimide is formed using a resist mask (not shown). The resin film 10 is etched to form openings 10a.
【０００８】図３(c) 参照 配線材料であるＡｌとＡｕとの相互拡散を防止するた
め，高融点金属として，例えばＴｉを真空蒸着してＴｉ
膜５を形成し，つづいてＡｕとの密着性強化材料となる
貴金属として，例えばＰｔを真空蒸着してＰｔ膜６を形
成する。Ｔｉ膜５とＰｔ膜６はバリアメタル層となる。See FIG. 3C. In order to prevent mutual diffusion of Al and Au, which are wiring materials, for example, Ti is vacuum-deposited as a refractory metal to form Ti.
The film 5 is formed, and then, as a noble metal that serves as an adhesion enhancing material with Au, for example, Pt is vacuum-deposited to form a Pt film 6. The Ti film 5 and the Pt film 6 become a barrier metal layer.
【０００９】図３(d) 参照 全面にフォトレジスト膜を形成し，それをパターニング
して開孔10a 上に開孔7aを有するレジストマスク７を形
成する。Referring to FIG. 3 (d), a photoresist film is formed on the entire surface and is patterned to form a resist mask 7 having an opening 7a on the opening 10a.
【００１０】開孔10a 底部のバリアメタル層を電流経路
として，その上に電気メッキ法によりＡｕを堆積し，金
メッキ膜８を形成する。 図３(e) 参照 レジストマスク７を除去し，さらに金メッキ膜８をマス
クにしてバリアメタル層をエッチングし除去する。Using the barrier metal layer at the bottom of the opening 10a as a current path, Au is deposited thereon by electroplating to form a gold plating film 8. See FIG. 3E. The resist mask 7 is removed, and the barrier metal layer is etched and removed using the gold plating film 8 as a mask.
【００１１】かくして，非感光性ポリイミド樹脂膜10の
面が露出し，その面から突出する金バンプ９が形成され
る。ところで，この従来法では，非感光性ポリイミド樹
脂膜10の厚さは２μｍとしている。それは開孔10a を形
成する時, 樹脂膜10の厚さが大きいとサイドエッチング
が進んでエッチングシフトが大きくなり，バンプの位置
と寸法の精度が低下し，高集積化の障害となるからであ
る。Thus, the surface of the non-photosensitive polyimide resin film 10 is exposed, and the gold bumps 9 projecting from the surface are formed. By the way, in this conventional method, the thickness of the non-photosensitive polyimide resin film 10 is set to 2 μm. This is because when forming the opening 10a, if the thickness of the resin film 10 is large, side etching progresses and the etching shift becomes large, and the accuracy of the position and size of the bump decreases, which hinders high integration. ..
【００１２】一方，非感光性ポリイミド樹脂膜10の膜厚
が十分でないため，外部のセラミック材料からのα線や
内部のバンプ金属からα線を減衰，吸収する効果が十分
でなく，メモリ回路にソフトエラーを生じるという問題
があった。On the other hand, since the thickness of the non-photosensitive polyimide resin film 10 is not sufficient, the effect of attenuating and absorbing α-rays from the external ceramic material and α-rays from the internal bump metal is not sufficient, so that the memory circuit is not affected. There was a problem of causing a soft error.
【００１３】[0013]
【発明が解決しようとする課題】本発明は上記の問題に
鑑み，外部及び内部からのα線を十分に減衰，吸収し，
しかも寸法精度のよいバンプが形成でき，高集積化に対
処できる半導体装置の製造方法を提供することを目的と
する。In view of the above problems, the present invention sufficiently attenuates and absorbs α-rays from outside and inside,
Moreover, it is an object of the present invention to provide a semiconductor device manufacturing method capable of forming bumps with high dimensional accuracy and coping with high integration.
【００１４】[0014]
【課題を解決するための手段】図１(a) 〜(e) は実施例
を示す工程順断面図である。上記課題は，メモリ回路の
形成された半導体基板１に突出電極９を形成するに際
し, 該半導体基板１上に少なくとも該メモリ回路５形成
領域を覆って展延する感光性ポリイミド樹脂膜４を形成
する工程と, 該感光性ポリイミド樹脂膜４を加工して，
突出電極形成部に開孔4aを形成する工程と, 該開孔4aを
導電体で埋め込んで突出電極９を形成する工程とを有す
る半導体装置の製造方法によって解決される。1 (a) to 1 (e) are sectional views in order of steps showing an embodiment. The above-mentioned problem is to form a photosensitive polyimide resin film 4 that extends over at least the memory circuit 5 forming region on the semiconductor substrate 1 when forming the protruding electrode 9 on the semiconductor substrate 1 on which the memory circuit is formed. Process and processing the photosensitive polyimide resin film 4,
This is solved by the method of manufacturing a semiconductor device, which includes a step of forming the opening 4a in the protruding electrode forming portion and a step of filling the opening 4a with a conductor to form the protruding electrode 9.
【００１５】また，前記感光性ポリイミド樹脂膜４の厚
さを，２８μｍ乃至５０μｍとする半導体装置の製造方
法によって解決される。また，前記感光性ポリイミド樹
脂膜４がエステル結合型感光性ポリイミド樹脂膜である
半導体装置の製造方法によって解決される。Further, it is solved by a method of manufacturing a semiconductor device in which the thickness of the photosensitive polyimide resin film 4 is 28 μm to 50 μm. Further, it is solved by the method of manufacturing a semiconductor device, wherein the photosensitive polyimide resin film 4 is an ester bond type photosensitive polyimide resin film.
【００１６】[0016]
【作用】本発明において，感光性ポリイミド樹脂膜４は
α線を減衰，吸収するために設けられている。感光性ポ
リイミド樹脂膜４は，露光部を現像することにより開孔
4aを形成することができ，非感光性ポリイミド樹脂膜の
ようにマスクを用いてエッチングする必要がないから，
エッチングシフトを生じることもない。In the present invention, the photosensitive polyimide resin film 4 is provided to attenuate and absorb α rays. The photosensitive polyimide resin film 4 is opened by developing the exposed area.
4a can be formed, and it is not necessary to use a mask for etching unlike a non-photosensitive polyimide resin film.
No etching shift occurs.
【００１７】したがって，非感光性ポリイミド樹脂膜を
α線の減衰，吸収の効果が十分なほど厚く形成しても開
孔4aが寸法精度よく形成でき，そこを埋め込む突出電極
９も寸法精度よく形成することができる。Therefore, even if the non-photosensitive polyimide resin film is formed thick enough to attenuate and absorb α rays, the opening 4a can be formed with high dimensional accuracy, and the protruding electrode 9 to be embedded therein can also be formed with high dimensional accuracy. can do.
【００１８】それゆえ，感光性ポリイミド樹脂膜４を用
いれば，外部及び内部からのα線がメモリせるに到達す
るのを遮蔽し，その上突出電極９も寸法精度よく形成す
ることができる。Therefore, by using the photosensitive polyimide resin film 4, it is possible to block the α rays from the outside and the inside from reaching the memory, and the protruding electrode 9 can be formed with high dimensional accuracy.
【００１９】感光性ポリイミド樹脂膜４の厚さは２８μ
ｍ以上あれば，メモリセルにα線によるソフトエラーが
生じない程度の減衰，吸収が可能となる。しかし，感光
性ポリイミド樹脂膜４自身もごく僅かではあるがウラ
ン，トリウム等の放射性元素を含みα線を放射するの
で，感光性ポリイミド樹脂膜４の厚さが５０μｍを超え
ると，メモリセルにソフトエラーが生じる。The thickness of the photosensitive polyimide resin film 4 is 28 μm.
If it is m or more, it is possible to perform attenuation and absorption to the extent that a soft error due to α rays does not occur in the memory cell. However, since the photosensitive polyimide resin film 4 itself contains radioactive elements such as uranium and thorium to emit α rays, although it is very small, when the thickness of the photosensitive polyimide resin film 4 exceeds 50 μm, the memory cell is softened. An error occurs.
【００２０】また，エステル結合型感光性ポリイミド樹
脂膜は，１０μｍ以上の厚い膜に寸法精度のよい開孔4a
が形成できるので，極めて効果的である。Further, the ester bond type photosensitive polyimide resin film is a thick film having a thickness of 10 μm or more, and the opening 4a with good dimensional accuracy is formed.
Can be formed, which is extremely effective.
【００２１】[0021]
【実施例】図１(a) 〜(e) は実施例を示す工程順断面図
である。以下, これらの図を参照しながら，実施例につ
いて説明する。EXAMPLE FIGS. 1A to 1E are sectional views in order of steps showing an example. Examples will be described below with reference to these drawings.
【００２２】図１(a) 参照 Ｓｉ基板１は素子の形成された基板で，1aはメモリセル
を表す。２は配線を表し例えばＡｌ配線であるが，Ａｌ
合金等で形成された多層配線も含む。配線２は後に形成
される突出電極（バンプ）に接続する。See FIG. 1 (a). A Si substrate 1 is a substrate on which elements are formed, and 1a is a memory cell. 2 represents wiring, for example, Al wiring,
It also includes a multi-layer wiring formed of an alloy or the like. The wiring 2 is connected to a protruding electrode (bump) formed later.
【００２３】ブラズマＣＶＤ法により，配線２を覆って
厚さ1.0 μｍのＰＳＧ膜３を形成する。つづいて，全面
にフォトレジストを塗布し，バンプ形成部分とスクライ
ブライン部分に開孔を形成する。その開孔からＣＦ4 系
のガスプラズマによりＰＳＧ膜３をエッチングし，バン
プ形成領域に開孔3aを形成する。開孔3aはメモリセル領
域外にあり，形状は例えば一辺100μｍの正方形であ
る。A PSG film 3 having a thickness of 1.0 μm is formed so as to cover the wiring 2 by the plasma CVD method. Subsequently, photoresist is applied to the entire surface to form openings in the bump formation portion and the scribe line portion. The PSG film 3 is etched from the opening by CF 4 gas plasma to form the opening 3a in the bump formation region. The opening 3a is located outside the memory cell region and has a shape of, for example, a square having a side of 100 μm.
【００２４】図１(b) 参照 全面にエステル結合型感光性ポリイミド樹脂を３０μｍ
の厚さに塗布してエステル結合型感光性ポリイミド樹脂
膜４を形成し，露光マスク（図示せず）を用いてエステ
ル結合型感光性ポリイミド樹脂膜４の露光・現像を行
い，開孔3aを形成した同じ位置に開孔4aを形成する。開
孔4aの形状寸法は開孔3aの形状寸法とほぼ等しく，底部
に配線２を露出する。See FIG. 1 (b). An ester bond type photosensitive polyimide resin is 30 μm on the entire surface.
To form the ester bond type photosensitive polyimide resin film 4, and the ester bond type photosensitive polyimide resin film 4 is exposed and developed using an exposure mask (not shown) to form the opening 3a. The opening 4a is formed at the same position as formed. The shape of the opening 4a is almost the same as the shape of the opening 3a, and the wiring 2 is exposed at the bottom.
【００２５】図１(c) 参照 配線２のＡｌとＡｕとの相互拡散を防止するため，高融
点金属として，例えばＴｉを全面に0.5 μｍの厚さに真
空蒸着してＴｉ膜５を形成し，つづいてＡｕとの密着性
強化材料となる貴金属として，例えばＰｔを全面に0.5
μｍの厚さに真空蒸着してＰｔ膜６を形成する。See FIG. 1C. In order to prevent mutual diffusion of Al and Au of the wiring 2, for example, Ti as a refractory metal is vacuum-deposited to a thickness of 0.5 μm on the entire surface to form a Ti film 5. , Then, as a noble metal that serves as a material for strengthening the adhesion with Au, for example, Pt is 0.5
The Pt film 6 is formed by vacuum evaporation to a thickness of μm.
【００２６】Ｔｉ膜５とＰｔ膜６はバリアメタル層であ
り，この層は配線２上とエステル結合型感光性ポリイミ
ド樹脂膜４上に形成される。 図１(d) 参照 全面に厚さ３０μｍのフォトレジスト膜を形成し，それ
をパターニングして開孔4a上に開孔7aを有するレジスト
マスク７を形成する。開孔7aは開孔4aを含む形状で，例
えば一辺 150μｍの正方形であり，その下部に開孔4aが
連続する開孔が形成される。The Ti film 5 and the Pt film 6 are barrier metal layers, which are formed on the wiring 2 and the ester bond type photosensitive polyimide resin film 4. Referring to FIG. 1D, a photoresist film having a thickness of 30 μm is formed on the entire surface, and is patterned to form a resist mask 7 having an opening 7a on the opening 4a. The opening 7a has a shape including the opening 4a, and is, for example, a square having a side length of 150 μm, and the opening 4a is formed in the lower portion thereof.
【００２７】開孔4aの下のバリアメタル層を電流経路と
して，その上に電気メッキ法によりＡｕを堆積し，金メ
ッキ膜８を形成する。金メッキ膜８のエステル結合型感
光性ポリイミド樹脂膜４面上の高さは，２０〜２５μｍ
である。Using the barrier metal layer below the opening 4a as a current path, Au is deposited thereon by electroplating to form a gold plating film 8. The height of the gold plating film 8 on the surface of the ester bond type photosensitive polyimide resin film 4 is 20 to 25 μm.
Is.
【００２８】図１(e) 参照 レジストマスク７を有機溶剤で除去し，さらに金メッキ
膜８をマスクにしてエステル結合型感光性ポリイミド樹
脂膜４上のバリアメタル層をエッチングして除去する。Referring to FIG. 1 (e), the resist mask 7 is removed with an organic solvent, and the barrier metal layer on the ester bond type photosensitive polyimide resin film 4 is removed by etching using the gold plating film 8 as a mask.
【００２９】かくして，エステル結合型感光性ポリイミ
ド樹脂膜４が露出し，その膜面から２０〜２５μｍの高
さに突出する金バンプ９が形成された。エステル結合型
感光性ポリイミド樹脂膜４は外部からのα線と金バンプ
からのα線を減衰，吸収して，メモリセルにソフトエラ
ーは生じない。Thus, the ester bond type photosensitive polyimide resin film 4 was exposed, and the gold bumps 9 were formed to project from the film surface to a height of 20 to 25 μm. The ester bond type photosensitive polyimide resin film 4 attenuates and absorbs α rays from the outside and α rays from the gold bumps, so that a soft error does not occur in the memory cell.
【００３０】エステル結合型感光性ポリイミド樹脂膜４
の厚さが２８μｍより小さいと，α線の減衰，吸収効果
が十分でなくなり，メモリセルにソフトエラーを生じ
る。また，その厚さが５０μｍを超えると，エステル結
合型感光性ポリイミド樹脂膜４自身のα線放射により，
メモリセルにソフトエラーを生じる。Ester bond type photosensitive polyimide resin film 4
If the thickness is less than 28 μm, the α-ray attenuation and absorption effect becomes insufficient, and a soft error occurs in the memory cell. If the thickness exceeds 50 μm, the α-ray radiation of the ester bond type photosensitive polyimide resin film 4 itself causes
A soft error occurs in the memory cell.
【００３１】なお，上記の実施例では配線２を覆う保護
膜としてＰＳＧ膜３を形成したが，ＰＳＧ膜に替えてＳ
ｉＮ膜を形成してもよい。さらに，ＰＳＧ膜３を形成せ
ずに直接エステル結合型感光性ポリイミド樹脂膜４を形
成してもよい。Although the PSG film 3 is formed as a protective film for covering the wiring 2 in the above embodiment, the PSG film is replaced by S.
An iN film may be formed. Furthermore, the ester bond type photosensitive polyimide resin film 4 may be directly formed without forming the PSG film 3.
【００３２】[0032]
【発明の効果】以上説明したように，本発明によれば，
メモリセルを有する半導体集積回路の形成された基板の
外部（セラミックパッケージ構成材料等）及び内部（バ
ンプ構成材料等）からのα線を減衰，吸収して，メモリ
セルにソフトエラーを生じさせないようにすることがで
きる。As described above, according to the present invention,
Attenuating and absorbing α-rays from outside (ceramic package constituent material, etc.) and inside (bump constituent material, etc.) of a substrate on which a semiconductor integrated circuit having memory cells is formed, so as not to cause a soft error in the memory cell can do.
【００３３】同時に，突出電極（バンプ）を寸法精度よ
く形成することができる。本発明は半導体装置の微細
化，高集積化に寄与するものである。At the same time, the protruding electrodes (bumps) can be formed with high dimensional accuracy. The present invention contributes to miniaturization and high integration of semiconductor devices.
【図１】(a) 〜(e) は実施例を示す工程順断面図であ
る。1A to 1E are cross-sectional views in order of the processes, showing an embodiment.
【図２】(a), (b)は金バンプを形成したチップの上面図
と断面図で, それぞれ，上面図，Ａ−Ａ断面図である。2A and 2B are a top view and a cross-sectional view of a chip on which gold bumps are formed, which are the top view and the AA cross-sectional view, respectively.
【図３】(a) 〜(e) は従来例を示す工程順断面図であ
る。3A to 3E are cross-sectional views in order of the processes, showing a conventional example.
１は半導体基板であってＳｉ基板 1aはメモリセル ２は配線であってＡｌ配線 ３は絶縁膜であってＰＳＧ膜 3aは開孔 ４は感光性ポリイミド樹脂膜であってエステル結合型感
光性ポリイミド樹脂膜 4aは開孔 ５はバリアメタル層であってＴｉ膜 ６はバリアメタル層であってＰｔ膜 ７はレジストマスク 7aは開孔 ８は金メッキ膜 ９は突出電極であって金バンプ 10は非感光性ポリイミド樹脂膜 10a は開孔 11は保護膜Reference numeral 1 is a semiconductor substrate, Si substrate 1a is memory cell 2, wiring is Al wiring 3, PSG film 3a is an opening, 4 is a photosensitive polyimide resin film, ester bond type photosensitive polyimide The resin film 4a has openings 5 as a barrier metal layer, the Ti film 6 as a barrier metal layer, the Pt film 7 as a resist mask 7a as openings 8 as a gold plating film 9 as protruding electrodes, and the gold bumps 10 as non- Photosensitive polyimide resin film 10a has holes 11 is protective film
Claims (3)
に突出電極(9) を形成するに際し, 該半導体基板(1) 上に少なくとも該メモリ回路形成領域
を覆って展延する感光性ポリイミド樹脂膜(4) を形成す
る工程と, 該感光性ポリイミド樹脂膜(4) を加工して，突出電極形
成部に開孔(4a)を形成する工程と, 該開孔(4a)を導電体で埋め込んで突出電極(9) を形成す
る工程とを有することを特徴とする半導体装置の製造方
法。1. A semiconductor substrate (1) on which a memory circuit is formed
A step of forming a photosensitive polyimide resin film (4) extending over at least the memory circuit forming region on the semiconductor substrate (1) when forming the protruding electrode (9) on the semiconductor substrate (1); It has a step of processing the film (4) to form an opening (4a) in the protruding electrode forming portion, and a step of filling the opening (4a) with a conductor to form the protruding electrode (9). A method for manufacturing a semiconductor device, comprising:
を，２８μｍ乃至５０μｍとすることを特徴とする請求
項１記載の半導体装置の製造方法。2. The method for manufacturing a semiconductor device according to claim 1, wherein the photosensitive polyimide resin film (4) has a thickness of 28 μm to 50 μm.
テル結合型感光性ポリイミド樹脂膜であることを特徴と
する請求項２記載の半導体装置の製造方法。3. The method for manufacturing a semiconductor device according to claim 2, wherein the photosensitive polyimide resin film (4) is an ester bond type photosensitive polyimide resin film.
Priority Applications (1)
| Application Number | Priority Date | Filing Date | Title |
|---|---|---|---|
| JP3195137A JPH0541499A (en) | 1991-08-05 | 1991-08-05 | Manufacture of semiconductor device |
Applications Claiming Priority (1)
| Application Number | Priority Date | Filing Date | Title |
|---|---|---|---|
| JP3195137A JPH0541499A (en) | 1991-08-05 | 1991-08-05 | Manufacture of semiconductor device |
Publications (1)
| Publication Number | Publication Date |
|---|---|
| JPH0541499A true JPH0541499A (en) | 1993-02-19 |
Family
ID=16336075
Family Applications (1)
| Application Number | Title | Priority Date | Filing Date |
|---|---|---|---|
| JP3195137A Withdrawn JPH0541499A (en) | 1991-08-05 | 1991-08-05 | Manufacture of semiconductor device |
Country Status (1)
| Country | Link |
|---|---|
| JP (1) | JPH0541499A (en) |
Cited By (1)
| Publication number | Priority date | Publication date | Assignee | Title |
|---|---|---|---|---|
| US7275626B2 (en) | 2002-08-02 | 2007-10-02 | Toto Ltd. | Damper device |
-
1991
- 1991-08-05 JP JP3195137A patent/JPH0541499A/en not_active Withdrawn
Cited By (1)
| Publication number | Priority date | Publication date | Assignee | Title |
|---|---|---|---|---|
| US7275626B2 (en) | 2002-08-02 | 2007-10-02 | Toto Ltd. | Damper device |
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