JPH01286448A - Manufacture of semiconductor device - Google Patents
Manufacture of semiconductor deviceInfo
- Publication number
- JPH01286448A JPH01286448A JP63114651A JP11465188A JPH01286448A JP H01286448 A JPH01286448 A JP H01286448A JP 63114651 A JP63114651 A JP 63114651A JP 11465188 A JP11465188 A JP 11465188A JP H01286448 A JPH01286448 A JP H01286448A
- Authority
- JP
- Japan
- Prior art keywords
- solder
- film
- integrated circuit
- electrode
- wafer
- Prior art date
- Legal status (The legal status is an assumption and is not a legal conclusion. Google has not performed a legal analysis and makes no representation as to the accuracy of the status listed.)
- Pending
Links
- 239000004065 semiconductor Substances 0.000 title claims abstract description 25
- 238000004519 manufacturing process Methods 0.000 title claims description 5
- 229910000679 solder Inorganic materials 0.000 claims abstract description 36
- 239000002184 metal Substances 0.000 claims abstract description 11
- 229910052751 metal Inorganic materials 0.000 claims abstract description 11
- 238000002161 passivation Methods 0.000 claims abstract description 8
- 239000010408 film Substances 0.000 abstract description 22
- 230000005260 alpha ray Effects 0.000 abstract description 13
- 238000000034 method Methods 0.000 abstract description 12
- 239000010409 thin film Substances 0.000 abstract description 12
- 239000011651 chromium Substances 0.000 abstract description 6
- 239000010949 copper Substances 0.000 abstract description 5
- 239000010931 gold Substances 0.000 abstract description 5
- VYZAMTAEIAYCRO-UHFFFAOYSA-N Chromium Chemical compound [Cr] VYZAMTAEIAYCRO-UHFFFAOYSA-N 0.000 abstract description 3
- 229910045601 alloy Inorganic materials 0.000 abstract description 3
- 239000000956 alloy Substances 0.000 abstract description 3
- 229910052804 chromium Inorganic materials 0.000 abstract description 3
- 229910052737 gold Inorganic materials 0.000 abstract description 3
- 238000004544 sputter deposition Methods 0.000 abstract description 3
- RYGMFSIKBFXOCR-UHFFFAOYSA-N Copper Chemical compound [Cu] RYGMFSIKBFXOCR-UHFFFAOYSA-N 0.000 abstract description 2
- 229910052802 copper Inorganic materials 0.000 abstract description 2
- PCHJSUWPFVWCPO-UHFFFAOYSA-N gold Chemical compound [Au] PCHJSUWPFVWCPO-UHFFFAOYSA-N 0.000 abstract description 2
- 230000003247 decreasing effect Effects 0.000 abstract 1
- 230000007423 decrease Effects 0.000 description 5
- 238000005516 engineering process Methods 0.000 description 5
- 229920001721 polyimide Polymers 0.000 description 5
- 239000009719 polyimide resin Substances 0.000 description 5
- 230000015572 biosynthetic process Effects 0.000 description 3
- 230000000694 effects Effects 0.000 description 3
- 239000011521 glass Substances 0.000 description 3
- 230000015654 memory Effects 0.000 description 3
- 230000001681 protective effect Effects 0.000 description 3
- 230000002285 radioactive effect Effects 0.000 description 3
- VYPSYNLAJGMNEJ-UHFFFAOYSA-N silicon dioxide Inorganic materials O=[Si]=O VYPSYNLAJGMNEJ-UHFFFAOYSA-N 0.000 description 3
- ATJFFYVFTNAWJD-UHFFFAOYSA-N Tin Chemical compound [Sn] ATJFFYVFTNAWJD-UHFFFAOYSA-N 0.000 description 2
- 238000010521 absorption reaction Methods 0.000 description 2
- 238000005530 etching Methods 0.000 description 2
- 229910052814 silicon oxide Inorganic materials 0.000 description 2
- 229910052770 Uranium Inorganic materials 0.000 description 1
- 230000005262 alpha decay Effects 0.000 description 1
- 238000000151 deposition Methods 0.000 description 1
- 230000007257 malfunction Effects 0.000 description 1
- 239000000463 material Substances 0.000 description 1
- 150000002739 metals Chemical class 0.000 description 1
- 238000004806 packaging method and process Methods 0.000 description 1
- 239000008188 pellet Substances 0.000 description 1
- 239000010453 quartz Substances 0.000 description 1
- 229910052705 radium Inorganic materials 0.000 description 1
- HCWPIIXVSYCSAN-UHFFFAOYSA-N radium atom Chemical compound [Ra] HCWPIIXVSYCSAN-UHFFFAOYSA-N 0.000 description 1
- 238000012827 research and development Methods 0.000 description 1
- 239000000758 substrate Substances 0.000 description 1
- JFALSRSLKYAFGM-UHFFFAOYSA-N uranium(0) Chemical compound [U] JFALSRSLKYAFGM-UHFFFAOYSA-N 0.000 description 1
- 238000007740 vapor deposition Methods 0.000 description 1
Classifications
-
- H—ELECTRICITY
- H01—ELECTRIC ELEMENTS
- H01L—SEMICONDUCTOR DEVICES NOT COVERED BY CLASS H10
- H01L23/00—Details of semiconductor or other solid state devices
- H01L23/552—Protection against radiation, e.g. light or electromagnetic waves
- H01L23/556—Protection against radiation, e.g. light or electromagnetic waves against alpha rays
-
- H—ELECTRICITY
- H01—ELECTRIC ELEMENTS
- H01L—SEMICONDUCTOR DEVICES NOT COVERED BY CLASS H10
- H01L2224/00—Indexing scheme for arrangements for connecting or disconnecting semiconductor or solid-state bodies and methods related thereto as covered by H01L24/00
- H01L2224/01—Means for bonding being attached to, or being formed on, the surface to be connected, e.g. chip-to-package, die-attach, "first-level" interconnects; Manufacturing methods related thereto
- H01L2224/02—Bonding areas; Manufacturing methods related thereto
- H01L2224/04—Structure, shape, material or disposition of the bonding areas prior to the connecting process
- H01L2224/0401—Bonding areas specifically adapted for bump connectors, e.g. under bump metallisation [UBM]
-
- H—ELECTRICITY
- H01—ELECTRIC ELEMENTS
- H01L—SEMICONDUCTOR DEVICES NOT COVERED BY CLASS H10
- H01L2224/00—Indexing scheme for arrangements for connecting or disconnecting semiconductor or solid-state bodies and methods related thereto as covered by H01L24/00
- H01L2224/01—Means for bonding being attached to, or being formed on, the surface to be connected, e.g. chip-to-package, die-attach, "first-level" interconnects; Manufacturing methods related thereto
- H01L2224/02—Bonding areas; Manufacturing methods related thereto
- H01L2224/04—Structure, shape, material or disposition of the bonding areas prior to the connecting process
- H01L2224/05—Structure, shape, material or disposition of the bonding areas prior to the connecting process of an individual bonding area
- H01L2224/0554—External layer
- H01L2224/0556—Disposition
- H01L2224/05571—Disposition the external layer being disposed in a recess of the surface
- H01L2224/05572—Disposition the external layer being disposed in a recess of the surface the external layer extending out of an opening
-
- H—ELECTRICITY
- H01—ELECTRIC ELEMENTS
- H01L—SEMICONDUCTOR DEVICES NOT COVERED BY CLASS H10
- H01L2224/00—Indexing scheme for arrangements for connecting or disconnecting semiconductor or solid-state bodies and methods related thereto as covered by H01L24/00
- H01L2224/01—Means for bonding being attached to, or being formed on, the surface to be connected, e.g. chip-to-package, die-attach, "first-level" interconnects; Manufacturing methods related thereto
- H01L2224/10—Bump connectors; Manufacturing methods related thereto
- H01L2224/11—Manufacturing methods
-
- H—ELECTRICITY
- H01—ELECTRIC ELEMENTS
- H01L—SEMICONDUCTOR DEVICES NOT COVERED BY CLASS H10
- H01L2224/00—Indexing scheme for arrangements for connecting or disconnecting semiconductor or solid-state bodies and methods related thereto as covered by H01L24/00
- H01L2224/01—Means for bonding being attached to, or being formed on, the surface to be connected, e.g. chip-to-package, die-attach, "first-level" interconnects; Manufacturing methods related thereto
- H01L2224/10—Bump connectors; Manufacturing methods related thereto
- H01L2224/12—Structure, shape, material or disposition of the bump connectors prior to the connecting process
-
- H—ELECTRICITY
- H01—ELECTRIC ELEMENTS
- H01L—SEMICONDUCTOR DEVICES NOT COVERED BY CLASS H10
- H01L2224/00—Indexing scheme for arrangements for connecting or disconnecting semiconductor or solid-state bodies and methods related thereto as covered by H01L24/00
- H01L2224/01—Means for bonding being attached to, or being formed on, the surface to be connected, e.g. chip-to-package, die-attach, "first-level" interconnects; Manufacturing methods related thereto
- H01L2224/10—Bump connectors; Manufacturing methods related thereto
- H01L2224/12—Structure, shape, material or disposition of the bump connectors prior to the connecting process
- H01L2224/13—Structure, shape, material or disposition of the bump connectors prior to the connecting process of an individual bump connector
- H01L2224/13001—Core members of the bump connector
- H01L2224/13005—Structure
- H01L2224/13007—Bump connector smaller than the underlying bonding area, e.g. than the under bump metallisation [UBM]
-
- H—ELECTRICITY
- H01—ELECTRIC ELEMENTS
- H01L—SEMICONDUCTOR DEVICES NOT COVERED BY CLASS H10
- H01L2224/00—Indexing scheme for arrangements for connecting or disconnecting semiconductor or solid-state bodies and methods related thereto as covered by H01L24/00
- H01L2224/01—Means for bonding being attached to, or being formed on, the surface to be connected, e.g. chip-to-package, die-attach, "first-level" interconnects; Manufacturing methods related thereto
- H01L2224/10—Bump connectors; Manufacturing methods related thereto
- H01L2224/15—Structure, shape, material or disposition of the bump connectors after the connecting process
- H01L2224/16—Structure, shape, material or disposition of the bump connectors after the connecting process of an individual bump connector
-
- H—ELECTRICITY
- H01—ELECTRIC ELEMENTS
- H01L—SEMICONDUCTOR DEVICES NOT COVERED BY CLASS H10
- H01L24/00—Arrangements for connecting or disconnecting semiconductor or solid-state bodies; Methods or apparatus related thereto
- H01L24/01—Means for bonding being attached to, or being formed on, the surface to be connected, e.g. chip-to-package, die-attach, "first-level" interconnects; Manufacturing methods related thereto
- H01L24/02—Bonding areas ; Manufacturing methods related thereto
- H01L24/03—Manufacturing methods
-
- H—ELECTRICITY
- H01—ELECTRIC ELEMENTS
- H01L—SEMICONDUCTOR DEVICES NOT COVERED BY CLASS H10
- H01L24/00—Arrangements for connecting or disconnecting semiconductor or solid-state bodies; Methods or apparatus related thereto
- H01L24/01—Means for bonding being attached to, or being formed on, the surface to be connected, e.g. chip-to-package, die-attach, "first-level" interconnects; Manufacturing methods related thereto
- H01L24/02—Bonding areas ; Manufacturing methods related thereto
- H01L24/04—Structure, shape, material or disposition of the bonding areas prior to the connecting process
- H01L24/05—Structure, shape, material or disposition of the bonding areas prior to the connecting process of an individual bonding area
-
- H—ELECTRICITY
- H01—ELECTRIC ELEMENTS
- H01L—SEMICONDUCTOR DEVICES NOT COVERED BY CLASS H10
- H01L24/00—Arrangements for connecting or disconnecting semiconductor or solid-state bodies; Methods or apparatus related thereto
- H01L24/01—Means for bonding being attached to, or being formed on, the surface to be connected, e.g. chip-to-package, die-attach, "first-level" interconnects; Manufacturing methods related thereto
- H01L24/10—Bump connectors ; Manufacturing methods related thereto
- H01L24/12—Structure, shape, material or disposition of the bump connectors prior to the connecting process
- H01L24/13—Structure, shape, material or disposition of the bump connectors prior to the connecting process of an individual bump connector
-
- H—ELECTRICITY
- H01—ELECTRIC ELEMENTS
- H01L—SEMICONDUCTOR DEVICES NOT COVERED BY CLASS H10
- H01L2924/00—Indexing scheme for arrangements or methods for connecting or disconnecting semiconductor or solid-state bodies as covered by H01L24/00
- H01L2924/10—Details of semiconductor or other solid state devices to be connected
- H01L2924/11—Device type
- H01L2924/14—Integrated circuits
Landscapes
- Physics & Mathematics (AREA)
- Health & Medical Sciences (AREA)
- Electromagnetism (AREA)
- Toxicology (AREA)
- Condensed Matter Physics & Semiconductors (AREA)
- General Physics & Mathematics (AREA)
- Engineering & Computer Science (AREA)
- Computer Hardware Design (AREA)
- Microelectronics & Electronic Packaging (AREA)
- Power Engineering (AREA)
- Internal Circuitry In Semiconductor Integrated Circuit Devices (AREA)
- Formation Of Insulating Films (AREA)
Abstract
Description
【発明の詳細な説明】
〔産業上の利用分野〕
本発明は、半導体装置の製造技術に関し、特に半田バン
プを有する半導体装置のソフトエラー防止に適用して有
効な技術に関するものである。DETAILED DESCRIPTION OF THE INVENTION [Field of Industrial Application] The present invention relates to a technology for manufacturing semiconductor devices, and particularly to a technology that is effective when applied to prevent soft errors in semiconductor devices having solder bumps.
近年、半導体装置の高密度実装方式として、集積回路を
形成した半導体ウェハ（以下、ウェハという）の電極上
に半田バンプ（突起電極）を形成し、この半田バンプを
介して半導体ペレットを実装基板に搭載する、いわゆる
フリップチップが活用されている。In recent years, as a high-density packaging method for semiconductor devices, solder bumps (protruding electrodes) are formed on the electrodes of a semiconductor wafer (hereinafter referred to as wafer) on which integrated circuits are formed, and semiconductor pellets are transferred to the mounting board via the solder bumps. The so-called flip chip installed on the device is utilized.
ウェハの電極上に半田バンプを形成するには、例えばＩ
ＢＭ社発行、ｒｌＢＭジャーナル・オブ・リサーチ・ア
ンド・ディベロップメント（１８ＭＪｏｕｒｎａｌ
ｏｆ Ｒｅ５ｅａｃｈ ａｎｄ Ｄｅｖｅｌｏｐ
Ｉｌｅｎｔ）、 ｌ ３ 巻。To form solder bumps on the electrodes of the wafer, for example I
Published by BM, rlBM Journal of Research and Development (18MJournal
of Re5each and Develop
Ilent), Volume 3.
漱３ＪＰ２３９〜Ｐ２５０に記載があるように、Ａｌ電
極パッドの表面にクロム（Ｃｒ）／１４（Ｃ電極（ＢＬ
Ｍ）を蒸着法で形成し、その表面にスズ（Ｓｎ）−鉛（
Ｐｂ）合金からなる半田膜を選択的に蒸着した後、この
半田膜をリフロー炉内でウェットバックして半球状の半
田バンプを得る方法が用いられている。As described in Sou 3 JP239-P250, chromium (Cr)/14 (C electrode (BL
M) is formed by vapor deposition, and tin (Sn)-lead (
A method is used in which a solder film made of a Pb) alloy is selectively deposited and then wet-backed in a reflow oven to obtain hemispherical solder bumps.
一方、半導体装置の高集積化に伴い、特に半導体メモリ
においてソフトエラーの対策が重要な課題となっている
。On the other hand, as semiconductor devices become more highly integrated, countermeasures against soft errors have become an important issue, especially in semiconductor memories.
すなわち、半導体集積回路が微細化され、メモリセルあ
たりの蓄積電荷量が微小になって（ると、集積回路を構
成する材料やパッケージ材料中に含まれた微量の放射性
同位元素から放射されるα線が基板に入射する際に発生
する電子正孔対によってメモリセルの蓄積電荷が失われ
、回路の誤動作が生じ易くなる。In other words, as semiconductor integrated circuits are miniaturized and the amount of accumulated charge per memory cell becomes minute, the Electron-hole pairs generated when the line is incident on the substrate cause the stored charge in the memory cell to be lost, making the circuit more likely to malfunction.
従来、パッケージ材料中に含まれている放射性同位元素
から放射されるα線を遮蔽するには、例えば、特公昭５
５−６８６５９号公報や特公昭６０−１５１５２号公報
などに記載があるように、集積回路の表面を保護するパ
ッシベーション膜上にポリイミド樹脂からなるαｓＢ蔽
用薄膜をコーティングする方法が用いられている。Conventionally, in order to shield alpha rays emitted from radioactive isotopes contained in package materials, for example,
As described in Japanese Patent Publication No. 5-68659 and Japanese Patent Publication No. 60-15152, a method is used in which an αsB shielding thin film made of polyimide resin is coated on a passivation film that protects the surface of an integrated circuit.
ところが、本発明者の検討によれば、上記従来技術は、
α線遮蔽用ポリイミド樹脂のエツチングレートが低いた
めにＡｌ電極パッド上に前記半田バンプを形成する工程
のスループットが低下するという欠点を有している。However, according to the inventor's study, the above conventional technology
Since the etching rate of the α-ray shielding polyimide resin is low, the throughput of the step of forming the solder bumps on the Al electrode pads is reduced.
上記α線遮蔽用ポリイミド樹脂は、集積回路が微細化す
る程厚膜化する必要があるため、半導体装置の高集積化
とともに半田バンプ形成工程のスルーブツト低下が深刻
になる。The α-ray shielding polyimide resin needs to be made thicker as the integrated circuit becomes finer, so as semiconductor devices become more highly integrated, the throughput of the solder bump forming process becomes seriously reduced.
また一方で、ポリイミド樹脂は、その耐湿性が乏シいた
め、パッシベーション膜上にコーティングされたα線遮
蔽用ポリイミド樹脂の吸湿が原因となって半導体装置の
信頼性が低下してしまうという間頚も生じている。On the other hand, polyimide resin has poor moisture resistance, so there is a problem that the reliability of semiconductor devices decreases due to moisture absorption of the α-ray shielding polyimide resin coated on the passivation film. It is occurring.
本発明の目的は、半田バンプを介して半導体ベレットを
実装基板に搭載する方式の半導体装置において、半田バ
ンプ形成工程のスループットを低下させることなくソフ
トエラーを有効に防止することのできる技術を提供する
ことにある。An object of the present invention is to provide a technology that can effectively prevent soft errors without reducing the throughput of the solder bump forming process in a semiconductor device in which a semiconductor bullet is mounted on a mounting board via solder bumps. There is a particular thing.
また、本発明の他の目的は、α線遮蔽用薄膜の吸湿に起
因する半導体装置の信頼性低下を有効に防止することの
できる技術を提供することにある。Another object of the present invention is to provide a technique that can effectively prevent a decrease in reliability of a semiconductor device due to moisture absorption of an α-ray shielding thin film.
本発明の前記並びにその他の目的と新規な特徴は、本明
細書の記述および添付図面から明らかになるであろう。The above and other objects and novel features of the present invention will become apparent from the description of this specification and the accompanying drawings.
本願において開示される発明のうち代表的なものの概要
を簡単に説明すれば、次の通りである。A brief overview of typical inventions disclosed in this application is as follows.
すなわち、ウェハの電極上に半田バンプを形成する際、
パッシベーション膜上に被着した半田下地電極用金属膜
の一部を集積回路形成領域の上方に残し、これをα線遮
蔽用薄膜として用いるものである。That is, when forming solder bumps on the electrodes of the wafer,
A part of the metal film for the solder base electrode deposited on the passivation film is left above the integrated circuit formation area, and this is used as a thin film for shielding alpha rays.
上記した手段によれば、パッシベーション膜上に別途α
線遮蔽用薄膜を被着する工程が不要となるので、半田バ
ンプ形成工程のスルーブツトを低下させることなくソフ
トエラーを防止することが可能となる。According to the above-mentioned means, α is separately added on the passivation film.
Since the process of depositing a line-shielding thin film is not necessary, it is possible to prevent soft errors without reducing the throughput of the solder bump forming process.
また、α線ｆｌ蔽用Ｍ膜が吸湿性のない金属で構成され
るので、半導体装置の信頼性低下を有効に防止すること
ができる。Further, since the α-ray fl shielding M film is made of a non-hygroscopic metal, it is possible to effectively prevent a decrease in the reliability of the semiconductor device.
第１図（ａ）〜（Ｃ）は、本発明の一実施例である半導
体装置の製造方法を示すウェハの要部断面図である。FIGS. 1A to 1C are cross-sectional views of essential parts of a wafer showing a method for manufacturing a semiconductor device according to an embodiment of the present invention.
まず、ウェハプロセスの常法に従い、シリコン単結晶か
らなるウェハ１の集積回路形成領域に所定の集積回路（
図示せず）を形成し、石英スパッタ法などを用いてウェ
ハ１の表面にガラス保護膜（パッシベーション膜）２を
被着する。First, according to the usual method of wafer processing, a predetermined integrated circuit (
(not shown), and a glass protective film (passivation film) 2 is deposited on the surface of the wafer 1 using a quartz sputtering method or the like.
次いで、レジストマスクを用いたエツチングでガラス保
護膜２の所定箇所の孔開けを行い、シリコン酸化膜３の
表面にパターン形成されたＡβ配線の一部を露出して、
Ａｌ電極バッド４を形成する（第１図（ａ））。Next, holes are formed at predetermined locations in the glass protective film 2 by etching using a resist mask, and a part of the Aβ wiring patterned on the surface of the silicon oxide film 3 is exposed.
An Al electrode pad 4 is formed (FIG. 1(a)).
次に、スパッタ法などを用いてウェハ１の表面に、例え
ばクロム（Ｃｒ）、銅（Ｃｕ）および金（Ａｕ）の薄膜
を順次被着し、レジストマスクを用いてこれらの薄膜の
エツチングを行い、Ａ １ ｉｔ。Next, thin films of, for example, chromium (Cr), copper (Cu), and gold (Au) are sequentially deposited on the surface of the wafer 1 using a sputtering method or the like, and these thin films are etched using a resist mask. , A 1 it.
極パッド４の゛表面に半田下地電極５を形成するととも
に、併せて集積回路形成領域の上方にα線遮蔽層６を形
成する（第１図（ｂ））。A solder base electrode 5 is formed on the surface of the pole pad 4, and at the same time, an α-ray shielding layer 6 is formed above the integrated circuit forming area (FIG. 1(b)).
上記半田下地電極５およびα線遮蔽層６に用いるＣｒ５
Ｃｕ％Ａｕなどの金属は、それ自体に放射性同位元素が
含まれていないことが要求されるため、少なくともウラ
ン（Ｕ）、）リウム（Ｔｈ）あるいはラジウム（Ｒａ）
などのようなα崩壊形放射性同位元素の含有率が０．５
ｐ ｐ ｂ以下となるまで精製した高純度金属を用い
るのがよい。Cr5 used for the solder base electrode 5 and α-ray shielding layer 6
Metals such as Cu%Au are required to contain no radioactive isotopes, so they contain at least uranium (U), ) lium (Th) or radium (Ra).
The content of α-decay radioactive isotopes such as 0.5
It is preferable to use a high purity metal that has been refined to a p p b or less.
次に、メタルまたはレジストからなるマスクを用いてス
ズ（Ｓｎ）−鉛（Ｐｂ）合金からなる半田膜を半田下地
電極５０表面に選択的に被着した後、この半田膜をリフ
ロー炉内でウェットバックして半球状の半田バンプ７を
形成する（第１図（Ｃ））。Next, a solder film made of a tin (Sn)-lead (Pb) alloy is selectively deposited on the surface of the solder base electrode 50 using a mask made of metal or resist, and then this solder film is wetted in a reflow oven. Backing is performed to form hemispherical solder bumps 7 (FIG. 1(C)).
このように、ウェハｌの表面に被着した金属薄膜で半田
下地電極５およびα線遮蔽層６を同時に形成する本実施
例によれば、別途α線遮蔽層を形成する工程が不要とな
るので、半田パンプ７を形成する工程のスループットを
低下させることなくソフトエラーを防止することが可能
となる。As described above, according to this embodiment in which the solder base electrode 5 and the α-ray shielding layer 6 are simultaneously formed with the metal thin film adhered to the surface of the wafer l, a separate step of forming an α-ray shielding layer is not necessary. , it becomes possible to prevent soft errors without reducing the throughput of the step of forming the solder pumps 7.
また、α線遮蔽層６を吸湿性のない金属で構成したので
、半導体装置の信頼性低下を有効に防止することができ
る。Further, since the α-ray shielding layer 6 is made of a non-hygroscopic metal, it is possible to effectively prevent a decrease in the reliability of the semiconductor device.
以上、本発明者によってなされた発明を実施例に基づき
具体的に説明したが、本発明は、前記実施例に限定され
るものではなく、その要旨を逸脱しない範囲で種々変更
可能であること１さいうまでもない。Although the invention made by the present inventor has been specifically explained based on Examples above, the present invention is not limited to the above-mentioned Examples, and can be modified in various ways without departing from the gist of the invention. Needless to say.
本願において開示される発明のうち代表的なものによっ
て得られる効果を簡単に説明すれば、下記の通りである
。A brief explanation of the effects obtained by typical inventions disclosed in this application is as follows.
すなわち、ウェハの電極上に半田バンプを形成する際、
パフシベーシａン膜上に被着した半田下地電極用金属膜
の一部を集積回路形成領域の上方に残し、これをα線遮
蔽用薄膜として用いることにより、別途α線遮蔽用薄膜
を形成する工程が不要となるので、半田バンプ形成、工
程のスループットを低下させることなくソフトエラーを
防止することが可能となる。That is, when forming solder bumps on the electrodes of the wafer,
A step of separately forming a thin film for shielding α-rays by leaving a part of the metal film for the solder base electrode deposited on the puff-shield A film above the integrated circuit formation area and using this as a thin film for shielding α-rays. Since this eliminates the need for solder bump formation, soft errors can be prevented without reducing the throughput of the process.
また、α線遮蔽用薄膜が吸湿性のない金属で構成される
ので、半導体装置の信頼性低下をを効に防止することが
できる。Furthermore, since the α-ray shielding thin film is made of a non-hygroscopic metal, it is possible to effectively prevent a decrease in the reliability of the semiconductor device.
第１図（ａ）〜（Ｃ）は本発明の一実施例である半導体
装置の製造方法を示す半導体ウェハの要部断面図である
。
１・・・半導体ウェハ、２・・・ガラス保護膜（パッシ
ベーション膜）、３・・・シリコン酸化膜、４・・・Ａ
Ｉ電極パッド、５・・・半田下地電極、６・・・α線遮
蔽層、７・・・半田パンプ。
第１図FIGS. 1A to 1C are cross-sectional views of essential parts of a semiconductor wafer showing a method of manufacturing a semiconductor device according to an embodiment of the present invention. 1... Semiconductor wafer, 2... Glass protective film (passivation film), 3... Silicon oxide film, 4... A
I electrode pad, 5... solder base electrode, 6... alpha ray shielding layer, 7... solder pump. Figure 1
Claims (1)
に半田下地電極を介して半田バンプを形成するに際し、
前記半導体ウェハのパッシベーション膜上に被着した半
田下地電極用金属膜の一部を集積回路形成領域の上方に
残すことを特徴とする半導体装置の製造方法。1. When forming solder bumps on the electrodes of a semiconductor wafer on which a predetermined integrated circuit is formed, via a solder base electrode,
A method of manufacturing a semiconductor device, characterized in that a part of the metal film for a solder base electrode deposited on the passivation film of the semiconductor wafer is left above an integrated circuit forming area.
Priority Applications (1)
| Application Number | Priority Date | Filing Date | Title |
|---|---|---|---|
| JP63114651A JPH01286448A (en) | 1988-05-13 | 1988-05-13 | Manufacture of semiconductor device |
Applications Claiming Priority (1)
| Application Number | Priority Date | Filing Date | Title |
|---|---|---|---|
| JP63114651A JPH01286448A (en) | 1988-05-13 | 1988-05-13 | Manufacture of semiconductor device |
Publications (1)
| Publication Number | Publication Date |
|---|---|
| JPH01286448A true JPH01286448A (en) | 1989-11-17 |
Family
ID=14643141
Family Applications (1)
| Application Number | Title | Priority Date | Filing Date |
|---|---|---|---|
| JP63114651A Pending JPH01286448A (en) | 1988-05-13 | 1988-05-13 | Manufacture of semiconductor device |
Country Status (1)
| Country | Link |
|---|---|
| JP (1) | JPH01286448A (en) |
Cited By (8)
| Publication number | Priority date | Publication date | Assignee | Title |
|---|---|---|---|---|
| JPH05136202A (en) * | 1991-05-11 | 1993-06-01 | Goldstar Electron Co Ltd | Semiconductor package and manufacture thereof |
| JPH05235000A (en) * | 1991-12-17 | 1993-09-10 | Internatl Business Mach Corp <Ibm> | Apparatus and method for reducing alpha particles |
| US6285079B1 (en) | 1998-06-02 | 2001-09-04 | Mitsubishi Denki Kabushiki Kaisha | Semiconductor device employing grid array electrodes and compact chip-size package |
| WO2004034450A1 (en) * | 2002-10-11 | 2004-04-22 | Tm Tech Co., Ltd. | A sputtering apparatus having enhanced adhesivity of particles and a manufacturing method thereof |
| WO2004055873A1 (en) * | 2002-12-14 | 2004-07-01 | Tm Tech Co., Ltd. | Thin film forming apparatus |
| EP1908105A2 (en) * | 2005-07-18 | 2008-04-09 | International Business Machines Corporation | Method and structure for reduction of soft error rates in integrated circuits |
| WO2011062666A1 (en) * | 2009-11-23 | 2011-05-26 | Xilinx, Inc. | Extended under-bump metal layer for blocking alpha particles in a semiconductor device |
| US9444399B2 (en) | 2014-07-25 | 2016-09-13 | Seiko Epson Corporation | Semiconductor circuit device, electronic apparatus, and moving object |
-
1988
- 1988-05-13 JP JP63114651A patent/JPH01286448A/en active Pending
Cited By (10)
| Publication number | Priority date | Publication date | Assignee | Title |
|---|---|---|---|---|
| JPH05136202A (en) * | 1991-05-11 | 1993-06-01 | Goldstar Electron Co Ltd | Semiconductor package and manufacture thereof |
| JPH05235000A (en) * | 1991-12-17 | 1993-09-10 | Internatl Business Mach Corp <Ibm> | Apparatus and method for reducing alpha particles |
| US6285079B1 (en) | 1998-06-02 | 2001-09-04 | Mitsubishi Denki Kabushiki Kaisha | Semiconductor device employing grid array electrodes and compact chip-size package |
| WO2004034450A1 (en) * | 2002-10-11 | 2004-04-22 | Tm Tech Co., Ltd. | A sputtering apparatus having enhanced adhesivity of particles and a manufacturing method thereof |
| WO2004055873A1 (en) * | 2002-12-14 | 2004-07-01 | Tm Tech Co., Ltd. | Thin film forming apparatus |
| EP1908105A2 (en) * | 2005-07-18 | 2008-04-09 | International Business Machines Corporation | Method and structure for reduction of soft error rates in integrated circuits |
| EP1908105A4 (en) * | 2005-07-18 | 2012-08-22 | Ibm | Method and structure for reduction of soft error rates in integrated circuits |
| WO2011062666A1 (en) * | 2009-11-23 | 2011-05-26 | Xilinx, Inc. | Extended under-bump metal layer for blocking alpha particles in a semiconductor device |
| US8410605B2 (en) | 2009-11-23 | 2013-04-02 | Xilinx, Inc. | Extended under-bump metal layer for blocking alpha particles in a semiconductor device |
| US9444399B2 (en) | 2014-07-25 | 2016-09-13 | Seiko Epson Corporation | Semiconductor circuit device, electronic apparatus, and moving object |
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