CN100514589C - Wafer level packaging method and its structure - Google Patents
Wafer level packaging method and its structure Download PDFInfo
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- CN100514589C CN100514589C CN 200610080134 CN200610080134A CN100514589C CN 100514589 C CN100514589 C CN 100514589C CN 200610080134 CN200610080134 CN 200610080134 CN 200610080134 A CN200610080134 A CN 200610080134A CN 100514589 C CN100514589 C CN 100514589C
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- H—ELECTRICITY
- H01—ELECTRIC ELEMENTS
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- Internal Circuitry In Semiconductor Integrated Circuit Devices (AREA)
- Semiconductor Integrated Circuits (AREA)
Abstract
The invention is an integrated wafer packaging structure, comprising a chip, at least a passive component, an interface layer, an insulating layer, at least a connection, an internal connecting pad and a protection layer, where the chip comprises a surface connecting pad, an internal connecting pad and a circuit component, the passive component is formed on one side of the chip, the interface layer increases the bond between the passive component and the chip, the insulating layer covers part of the surface on the other side of the chip, the connection covers part of the surface of the insulating layer and the internal connecting pad and is used to connect with the internal connecting pad, and the protection layer is used to protect the chip.
Description
Technical field
The present invention relates to a kind of integrated packaging process, especially refer to a kind of integrated wafer-level packaging process, this method can form at least one passive device with effective minimizing encapsulation volume and system bulk and reduce and carry out the outside with passive device and be connected signal attenuation and the failure problems that is caused in encapsulating structure.
Background technology
The packaged type of integrated circuit is broadly divided into pin and inserts and surface mount two class modes through development for a long time.The surface mount mode is finished with substrate by metal pad and is electrically connected.
In the evolution of surface mount mode, increase day by day along with substrate circuit integration degree, develop and many method for packing, for example naked crystalline substance and wafer-level package (the chipscale package of packaging body area ratio less than 1: 5, CSP), CSP often realizes by fine pitch BGA Package (fine pinch ballgrid array) or flip-chip (flip chip) mode.Existing Flip-Chip Using technological development goes out many variations, no matter why it changes, Flip-Chip Using technology all need utilize wafer frontside to be electrically connected, for example the United States Patent (USP) certificate number 5,720,100, the United States Patent (USP) certificate number 6,074,895 and United States Patent (USP) certificate number 6,372, in 544, all disclose above-mentioned flip chip structure, therefore, needed to use the semiconductor structure of wafer frontside, for example photoinduction element (common is CMOS or CCD structure), pressure responsive element and temperature sensitive member etc. all can't utilize Flipchip method to encapsulate.
Simultaneously, naked crystalline substance and wafer-level packaging (the wafer level chip scale package of packaging body area ratio near 1: 1, WLCSP) method also is developed, and WLCSP utilizes wafer two surfaces and side to encapsulate simultaneously, makes encapsulation volume further be dwindled.
On the other hand, for reducing the electronic system volume, reduce each element in the circuit board by the loss of signal that adds the side connecting conductor formula and caused with make an uproar news, and reduce the bad fault probability that causes of each connecting line, also develop and to utilize the semiconductor fabrication process mode, the conformability technology of integrated passive element in semiconductor package, but it often need increase technology separately in order to form passive device, complex process not only also increases the failure problems of encapsulating structure.
Therefore, a kind of being able to when carrying out wafer-level packaging, integrated passive element with the integration by passive device, dwindles the area of whole system and promotes the integrated packaging technology and the structure of reliability in described encapsulating structure, is very necessary.
Summary of the invention
Main purpose of the present invention provides a kind of integrated packaging process, and this method can form at least one passive device and effectively reduce encapsulation volume in an encapsulating structure.
Another object of the present invention provides a kind of integrated packaging process, and this method utilizes the wafer positive and negative to encapsulate respectively, in order to effective reduction encapsulation volume and area.
Another object of the present invention is for providing a kind of integrated packaging process, and this method is utilized BCB, Polyimide or other equivalent electric barrier material, finishes the isolated and protective layer combination of wafer electricity simultaneously.
Another object of the present invention is for providing an encapsulating structure, and this encapsulating structure integrated passive element is on crystal circle structure, in order to reduce problem of signal attenuation and can significantly reduce the area of described encapsulating structure institute imbedding system.
Another object of the present invention is for providing an encapsulating structure, and this structure comprises the packaging protection layer in order to protection to be provided, and makes described structure when defective workmanship takes place, and is easier to independently carry out heavy industry to increase the manufacturing process rate of finished products.
Another object of the present invention is for providing an encapsulating structure, this structure is different with flip chip structure (FlipChip), do not use described wafer frontside as encapsulating face, can be used for comprising the component package of sensing regions such as for example photoinduction, pressure sensitive, temperature sense.
For realizing aforementioned purpose, the invention provides a kind of integrated packaging process, comprise the following step:
Form a diffusion impervious layer (barrier layer) and a growth bottom (seed layer) in the surface of a wafer, described wafer comprises at least one surperficial connection gasket, at least one inner connection gasket and at least one circuit element;
On described growth bottom, form a photoresist layer, and on described photoresist layer and described surperficial connection gasket opposite position, form an opening, the shape and size of this opening in order to define at least one passive device;
Form at least one passive device on described aperture position, the required characteristic of wherein said passive device can determine with size by the shape of described opening;
Remove described photoresist layer and described growth bottom;
Be coated with an electric barrier material in described wafer the surface and cover described passive device, to form a binder course;
Form a protective layer, combine to provide protection to encapsulating structure with described binder course, described protective layer can be considered a carrier;
Opposite side in described wafer forms a screen, and forms an opening in the correspondence position of described screen and at least one interior metal connection gasket;
Opposite side to described wafer carries out an etching technics; remove not the wafer segment protected by described screen to form at least one opening; at last; opposite side in described wafer forms an insulating barrier, a connecting line layout in regular turn, and this connecting line layout is electrically connected with described interior metal connection gasket by described opening.
Described etching technics comprises the following step:
One isotropic etching technology is in order to form at least one expansion wafer opening;
One non-isotropy etching technics, in order to form outer open wafer opening on one day, this open outwardly wafer opening is the bowl-shape opening of a surface area greater than floor space.
Described method also comprises a wafer thinning program in order to the described wafer of thinning, this program is before the opposite side of described wafer forms screen, earlier this wafer is carried out thinning, this program can realize via one of following method: a grinding technics, a chemical machinery etching technics, a wet etching technology, a plasma etching technology and a combination thereof.
Described at least one passive device is an inductance element, capacity cell or described resistive element.
For reaching above-mentioned purpose, the present invention also provides a kind of integrated wafer method for packing, comprises the steps:
A side that has surperficial connection gasket at a wafer forms a photoresist layer, and the adjacent domain of this photoresist layer and described surperficial connection gasket relevant position includes at least one opening, the shape and size of this opening in order to define described at least one passive device;
Form an interface layer, this interface layer covers described photoresist layer and described at least one opening;
Form at least one passive device on described at least one opening, described interface layer reduces the stress influence between described at least one passive device and described surperficial connection gasket, removes described photoresist layer subsequently;
Opposite side at described wafer forms a screen, and the adjacent domain of this screen and described at least one interior metal connection gasket correspondence position includes at least one opening;
Be coated with electric barrier material in described wafer the surface and cover described at least one passive device, to form a binder course; And
One protective layer combines with described binder course;
Opposite side to described wafer carries out an etching technics, removes not the wafer segment protected by described screen to form at least one wafer opening, and described at least one wafer opening is connected with described at least one interior metal connection gasket;
Remove described screen;
Opposite side at described wafer forms an insulating barrier, and this insulating barrier also not exclusively covers described at least one wafer opening, is not subjected to improperly electrically to influence in order to protect described wafer; And
Opposite side at described wafer forms a connecting line layout, and this connecting line layout covers described insulating barrier.
Described interface layer forms step and also comprises: form a diffusion impervious layer; And form a growth bottom.
Described etching technics comprises the following step:
One isotropic etching technology is in order to form at least one expansion wafer opening;
One non-isotropy etching technics, in order to form outer open wafer opening on one day, this open outwardly wafer opening is the bowl-shape opening of a surface area greater than floor space.
Described method also comprises a wafer thinning program in order to the described wafer of thinning, this program is before the opposite side of described wafer forms screen, earlier described wafer is carried out thinning, this program can realize via one of following method: a grinding technics, a chemical machinery etching technics, a wet etching technology, a plasma etching technology and a combination thereof.
Described at least one passive device is an inductance element, capacity cell or described resistive element.
For reaching above-mentioned purpose, the present invention also provides a kind of crystal circle structure, comprises:
One wafer, this wafer comprise at least one surperficial connection gasket, at least one inner connection gasket and at least one circuit element, and this circuit element places described wafer;
At least one element, this element is formed at the surface of described wafer;
One interface layer increases adhesion between described at least one element and described wafer;
One insulating barrier, this insulating barrier cover the opposite side part surface of described wafer;
At least one connecting line covers described insulating barrier and at least one inner connection gasket opening, in order to be electrically connected with described inner connection gasket;
One binder course puts on described crystal column surface and the described at least one element, and;
One protective layer, this protective layer combines with described crystal circle structure via described binder course.
Described binder course is one of following: a photoinduction benzocyclobutene layer, a polyimide layer and combination thereof.
Described protective layer is a silica-base material.
Described at least one element is at least one passive device, at least one photoinduction element, at least one temperature sensitive member, at least one pressure sensing element or at least one planar inductor.
The present invention also provides a kind of crystal circle structure, and it comprises:
One wafer, this wafer comprise at least one surperficial connection gasket, at least one inner connection gasket and at least one circuit element;
At least one element, this element are formed at a side of described wafer;
One interface layer increases adhesion between described at least one element and described wafer;
One insulating barrier, this insulating barrier cover the opposite side part surface of described wafer;
At least one connecting line covers described insulating barrier part surface and described at least one inner connection gasket, in order to be electrically connected with described at least one inner connection gasket; And
One protective layer is in order to provide described wafer with protection.
Described interface layer comprises:
One diffusion impervious layer, this diffusion impervious layer are one of following: a tungsten layer, a tungsten titanium layer, a tantalum layer, tantalum nitride layer, a titanium layer, titanium nitride layer and combination thereof; And
One growth bottom, this growth bottom are one of following: a copper metal layer, a gold metal layer and combination thereof.
Described at least one element is at least one passive device, at least one photoinduction element, at least one temperature sensitive member, at least one pressure sensing element or at least one planar inductor.
Described protective layer can be an anti oxidation layer, and this protective layer can be a polymeric membrane.
For realizing described purpose, the present invention also provides a kind of wafer system, comprising:
Semiconductor structure also comprises:
One wafer, this wafer comprise at least one surperficial connection gasket, at least one inner connection gasket and at least one circuit element;
At least one element, this element are formed at a side of described wafer;
One interface layer increases adhesion between described at least one element and described wafer;
One insulating barrier, this insulating barrier cover the opposite side part surface of described wafer;
At least one connecting line covers described insulating barrier part surface and described at least one inner connection gasket, in order to be electrically connected with described at least one inner connection gasket; And
One binder course puts on described crystal column surface and described at least one element, and;
One protective layer, this protective layer combines with described semiconductor structure via described binder course, in order to provide protection to described wafer, described at least one circuit element and described at least one element;
At least one metal welding block is electrically connected with described at least one connecting line; And
One electrical connection interface is electrically connected with described at least one metal welding block, and described semiconductor device can be electrically connected with other electric device by described electrical connection interface.
Described electrical connection interface can be a circuit board.
Described electrical connection interface can be a printed circuit board (PCB).
The present invention makes full use of wafer two surfaces and carries out encapsulation work; and by the integration of wafer encapsulation with the passive device processing procedure; reduction technology required time and complexity; reduce the encapsulation time, reduce adverse effect that the signal attenuation of external passive device and noise cause system and the utilization by protective layer; the rate of finished products of wafer and passive device is promoted simultaneously, when defective workmanship takes place, also be easy to carry out heavy industry; in this simultaneously, this technology also is compatible with standard semiconductor fabrication techniques.In addition; described binder course finished simultaneously described wafer and described passive device electric protection and with the action that combines of loam cake wafer; because its electric connection mode is different with flip chip structure; make of the use of described encapsulating structure via printing opacity or protective clear layer; can be applicable to photo-sensitive cell or ink gun element etc. and comprise the component package of front sensing area; also can integrate for example light-sensitive element, detecting element and metal coupling alternative passive devices such as (metal bump), become reliable and dynamical integrated encapsulating structure.
Description of drawings
Fig. 1 is the wafer schematic diagram according to preferred embodiment of the present invention;
Fig. 2 A, Fig. 2 B, Fig. 2 C and Fig. 2 D form the signal block diagram according to a passive device of preferred embodiment of the present invention and protective layer;
Fig. 3 A, Fig. 3 B, Fig. 3 C, Fig. 3 D, Fig. 3 E and Fig. 3 F connect lead according to one of preferred embodiment of the present invention to form the signal block diagram.
The main element symbol description:
100 wafers, 110 circuit elements
120 surperficial connection gasket 130 inner connection gaskets
210 photoinduction dielectric layer 210A openings
260 passive devices, 230 diffusion impervious layers
240 growth bottoms, 270 binder courses
280 protective layers, 310 screens
310A opening 320 wafer openings
330 insulating barriers, 340 lead layouts
Embodiment
Purpose of the present invention, feature and benefit obtain more deep understanding by following detailed description, corresponding illustrating.
Please refer to Fig. 1, wafer 100 for foundation preferred embodiment of the present invention, this wafer 100 comprises at least one circuit element 110, at least one surperficial connection gasket 120 and at least one inner connection gasket 130, described circuit element 110 is positioned at described wafer 100, described surperficial connection gasket 120 is positioned at surface one side of described wafer 100, described inner connection gasket 130 is positioned at described wafer 100, is electrically connected with described circuit element 110.
At first, one surface activating process selectivity is as required implemented, this surface activating process is in order to remove the pollutant on described crystal column surface and the surperficial connection gasket, for example oxide or particulate or the like, use the adhesive force that increases described crystal column surface and surperficial connection gasket, in the present embodiment, described surface activating process can be realized by wet etching, dry etching or plasma etching and combination thereof, but not as limit.
Shown in Fig. 2 A; a side that comprises at least one surperficial connection gasket 120 at described wafer 100 forms a photoinduction dielectric layer 210 (photoresist layer); this photoinduction dielectric layer 210 is covered on described wafer 100 surfaces and described at least one surperficial connection gasket 120, in order to described wafer dielectric protection to be provided.The material of described photoinduction dielectric layer 210 need comprise following properties: the dielectricity of this material is enough to provide described wafer 100 electric protections; this material is for finishing the photoinduction material of graphical definition by exposure imaging; in the present embodiment; described photoinduction dielectric layer 210 can utilize photoinduction benzocyclobutene (photosensitive BCB) or polyimides materials such as (polyimide) to implement, but not as limit.
Ask for an interview Fig. 2 B, then carry out an exposure imaging technology, this exposure imaging technology is in order in described photoinduction dielectric layer 210, form at least one opening 210A, described at least one opening 210A is adjacent to the corresponding part of described at least one surperficial connection gasket 120, and this opening 210A must expose described at least one surperficial connection gasket 120 at least.Described at least one opening 210A is in order to define at least one passive device 260, planar inductive component for example, and the characteristic of described passive device 260 can change by the parameters such as size, shape thickness and surface state of described opening 210A be controlled.
Please refer to Fig. 2 C, it is a passive device manufacturing process of preferred embodiment of the present invention, forms a diffusion impervious layer (barrierlayer) 230 and a growth bottom (seed layer) 240 in regular turn on described photoinduction dielectric layer 210 and described surperficial connection gasket 120.
Described diffusion impervious layer 230 is the resilient coating between described surperficial connection gasket metal 120 and the dielectric layer, use by described diffusion impervious layer 230, solution results from the high diffusion coefficient of copper and form the electrical deterioration problem of element that deep levels caused in silicon substrate, even copper is to the low tack problem of common dielectric layer, all can achieve a solution, the common material that is used for diffusion impervious layer 230 can be tungsten (W), titanium-tungsten (TiW), tantalum/tantalum nitride (Ta/TaN), titanium/titanium nitride material and combinations thereof such as (Ti/TiN), but not as limit.Described growth bottom 240 is in order to provide subsequent technique element nucleation and to grow up required and avoid the excessive delamination problems that takes place of stress, described growth bottom 240 is looked the passive device material and is adjusted, common is copper (Cu) and gold (Au) material, but not as limit.
Form at least one passive device 260 in described growth bottom 240 surfaces subsequently, the formation of described passive device 260 can electroplate (Electroplating) or electroless plating (Electroless) mode is implemented, also can realize by chemical vapour deposition (CVD), plasma enhanced chemical vapor deposition or other physical gas-phase deposite method, but also not as limit.
Shown in Fig. 2 D, remove the described diffusion impervious layer 230 and growth bottom 240 that are not covered by described passive device 260, then carry out a cycle of annealing,, and reduce the resistance value of described passive device 260 in order to the adhesion of 260 of the described growth bottom 240 of further increase and described passive devices.Thereafter, carry out wafer with protection technology, be coated with electric barrier material in the surface of described wafer 100 and cover described passive device 260, forming a binder course 270, this binder course 270 is isolated and have stickiness in order to carry out electricity, and foot is for protecting technology required.This binder course is benzocyclobutene (photosensitive BCB) or polyimides materials such as (polyimide) under preferable situation, but not as limit, as epoxy resin (epoxy) or UV glue etc., also is common bond material.One protective layer 280 is positioned at described wafer top; described protective layer 280 combines with described wafer 100 by stickiness or other mechanical bond power of described binder course 270; described protective layer 280 is in order to provide protection to described encapsulating structure; be noted that; the running of encapsulating structure needs through photo-process (as photo-sensitive cells such as CMOS or CCD) as described; then described protective layer 280 materials need to allow light to pass through, and are transparent material (as silica-base material, polymeric membrane (oxidation-resistant material)) in the present embodiment.
What deserves to be mentioned is; the process portion that the present invention forms passive device can comprise another alternate embodiment; in this alternate embodiment; can form diffusion impervious layer 230 and growth bottom 240 earlier in described wafer 100 surfaces; carry out the resist exposure developing process thereafter; form a photoresist layer (not shown) to define described passive device 260; after generating described passive device 260, remove described photoresist layer 251 and unnecessary described diffusion impervious layer 230 and growth bottom 240; be coated with described binder course 270 subsequently and be covered on described wafer 100 and the described passive device 260, then utilize binder course 270 to combine with protective layer 280.
Subsequently, as shown in Figure 3A, opposite side in described wafer 100 carries out the wafer thinning program, this program is in order to reduce the thickness of described wafer, can be via grinding, polishing, chemico-mechanical polishing (CMP), chemical etching, plasma etching or other physics and chemical etching method are realized, in this preferred embodiment, utilize one or two stage thinning program to implement, comprise one first thinning program and one second thinning program, the described first thinning program utilizes one to grind (grinding), corase grind (polishing) mode and combination thereof, under the prerequisite of not damaging wafer, earlier wafer is carried out quick thinning, then implement the described second thinning program, utilize the chemical machinery etching, plasma etching or wet etching, the further average described wafer of thinning.
Shown in Fig. 3 B, opposite side in described wafer 100 forms a screen 310, this screen 310 forms at least one opening in the corresponding part that described wafer 100 is adjacent to described inner connection gasket 130, and described opening must expose at least one inner connection gasket 130 at least.In the present embodiment, described screen 310 is a photoresist material layer, form described screen 310 and opening 310A thereof via an exposure imaging technology, but not as limit, for example via oxidation or nitrogenize program, utilize the etching mode to form described at least one opening subsequently, also for substituting one of implementation method.
Ask for an interview Fig. 3 C, then, utilize an etching technics to remove the part wafer 100 among described at least one opening 310A in the present embodiment, this moment, described inner connection gasket 130 was not exposed as yet.It should be noted that this technology can anyly have alternative enforcement of technology of isotropic etching characteristic, isotropic etching means, not only can vertically carry out etching, and have horizontal etching effect.Lateral etching can cause the phenomenon of what is called " undercutting (undercut) " to take place, in the prior art, above-mentioned undercut phenomenon often makes figure can't accurately be transferred to chip, but in the present embodiment, the expansion wafer opening that but can utilize undercut phenomenon to form assists to form outer open structure on one day, maybe can be expressed as the bowl structure of its surface area greater than described floor space, above-mentioned isotropic etching technology also can realize by a wet process etching (wet etching) or a reactive ion etching (reactive ion etching).
Shown in Fig. 3 D, carry out in the side that described wafer 100 comprises described inner connection gasket 130 " each to different in nature etching (anisotropic etching) ", use and remove described screen 310 and further remove part wafer 100, be exposed and a wafer opening 320 parts that expose described inner connection gasket 130 form outer opening on one day structure up to described inner connection gasket 130, maybe can be expressed as the bowl structure of its surface area greater than described floor space, this structure is in order to guarantee to form in the subsequent technique reliability of lead layout.Above-mentioned anisotropic etching mechanism is a kind of physical interaction basically, so the bump of ion not only can remove the film that is etched, and also can remove the photoresist mask simultaneously.Above-mentioned anisotropic etching mechanism can be dry etching (dry etching), normally a kind of plasma etching (plasma etching), plasma etching, can be the physical action of plasma intermediate ion bump crystal column surface, perhaps can be living radical in the plasma (Radical) and the interatomic chemical reaction of crystal column surface, also can be both composite actions.
Two above-mentioned stage etching technics are in order to form described open architecture outwardly, also can use a single technology to reach above-mentioned effect.For example penetrating concentration, flow and the control of other parameter make that single isotropic etching and anisotropic etching can be in order to realize described open architecture outwardly.
Ask for an interview Fig. 3 E, carry out an insulating layer deposition subsequently, a side that comprises at least one inner connection gasket 130 in described wafer 100 deposits an insulating barrier 330, this insulating barrier 330 provides described wafer 100 electricity isolated required, form a photoresist layer (figure does not show) subsequently and be covered on the described insulating barrier 330, utilize an exposure imaging technology to form at least one connection opening again in the corresponding part that is adjacent to described inner connection gasket 130.Carry out an etching technics, in order to removing the insulating barrier in the described opening 320, exposing described inner connection gasket 130, and remove described photoresist layer.
Ask for an interview Fig. 3 F, last, carry out one and connect lead technology, on described insulating barrier 330, form a lead layout 340, in order to be electrically connected with described inner connection gasket 130.In this preferred embodiment, described lead layout 340 is electrically connected with described inner connection gasket 130 by described open architecture outwardly, and avoid the excessive insulating barrier that causes 330 of opening slope bad with lead layout 340 deposition effects by this, and described opening both sides lead is too near the electric reliability issues that is caused.Described connection lead technology can be and forms a conductive layer by a depositing operation and be covered in the side that described wafer 100 comprises described at least one inner connection gasket 130, utilize a lead layout photoresist, to define described lead layout, described conductive layer carried out etching technics to finish described circuit layout thereafter, but not as limit, for example utilize shadow shield (shadow mask) to cooperate thin film technique, also can on described wafer 100, carry out lead layout definition.
According to aforesaid the present invention, can form the wafer system, it comprises: semiconductor structure also comprises: a wafer, this wafer comprise at least one surperficial connection gasket, at least one inner connection gasket and at least one circuit element; At least one element, this element are formed at a side of described wafer; One interface layer increases adhesion between described at least one element and described wafer; One insulating barrier, this insulating barrier cover the opposite side part surface of described wafer; At least one connecting line covers described insulating barrier part surface and described at least one inner connection gasket, in order to be electrically connected with described inner connection gasket; And a binder course, put on described crystal column surface and the described passive device; And a protective layer, this protective layer combines with described semiconductor structure via described binder course, in order to provide protection to described wafer, described at least one circuit element and described at least one element; At least one metal welding block is electrically connected with described at least one connecting line; And an electrical connection interface, being electrically connected with described at least one metal welding block, described semiconductor structure can be electrically connected with other electric device by described electrical connection interface.
Electrical connection interface can be a circuit board or printed circuit board (PCB).
The present invention makes full use of wafer two surfaces and carries out encapsulation work; and by the integration of wafer encapsulation with passive device technology; reduction technology required time and complexity; reduce the encapsulation time, reduce adverse effect that the signal attenuation of external passive device and noise cause system and the utilization by protective layer; the rate of finished products of wafer and passive device is promoted simultaneously, when defective workmanship takes place, also be easy to carry out heavy industry; in this simultaneously, this technology also is compatible with standard semiconductor fabrication techniques.In addition; described binder course finished simultaneously described wafer and described passive device electric protection and with the action that combines of loam cake wafer; because its electric connection mode is different with flip chip structure; make of the use of described encapsulating structure via printing opacity or protective clear layer; can be applicable to photo-sensitive cell or ink gun element etc. and comprise the component package of front sensing area; also can integrate for example light-sensitive element, detecting element and metal coupling alternative passive devices such as (metal bump), become reliable and dynamical integrated encapsulating structure.
Above embodiment only is used to illustrate the present invention, but not is used to limit the present invention.
Claims (33)
1. integrated wafer method for packing is characterized in that comprising the following step:
A side that has surperficial connection gasket in a wafer forms an interface layer;
Form a photoresist layer, the adjacent domain of this photoresist layer and described surperficial connection gasket relevant position includes at least one opening, the shape and size of this opening in order to define at least one passive device;
Form at least one passive device on described at least one opening, described interface layer reduces the stress influence between described at least one passive device and described surperficial connection gasket, removes described photoresist layer subsequently;
Opposite side in described wafer forms a screen, and the adjacent domain of this screen and at least one interior metal connection gasket correspondence position includes at least one opening;
Be coated with electric barrier material in described wafer the surface and cover described at least one passive device, to form a binder course; And
One protective layer combines with described binder course;
Opposite side to described wafer carries out an etching technics, removes not the described wafer segment protected by described screen to form at least one wafer opening, and described at least one wafer opening is connected with described at least one interior metal connection gasket;
Remove described screen;
Opposite side in described wafer forms an insulating barrier, and this insulating barrier also not exclusively covers described at least one wafer opening, is not subjected to improperly electrically to influence in order to protect described wafer; And
Opposite side in described wafer forms a connecting line layout, and this connecting line layout covers described insulating barrier.
2. method according to claim 1 is characterized in that described interface layer forms step and also comprises:
Form a diffusion impervious layer; And
Form a growth bottom.
3. method according to claim 1 is characterized in that described etching technics comprises the following step:
One isotropic etching technology is in order to form at least one expansion wafer opening;
One anisotropic etch process, in order to form outer open wafer opening on one day, this open outwardly wafer opening is the bowl-shape opening of a surface area greater than floor space.
4. method according to claim 2 is characterized in that described etching technics comprises the following step:
One isotropic etching technology is in order to form at least one expansion wafer opening;
One anisotropic etch process, in order to form outer open wafer opening on one day, this open outwardly wafer opening is the bowl-shape opening of a surface area greater than floor space.
5. method according to claim 1, it is characterized in that also comprising a wafer thinning program in order to the described wafer of thinning, this program is before the opposite side of described wafer forms screen, earlier this wafer is carried out thinning, this program realizes via one of following method: a grinding technics, a chemical machinery etching technics, a wet etching technology, a plasma etching technology and a combination thereof.
6. method according to claim 2, it is characterized in that also comprising a wafer thinning program in order to the described wafer of thinning, this program is before the opposite side of described wafer forms screen, earlier described wafer is carried out thinning, this program realizes via one of following method: a grinding technics, a chemical machinery etching technics, a wet etching technology, a plasma etching technology and a combination thereof.
7. method according to claim 3, it is characterized in that also comprising a wafer thinning program in order to the described wafer of thinning, this program is before the opposite side of described wafer forms screen, earlier described wafer is carried out thinning, this program realizes via one of following method: a grinding technics, a chemical machinery etching technics, a wet etching technology, a plasma etching technology and a combination thereof.
8. method according to claim 4, it is characterized in that also comprising a wafer thinning program in order to the described wafer of thinning, this program is before the opposite side of described wafer forms screen, earlier described wafer is carried out thinning, this program realizes via one of following method: a grinding technics, a chemical machinery etching technics, a wet etching technology, a plasma etching technology and a combination thereof.
9. method according to claim 1 is characterized in that described at least one passive device is an inductance element.
10. method according to claim 1 is characterized in that described at least one passive device is a capacity cell.
11. method according to claim 1 is characterized in that described at least one passive device is a resistive element.
12. an integrated wafer method for packing is characterized in that comprising the following step:
A side that has surperficial connection gasket at a wafer forms a photoresist layer, and the adjacent domain of this photoresist layer and described surperficial connection gasket relevant position includes at least one opening, the shape and size of this opening in order to define described at least one passive device;
Form an interface layer, this interface layer covers described photoresist layer and described at least one opening;
Form at least one passive device on described at least one opening, described interface layer reduces the stress influence between described at least one passive device and described surperficial connection gasket, removes described photoresist layer subsequently;
Opposite side at described wafer forms a screen, and the adjacent domain of this screen and described at least one interior metal connection gasket correspondence position includes at least one opening;
Be coated with electric barrier material in described wafer the surface and cover described at least one passive device, to form a binder course; And
One protective layer combines with described binder course;
Opposite side to described wafer carries out an etching technics, removes not the wafer segment protected by described screen to form at least one wafer opening, and described at least one wafer opening is connected with described at least one interior metal connection gasket;
Remove described screen;
Opposite side at described wafer forms an insulating barrier, and this insulating barrier also not exclusively covers described at least one wafer opening, is not subjected to improperly electrically to influence in order to protect described wafer; And
Opposite side at described wafer forms a connecting line layout, and this connecting line layout covers described insulating barrier.
13. method according to claim 12 is characterized in that described interface layer forms step and also comprises:
Form a diffusion impervious layer; And
Form a growth bottom.
14. method according to claim 12 is characterized in that described etching technics comprises the following step:
One isotropic etching technology is in order to form at least one expansion wafer opening;
One anisotropic etch process, in order to form outer open wafer opening on one day, this open outwardly wafer opening is the bowl-shape opening of a surface area greater than floor space.
15. method according to claim 13 is characterized in that described etching technics comprises the following step:
One isotropic etching technology is in order to form at least one expansion wafer opening;
One anisotropic etch process, in order to form outer open wafer opening on one day, this open outwardly wafer opening is the bowl-shape opening of a surface area greater than floor space.
16. method according to claim 12, it is characterized in that also comprising a wafer thinning program in order to the described wafer of thinning, this program is before the opposite side of described wafer forms screen, earlier described wafer is carried out thinning, this program realizes via one of following method: a grinding technics, a chemical machinery etching technics, a wet etching technology, a plasma etching technology and a combination thereof.
17. method according to claim 13, it is characterized in that also comprising a wafer thinning program in order to the described wafer of thinning, this program is before the opposite side of described wafer forms screen, earlier described wafer is carried out thinning, this program realizes via one of following method: a grinding technics, a chemical machinery etching technics, a wet etching technology, a plasma etching technology and a combination thereof.
18. method according to claim 14, it is characterized in that also comprising a wafer thinning program in order to the described wafer of thinning, this program is before the opposite side of described wafer forms screen, earlier described wafer is carried out thinning, this program realizes via one of following method: a grinding technics, a chemical machinery etching technics, a wet etching technology, a plasma etching technology and a combination thereof.
19. method according to claim 15, it is characterized in that also comprising a wafer thinning program in order to the described wafer of thinning, this program is before the opposite side of described wafer forms screen, earlier described wafer is carried out thinning, this program realizes via one of following method: a grinding technics, a chemical machinery etching technics, a wet etching technology, a plasma etching technology and a combination thereof.
20. method according to claim 12 is characterized in that described at least one passive device is an inductance element.
21. method according to claim 12 is characterized in that described at least one passive device is a capacity cell.
22. method according to claim 12 is characterized in that described at least one passive device is a resistive element.
23. a crystal circle structure is characterized in that comprising:
One wafer, this wafer comprise at least one surperficial connection gasket, at least one inner connection gasket and at least one circuit element;
At least one element, this element are formed at a side of described wafer;
One interface layer increases adhesion between described at least one element and described wafer;
One insulating barrier, this insulating barrier cover the opposite side part surface of described wafer;
At least one connecting line covers described insulating barrier part surface and described at least one inner connection gasket, in order to be electrically connected with described at least one inner connection gasket; And
One binder course puts on described crystal column surface and the described at least one element, and;
One protective layer, described protective layer combines with described crystal circle structure via described binder course, in order to provide protection to described wafer, described at least one circuit element and described at least one element.
24. crystal circle structure according to claim 23 is characterized in that: described binder course is one of following: a photoinduction benzocyclobutene layer, a polyimide layer and combination thereof.
25. crystal circle structure according to claim 23 is characterized in that: described protective layer is a silica-base material.
26. crystal circle structure according to claim 23 is characterized in that: described at least one element is at least one passive device.
27. crystal circle structure according to claim 23 is characterized in that: described at least one element is at least one photoinduction element.
28. crystal circle structure according to claim 23 is characterized in that: described at least one element is at least one temperature sensitive member.
29. crystal circle structure according to claim 23 is characterized in that: described at least one element is at least one pressure sensing element.
30. crystal circle structure according to claim 23 is characterized in that: described at least one element is at least one planar inductor.
31. a wafer system is characterized in that comprising:
Semiconductor structure also comprises:
One wafer, this wafer comprise at least one surperficial connection gasket, at least one inner connection gasket and at least one circuit element;
At least one element, this element are formed at a side of described wafer;
One interface layer increases adhesion between described at least one element and described wafer;
One insulating barrier, this insulating barrier cover the opposite side part surface of described wafer;
At least one connecting line covers described insulating barrier part surface and described at least one inner connection gasket, in order to be electrically connected with described at least one inner connection gasket; And
One binder course puts on described crystal column surface and the described at least one element, and;
One protective layer, this protective layer combines with described semiconductor structure via described binder course, in order to provide protection to described wafer, described at least one circuit element and described at least one element;
At least one metal welding block is electrically connected with described at least one connecting line; And
One electrical connection interface is electrically connected with described at least one metal welding block, and described semiconductor structure is electrically connected with other electric device by described electrical connection interface.
32. wafer according to claim 31 system, it is characterized in that: described electrical connection interface is a circuit board.
33. wafer according to claim 32 system, it is characterized in that: described electrical connection interface is a printed circuit board (PCB).
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| Application Number | Priority Date | Filing Date | Title |
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| CN 200610080134 CN100514589C (en) | 2006-05-09 | 2006-05-09 | Wafer level packaging method and its structure |
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| CN 200610080134 CN100514589C (en) | 2006-05-09 | 2006-05-09 | Wafer level packaging method and its structure |
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| CN100514589C true CN100514589C (en) | 2009-07-15 |
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| CN102044472B (en) * | 2009-10-09 | 2013-03-06 | 中芯国际集成电路制造(上海)有限公司 | Method for reducing thickness of dielectric layer |
| US20120188727A1 (en) * | 2011-01-24 | 2012-07-26 | ADL Engineering Inc. | EMI Shielding in a Package Module |
| US8748232B2 (en) * | 2012-01-03 | 2014-06-10 | Maxim Integrated Products, Inc. | Semiconductor device having a through-substrate via |
| CN106229809A (en) * | 2016-09-20 | 2016-12-14 | 大连艾科科技开发有限公司 | Chip carrier for semiconductor laser |
| CN108134898B (en) | 2018-01-30 | 2020-04-10 | 维沃移动通信有限公司 | Camera module, assembling method of camera module and mobile terminal |
| CN111312602B (en) * | 2020-02-26 | 2022-07-05 | 厦门通富微电子有限公司 | Packaging method |
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