JP3301894B2 - Method for manufacturing semiconductor device - Google Patents

Description

DETAILED DESCRIPTION OF THE INVENTION

[0001]

BACKGROUND OF THE INVENTION 1. Field of the Invention The present invention relates to a method for manufacturing a semiconductor device capable of easily manufacturing a semiconductor device having substantially the same dimensions as a semiconductor chip such as an LSI chip.

[0002]

2. Description of the Related Art There is a strong demand for miniaturization of a semiconductor device on which a semiconductor chip is mounted in order to increase the packaging density. The downsizing of the semiconductor device is nothing but the downsizing of the package enclosing the semiconductor chip. To meet this demand, in recent years, a chip-sized package, that is, a CSP (chip si
ze packagea or chip scale package) has emerged. There are various CSP types, and FIG. 23 shows an example. Reference numeral 10 denotes a semiconductor chip, and 12 denotes a ceramic substrate. The ceramic substrate 12 is a semiconductor chip 10
It is formed in almost the same size. Ceramic substrate 10
A wiring pattern 14 for inputting or outputting a signal is formed on the upper surface. The wiring pattern 14 is connected to a land (joining portion of an external connection terminal) 18 formed in a required arrangement on the lower surface side of the ceramic substrate 12 via a via 16. It is connected. The electrodes of the semiconductor chip 10 are Au bump 20 and AgPd paste 22
Is connected to the wiring pattern 14 through the semiconductor chip 1
A resin 24 is sealed in a gap between the first substrate 0 and the ceramic substrate 12.

[0003]

According to the above-described semiconductor device, miniaturization can be achieved.
Further, since the Au bump 20 is used, not only is it expensive, but also the ceramic substrate 10 must be manufactured separately. SUMMARY OF THE INVENTION The present invention has been made to solve the above problems, and an object of the present invention is to provide a method of manufacturing a semiconductor device which can be easily and inexpensively manufactured.

[0004]

The present invention has the following arrangement to achieve the above object. That is , a step of fixing the other surface of the insulating sheet having the metal layer formed on one surface to the surface of the semiconductor chip on which the electrodes and the passivation film are formed, and a process corresponding to the electrode of the semiconductor chip. a step of processing drilling a portion of the metal layer, said site of the insulating sheet is processed <br/> drilling corresponding to the holes in the metal layer formed by the hole drilling, thereby exposing the electrode And the electrode
Electrically connecting the electrode and the metal layer through a hole formed by a drilling process that exposes the metal layer, forming the metal layer into a required wiring pattern, and connecting the wiring pattern to the outside. With the terminal joint exposed ,
Forming an insulating film on the surface of the insulating sheet including turns; and joining an external connection terminal to the exposed external connection terminal joint. Also, many semiconductor chips are built in instead of semiconductor chips
The processed wafer is used as a workpiece, and the electrodes of the wafer and
On the surface on which the passivation film is formed,
Fixing the other surface of the insulating sheet having the layer formed thereon
And a portion of the metal layer corresponding to the electrode of the wafer
A step of drilling, and a step formed by the drilling.
Drill a hole in the insulating sheet corresponding to the hole in the metal layer.
Exposing the electrode, and exposing the electrode.
Through the hole formed by drilling the electrode
Electrically connecting the metal layer; and
Forming a required wiring pattern;
To expose the external connection terminal joint of the
Forming an insulating film on the surface of the insulating sheet
And an external connection terminal at the exposed external connection terminal joint.
Bonding the wafer and separating the wafer into individual semiconductor chips
And a step of separating into two.

The passivation film is formed.surface
To,purpleProvide an outside line shielding layer, in frontPower savingCorrespond to polesFrom the part
Also widelyThe site of the ultraviolet shielding layerSaid after removingInsulation
CToBy fixing, photolithography process
Semiconductor chips from ultraviolet rays used in the processAnd waferKeep
Can be protected. SaidExpose the electrodesThe step of
Insulation sheetDrilling by etchingEtch
It is characterized in that it is a aging process. Also beforePower savingTo the pole
Drilling a corresponding portion of the metal layer;
And forming a metal layer into a required wiring pattern.,Etch
It is characterized in that it is carried out by machining. Also beforePower saving
The step of electrically connecting a pole to the metal layer comprises:
And a plating process to form a plating film on the electrodes
It is characterized by. Further, the step of forming the insulating film,
Applying a photosensitive resist on the insulating sheetFormed
Exposure and development of the photosensitive resist film to connect the external connection terminal
Is a photolithography process that exposes
Sign. Further, as the ultraviolet shielding layer,MoneyGenus is good
Appropriately used.

[0006]

The insulating sheet and the insulating film serving as an interposer (intermediate) can be formed thin, and the insulating sheet and the insulating film act as a buffer layer of the semiconductor chip, so that the stress generated between the semiconductor chip and the mounting substrate can be reduced. A semiconductor device can be provided easily and at low cost.

[0007]

Preferred embodiments of the present invention will be described below in detail with reference to the accompanying drawings. FIG. 1 shows a sectional view of a semiconductor device 30 to be obtained. Reference numeral 32 denotes a semiconductor chip, reference numeral 34 denotes a passivation film made of SiO ₂ or the like covering the surface of the semiconductor chip 32, and reference numeral 36 denotes an Al pad (electrode) as a terminal formed in the semiconductor chip 32. The passivation film 34 is not formed at the portion of the Al pad 36,
The Al pad 36 is exposed on the surface of the semiconductor chip 32. The Al pad 36 has the required pattern and the semiconductor chip 32
Many are formed above. Reference numeral 38 denotes an insulating sheet made of an acrylic resin or the like, which is thermocompression-bonded on the semiconductor chip 32 so as to cover the passivation film 34 of the semiconductor chip 32. A through hole 39 is formed in a portion of the insulating sheet 38 corresponding to the Al pad 36, and the Al pad 36 is exposed.

Reference numeral 40 denotes a wiring pattern, which includes a through hole 39, an inner wall surface of the through hole of the passivation film 34, and the Al pad 3.
6 through the plated film 41 formed on the Al pad 36.
And is formed in a required pattern on the insulating sheet 38. The wiring pattern 40 is formed into a required pattern by etching a metal layer made of copper or the like formed on the insulating sheet 38 as described later. The electrical connection between the wiring pattern 40 and the Al pad 36 can also be performed by filling the through hole 39 with a conductive paste (not shown). Reference numeral 42 denotes an insulating film, which is formed to cover the insulating sheet 38 and the wiring pattern 40. The insulating film 42 is a protective film for the wiring pattern 40 and can be formed using various materials, for example, a photosensitive solder resist.

[0009] At appropriate portions of the insulating film 42 corresponding to the wiring patterns 40, for example, through holes 44 are formed on the insulating film 42 so as to form a matrix-like arrangement. A portion 40 is an external connection terminal joining portion 43). Reference numeral 46 denotes an external connection terminal, which is disposed so as to be electrically connected to each external connection terminal joining portion 43 through each through hole 44 and protrudes above the insulating film 42. The external connection terminal 46 can be formed in a ball shape as shown in the figure, but can be formed in a flat land shape or another shape. Reference numeral 48 denotes a protective film, which is formed so as to cover the side walls of the semiconductor chip 32, the passivation film 34, and the insulating sheet 38, and prevents entry of moisture from a boundary between the layers.
The protective film 48 can be formed using a resin of an appropriate material.
It does not necessarily have to be provided. Further, a frame made of metal or the like may be fixed instead of the protective film 48 (not shown).

[0010] Since it is formed as described above, it can be formed in a semiconductor device 30 having the same size as the semiconductor chip 32.
Further, the insulating sheet 38 and the insulating film 42 serving as the interposer can be formed thin, so that the semiconductor device 30 can be formed thin. Since the hardness of the insulating sheet 38 and the insulating film 42 is not so high, the insulating sheet 38 and the insulating film 42 also function as a buffer layer for protecting the surface of the semiconductor chip 32. Preferably, the surface on the opposite side of the semiconductor chip 32 is exposed to enhance heat radiation. In order to further improve the heat dissipation, a heat sink may be fixed (not shown).

FIGS. 2 to 7 show a manufacturing process for manufacturing the semiconductor device 30 shown in FIG. First, as shown in FIG. 2, a passivation film 34 formed on the surface of a semiconductor chip 32 is formed by attaching the other surface of an insulating sheet 38 having a metal layer 40a of copper or the like formed on one surface by sticking or physical vapor deposition. and
Thermocompression bonding is performed to cover the Al pad 36. Next, the metal layer 4
On the metal layer 40a at a position corresponding to the Al pad 36, a resist is coated by applying a resist on the
Drilling for forming Ob is performed (FIG. 3).

Next, as shown in FIG. 4, an etching process is performed using the metal layer 40a as a mask, and a hole 39 is formed in the insulating sheet 38 corresponding to the hole 40b to form a through hole 39. Thereby, the Al pad 36 is exposed. Next, by applying a resist on the metal layer 40a, the holes 40b,
A plating film 41 is formed on the through hole 39, the inner peripheral wall surface of the through hole of the passivation film 34, and the Al pad 36 by electrolytic or electroless plating of copper or the like (FIG. 5). The film 41 can also be formed by physical vapor deposition means (such as sputtering). Further, a resist is applied on the metal layer 40a, the wiring pattern is patterned by a photolithography process, and then the wiring pattern 40 is formed by etching the metal layer 40a (FIG. 6).

Next, a photosensitive resist is applied on the insulating sheet 38 so as to cover the wiring pattern 40 to form an insulating film 42. The insulating film 42 is exposed and developed by a photolithography process and covered with the photosensitive resist film. The photosensitive resist film at the portion of the wiring pattern 40 corresponding to the external connection terminal joining portion 43 is removed to expose the wiring pattern 40 at that portion (FIG. 7). A solder ball (external connection terminal) 46 is arranged on the exposed external connection terminal joint portion 43 and reflowed so that the solder ball 46 is connected to the wiring pattern 4.
Fixed on 0. As an external connection terminal, a lead pin may be fixed to the joint portion 43 in addition to the solder ball (not shown). Note that, if necessary, a resist is applied to the side wall of the semiconductor device 30 and dried to form a protective film 48. As described above, the semiconductor device 30 shown in FIG. 1 can be completed. FIG. 8 is an explanatory diagram showing an example of the arrangement of the external connection terminals 46.

The drilling shown in FIG. 3 and the formation of the wiring pattern shown in FIG. 6 can be performed in the same etching step. Thereafter, the steps shown in FIGS. 4 and 5 are performed. In the step of FIG. 5, instead of plating, the holes 39 and the like are filled with a conductive paste so that the metal layer 40a
(Alternatively, the wiring pattern 40) and the Al pad 36 may be electrically connected.

9 to 19 show another embodiment of the method for manufacturing a semiconductor device. This embodiment is characterized in that a circuit formed on a semiconductor chip is not damaged by irradiation of ultraviolet rays in a photolithography step when forming an insulating film 42 using a negative photosensitive resist. I do. FIGS. 9 and 10 show a characteristic process of the present embodiment. Before the insulating sheet 38 is thermocompression-bonded to the surface of the semiconductor chip 32, an ultraviolet shielding layer for shielding ultraviolet light used as an exposure light source in a photolithography process. The step of providing 50 is shown.

The ultraviolet shielding layer 50 protects an area where a circuit is formed on the semiconductor chip 32 from ultraviolet rays.
As shown in FIG. 10, it is formed on the passivation film 34 in a range excluding the Al pad 36. In order to form the ultraviolet shielding layer 50, as shown in FIG. 9, first, a metal layer 50a is formed on the passivation film 34 of the semiconductor chip 32 by a sputtering method or a vapor deposition method, and a photosensitive resist 51 is formed thereon. Is applied. When the photosensitive resist 51 is of a negative type, the portion corresponding to the Al pad 36 is shielded and exposed and developed, and the portion of the photosensitive resist 51 corresponding to the Al pad 36 is removed to expose the metal layer 50a. The ultraviolet shielding layer 50 is formed on the passivation film 34 by etching the metal layer 50a (FIG. 10).

When a positive resist is used as the photosensitive resist 51, the exposure range is opposite to that when a negative resist is used. In the photolithography process described above, ultraviolet light is used for exposing the photosensitive resist 51.
Since the metal layer 50a is formed on the entire surface of the passivation film 34 as an underlayer, the ultraviolet rays are blocked by the metal layer 50a regardless of whether the photosensitive resist 51 is a negative type or a positive type. The circuit of the semiconductor chip 32 is prevented from being damaged.

The metal used for the ultraviolet shielding layer 50 is C
r can be suitably used, and a thickness of about 0.1 μm can sufficiently shield ultraviolet rays. Note that a Cu metal layer can be used instead of the Cr metal layer. Further, the ultraviolet shielding layer 50 can be formed by a plurality of laminated structures such as a Cr metal layer-Ni metal layer-Cu metal layer.

The manufacturing steps after FIG. 11 are the same as the steps described above. That is, after the above-mentioned ultraviolet shielding layer 50 is formed, the insulating sheet 38 in which the metal layer 40a is formed on the surface of the semiconductor chip 32 is formed (FIG. 11). Next, a photosensitive resist is applied to the surface of the metal layer 40a, a resist pattern is formed by a photolithography process, and the metal layer 40a is etched to form a hole 40b (FIG. 12). In this photolithography step, the photosensitive resist applied to the surface of the metal layer 40a is also exposed to ultraviolet rays. However, since the surface of the insulating sheet 38 is covered with the metal layer 40a, the photosensitive resist is also used in this step. Damage to the semiconductor chip 32 is prevented regardless of whether it is a negative type or a positive type.

Next, the metal layer 40 in which the hole 40b is formed
Etching is performed on the insulating sheet 38 using a as a mask to form through holes 39 in the insulating sheet 38 corresponding to the holes 40b (FIG. 13). Next, electroless copper plating and electrolytic copper plating are applied to the hole 40b, the through hole 39, the inner peripheral wall surface of the through hole of the passivation film 34, and the Al pad 36, thereby forming a plating film 41 (FIG. 14).

Next, in order to form the wiring pattern 40 by etching the metal layer 40a, a photosensitive resist is applied to the surface of the metal layer 40a, and the photosensitive resist is exposed by the same photolithography process as described above. Developing to form a predetermined resist pattern, and etching the metal layer 40a to form a wiring pattern 40 (FIG. 15).
Also in the photolithography process, when the photosensitive resist is exposed to ultraviolet rays, the underlying layer of the photosensitive resist is completely covered by the metal layer 40a and the plating film 41, so that the circuit of the semiconductor chip 32 may be damaged. I will not give.

After the wiring pattern 40 is formed as described above, an insulating film 42 is formed on the insulating sheet 38 so as to cover the wiring pattern 40 so as to form a joint for connecting the wiring pattern 40 and the external connection terminal. Photosensitive resist 42
is applied, and the photosensitive resist 42a is exposed and developed to expose the external connection terminal joint 43 of the wiring pattern 40. FIG. 16 shows a state in which a portion corresponding to the external connection terminal junction 43 is shielded and exposed, and FIG. 17 shows a state in which the photosensitive resist is exposed and developed, the insulating film 42 is perforated, and the external connection terminal junction 43 is exposed. Shows the exposed state.

FIG. 16 shows a case where a negative type photosensitive resist is used as a photosensitive resist for forming the insulating film 42. Since the portion of the negative type photosensitive resist that is not exposed to light is dissolved by the developer, the portion corresponding to the external connection terminal joining portion 43 is shielded by a mask and irradiated with ultraviolet light during exposure.

The above-mentioned ultraviolet shielding layer 50 is effective for preventing the circuit of the semiconductor chip 32 from being damaged during the irradiation of the ultraviolet rays. That is, if the ultraviolet ray shielding layer 50 is not provided in the photolithography step, there is no layer for shielding the ultraviolet ray between the patterns of the wiring patterns 40 when the ultraviolet ray is irradiated, and the photosensitive resist and the insulating sheet 38 and the passivation film 34 UV light is transmitted through the semiconductor chip 3
Ultraviolet rays may be incident on the surface of No. 2 and damage the circuit. In the photolithography process described above, when irradiating the photosensitive resist with ultraviolet light, the metal layer as an underlayer covered the entire surface of the light irradiation surface, whereas in this photolithography process, the wiring pattern was formed. 4
Since this is a step after forming 0, there is a problem that the circuit of the semiconductor chip 32 is damaged due to transmission of ultraviolet rays.

FIG. 19 shows an exposure method using ultraviolet rays when a positive resist is used as a photosensitive resist for forming the insulating film 42. In the case of the positive type, the part irradiated with ultraviolet rays is dissolved by the developer,
As shown in the figure, a portion other than the portion where the external connection terminal joint 43 is exposed is shielded by a mask and irradiated with ultraviolet rays. Then, after exposure, development is performed to form an external connection terminal joint 43 similar to that of FIG.

As described above, when a positive type photosensitive resist is used, ultraviolet rays may be applied only to a portion where the external connection terminal joint 43 is exposed. Since the external connection terminal bonding portion 43 is provided in a range where the wiring pattern 40 is formed, when a positive photosensitive resist is used, the irradiation range of the ultraviolet rays is limited to a range where the wiring pattern 40 is formed. be able to. That is, when a positive photosensitive resist is used, ultraviolet rays may be applied to the area where the wiring pattern 40 is formed as a base layer, so that the ultraviolet rays are blocked by the wiring pattern 40 and the ultraviolet shielding layer 50 is not provided. However, it is possible to prevent the circuit of the semiconductor chip 32 from being damaged.

After exposing the external connection terminal joints 43 from the insulating film 42 as described above, solder balls (external connection terminals) 46 are arranged on the exposed external connection terminal joints 43, and reflowed by soldering. The semiconductor device is obtained by fixing the ball 46 on the wiring pattern 40 (FIG. 18). And
If necessary, a resist is applied to the side wall of the semiconductor device 30 and dried to form a protective film 48, whereby the semiconductor device 30 shown in FIG. 1 can be completed.

In the method of manufacturing the semiconductor device shown in FIGS. 9 to 19, the ultraviolet shielding layer 5 is formed on the passivation film 34.
By providing 0, it is effective in manufacturing a semiconductor device suitably without damaging the circuit of the semiconductor chip, especially when performing a photolithography process using a negative photosensitive resist.

FIG. 20 to FIG.
A method of forming lands on the inner surface of the storage hole 54 of the insulating film 42 and the peripheral edge of the storage hole 54 for joining the external connection terminal 46 to the external connection terminal 46 so that the external connection terminal 46 can be reliably connected. FIG. 20 shows a state in which a metal layer 58 such as a copper layer is formed on the surface of the insulating film 42 and the inner surface of the storage hole 54 by a sputtering method or a vapor deposition method in a state where the storage hole 54 shown in FIG. 17 is formed.

Next, a photosensitive resist is applied to the surface of the metal layer 58, and the metal layer 58 is etched by a photolithography process, leaving the photosensitive resist inside the storage hole 54 and the periphery of the storage hole 54. Thus, a land 60 is formed (FIG. 21). Land 60 is connected to external terminal joint 4 at the bottom.
3, and the inner surface and the periphery of the storage hole 54 are covered with a metal layer.

FIG. 22 shows a state in which the external connection terminal 46 is joined to the land 60. In the example shown in FIG. 18, the external connection terminal 46 is only connected to the external terminal joint 60 of the wiring pattern 40 on the bottom surface, whereas in this example, the external connection terminal 46 is joined via the land 60. The external connection terminal 46 is also securely joined to the inner surface of the storage hole 54, and has an advantage that the connection with the semiconductor chip 32 is more reliably achieved.

In the above embodiment, the individual semiconductor chips 32 are described. However, a wafer in which a large number of semiconductor chips 32 are formed is used, and an insulating sheet 38, a wiring pattern 40, After the insulating film 42 and the external connection terminals 46 are formed, a large number of semiconductor devices 30 can be formed at a time by slicing and separating into individual pieces, so that the cost can be reduced.

[0033]

According to the method of manufacturing a semiconductor device according to the present invention, as described above, the semiconductor device can be manufactured mainly by an etching process, a photolithography process, etc., so that a small and lightweight semiconductor device can be easily manufactured at low cost. Can be manufactured. Also,
By providing an ultraviolet shielding layer on the circuit surface of the semiconductor chip and exposing the semiconductor chip, the semiconductor device can be manufactured without damaging the semiconductor chip.

[Brief description of the drawings]

FIG. 1 is a partial cross-sectional view of a semiconductor device.

FIG. 2 is a partial cross-sectional view of a state where an insulating sheet is thermocompression-bonded.

FIG. 3 is a partial cross-sectional view showing a state where a metal layer has been drilled.

FIG. 4 is a partial cross-sectional view showing a state where a hole is formed in an insulating sheet.

FIG. 5 is a partial sectional view showing a state where a plating film is formed.

FIG. 6 is a partial cross-sectional view showing a state where a wiring pattern is formed.

FIG. 7 is a partial cross-sectional view in a state where an insulating film is formed.

FIG. 8 is an explanatory diagram showing an example of the arrangement of solder bumps.

FIG. 9 is a partial cross-sectional view showing a state where a metal layer is applied to a passivation film and a photosensitive resist is applied.

FIG. 10 is a partial sectional view showing a state where an ultraviolet shielding layer is provided.

FIG. 11 is a partial cross-sectional view showing a state where an insulating sheet is thermocompression-bonded.

FIG. 12 is a partial cross-sectional view showing a state where a hole is formed in a metal layer.

FIG. 13 is a partial cross-sectional view showing a state where a hole is formed in an insulating sheet.

FIG. 14 is a partial sectional view showing a state where a plating film is formed.

FIG. 15 is a partial cross-sectional view in a state where a wiring pattern is formed.

FIG. 16 is an explanatory diagram showing a state in which a negative photosensitive resist is irradiated with ultraviolet rays.

FIG. 17 is a partial cross-sectional view showing a state where an external connection terminal joint is formed.

FIG. 18 is a partial sectional view showing a state where solder balls are attached.

FIG. 19 is an explanatory diagram illustrating a state in which a positive photosensitive resist is irradiated with ultraviolet rays.

FIG. 20 is a partial cross-sectional view showing a state in which a metal layer is provided on surfaces of an insulating sheet and a wiring pattern.

FIG. 21 is a partial cross-sectional view showing a state where lands are provided on the surface of an insulating sheet.

FIG. 22 is a partial cross-sectional view showing a state where external connection terminals are joined to lands.

FIG. 23 is a cross-sectional view illustrating an example of a conventional semiconductor device.

[Explanation of symbols]

 REFERENCE SIGNS LIST 30 semiconductor device 32 semiconductor chip 34 passivation film 36 Al pad 38 insulating sheet 40 wiring pattern 40 a metal layer 42 insulating film 43 external connection terminal joint 44 through hole 46 external connection terminal 48 protective film 50 ultraviolet shielding layer 50 a metal layer 51 photosensitive Resist 54 Storage hole 58 Metal layer 60 Land

──────────────────────────────────────────────────続 き Continuation of the front page (72) Inventor Takehiko Arai Nagano Pref. 7-321157 (JP, A) JP-A-8-330313 (JP, A) (58) Fields investigated (Int. Cl. ⁷ , DB name) H01L 23/12 H01L 21/60

Claims (8)

(57) [Claims] 1. A step of fixing the other surface of an insulating sheet having a metal layer formed on one surface to a surface of a semiconductor chip on which electrodes and a passivation film are formed, and the step of fixing the metal corresponding to the electrodes of the semiconductor chip. a step of processing drilling sites layer, before corresponding to the hole of the metal layer formed by the hole drilling
Serial and drilling sites insulating sheet, thereby exposing the electrode, thereby electrically connecting to the electrode through a hole formed by drilling to expose the electrode and the metal layer Forming the metal layer into a required wiring pattern; exposing an external connection terminal joint of the wiring pattern ;
A method of manufacturing a semiconductor device, comprising: a step of forming an insulating film on a surface of the insulating sheet including a wiring pattern ; and a step of joining an external connection terminal to the exposed external connection terminal joint. 2. A wafer on which a large number of semiconductor chips are formed.
The electrode and passivation film
Fix the other side of the insulating sheet with the metal layer formed on one side.
A step of wearing the portion of the metal layer corresponding to the electrode of the wafer perforated
A step of drilling and before the hole corresponding to the hole of the metal layer formed by the drilling.
Drill holes in the insulating sheet to expose the electrodes
A step of, the holes formed by drilling to expose the electrode via
Electrically connecting the electrode and the metal layer
When the step of forming the metal layer into a desired wiring pattern, to expose the external connection terminal junction of the wiring pattern, the
Insulating film on the surface of the insulating sheet including the wiring pattern
Forming and connecting an external connection terminal to the exposed external connection terminal joint.
Combining the wafer and separating the wafer into individual semiconductor chips.
A method for manufacturing a semiconductor device, comprising: 3. The method according to claim 1, wherein the surface on which the passivation film is formed is
An ultraviolet shielding layer is provided , and is wider than the portion corresponding to the electrode.
After removing the portion of the ultraviolet shielding layer, the insulating sheet is removed.
3. The method of manufacturing a semiconductor device according to claim 1, wherein the semiconductor device is fixed . 4. The step of exposing said electrode includes the step of exposing said insulating film.
Etching process that drills holes in the plate by etching
4. The method for manufacturing a semiconductor device according to claim 1, wherein 5. The method according to claim 1, wherein a portion of the metal layer corresponding to the electrode is
Drilling process and required wiring pattern of the metal layer
5. The method of manufacturing a semiconductor device according to claim 1 , wherein the step of forming the semiconductor device is performed by etching . 6. An electrical connection between said electrode and said metal layer.
Forming a plating film on the holes and the electrodes.
A plating step, wherein the plating step is performed.
6. The method for manufacturing a semiconductor device according to 4 or 5. 7. The step of forming the insulating film comprises the step of
Photosensitivity formed by applying photosensitive resist on edge sheet
Exposing and developing the resist film to expose the external connection terminal junction
Claim 1, 2, 3, 4, a manufacturing method of a semiconductor device 5 or 6, wherein it is a photo-lithography step for. 8. A metal layer is formed as said ultraviolet shielding layer.
Claims 2, 3, 4, 5, 6 or
8. The method for manufacturing a semiconductor device according to claim 7.