JPH0541428A - Semiconductor device - Google Patents

Abstract

PURPOSE:To obtain a semiconductor device having a semiconductor chip capable of preventing the generation of idle regions turning to obstacles for miniaturizing a semiconductor chip when many pads for zapping are arranged. CONSTITUTION:In a semiconductor device having a semiconductor chip 1 provided with pads 1b for zapping the centers of the adjacent pads 1b do not exist on a straight line but on the bending points of a zigzag line. The pads 1b are so arranged that the mutually facing sides of the adjacent pads 1b are parallel with each other.

Description

Detailed Description of the Invention

[0001]

BACKGROUND OF THE INVENTION 1. Field of the Invention The present invention relates to a semiconductor device having an improved arrangement of zap pads on a semiconductor chip.

The semiconductor chip of a recent semiconductor device is required to be as small as possible. On the other hand, in a highly functional semiconductor chip, an internal diode or the like is short-circuited to obtain a predetermined resistance value, for example. Zap pads are provided. A probe needle is brought into contact with this zap pad to supply a voltage that short-circuits a diode, for example, to the internal circuit, but recently, since many zap pads tend to be placed together on one side of a semiconductor chip, This is an obstacle to miniaturization of semiconductor chips.

Under the circumstances as described above, there is a demand for a semiconductor device having a semiconductor chip in which many zap pads can be arranged in a region as narrow as possible.

[0004]

2. Description of the Related Art A conventional semiconductor device having a semiconductor chip having five zap pads will be described in detail with reference to FIG.

FIG. 3 is a view showing the arrangement of zap pads of a conventional semiconductor device. If the pads are arranged by preferentially considering the bonding by the wire 3 between the lead 2a of the lead frame 2 and the bonding pad 1a of the semiconductor chip 1, the entire length of the zap pad 1b becomes long as shown in FIG. The length of the side on which the zap pad 1b is arranged is longer than the length of the element formation region 1c, and an idle region 1d is generated, which hinders miniaturization of the semiconductor chip 1.

[0006]

In the semiconductor chip of the conventional semiconductor device described above, since the centers of the zap pads are arranged in a straight line, the total length of the side on which the zap pads are arranged is the element. It becomes longer than the formation region, and an idle region is generated, which hinders the miniaturization of the semiconductor chip. Further, as shown in FIG. 4, when the pads are arranged by prioritizing the miniaturization of the semiconductor chip 1, the bonding pad of * A is formed. , * B, it is difficult to perform bonding at the two places of the lead, and there is a problem that a lead frame must be newly manufactured.

In view of the above situation, the present invention is a semiconductor device having a semiconductor chip which can prevent the generation of an idle region which hinders the miniaturization of the semiconductor chip when many zap pads are arranged. The purpose is to provide.

[0008]

The semiconductor device of the present invention comprises:
A semiconductor device having a semiconductor chip with a zap pad, wherein the center of the adjacent zap pad is not on a straight line, but at the zigzag line break point, and the opposite sides of the zap pads are parallel to each other. Configure it to be placed.

[0009]

That is, in the present invention, the centers of the adjacent zap pads are not on a straight line but at the zigzag line break points, the opposite sides of the zap pads are parallel, and the distance between these sides is the minimum allowable value. As the zap pads are placed in the dimensions, the placement pitch is 200μ as shown in Fig. 2.
In case of regular octagonal zap pad of m, 58.58μm per one zap pad [200 ÷ (1 + 1.4142 + 1)]
It can be shortened, for example, if there are 5 zap pads,
234.3 μm (1,000-765.7) can be shortened, and when arranging the same number of zap pads, it can be arranged in a shorter range than before, so it is possible to eliminate idle areas and newly lead according to the position of the bonding pad. Eliminates the need to manufacture a frame.

Further, since the shape is different from that of other bonding pads, the identification is easy.

[0011]

DETAILED DESCRIPTION OF THE PREFERRED EMBODIMENTS A fifth embodiment of the present invention will now be described with reference to FIGS.
A semiconductor device having a semiconductor chip having a regular octagonal zap pad will be described in detail.

FIG. 1 is a view showing the arrangement of zap pads of a semiconductor device according to an embodiment of the present invention. In one embodiment according to the present invention, as shown in the figure, the center of the adjacent zap pad 1b is arranged at the break point of the zigzag line shown by the dotted line in the figure, and the opposite sides of this zap pad 1b are parallel, Since the zap pad 1b is arranged at the minimum allowable space between the sides, the zap pad 1b can be arranged in a range 234.3 μm shorter than the conventional one as shown in FIG. Since it is possible to eliminate the area 1d, the conventional lead frame 2 is used and the wire 3
Can be bonded.

[0013]

As is apparent from the above description, according to the present invention, it is possible to eliminate the idle region of the semiconductor chip by changing the arrangement of the zap pads, which is extremely simple, and to manufacture a new lead frame. It is possible to provide a semiconductor device which has advantages such as no need, and which can be expected to have a remarkable economic effect and reliability improvement effect.

[Brief description of drawings]

FIG. 1 is a diagram showing an arrangement of zap pads of a semiconductor device according to an embodiment of the present invention,

FIG. 2 is a diagram showing the relationship between the number of zap pads and the total length of zap pads,

FIG. 3 is a diagram showing a layout of zap pads of a conventional semiconductor device;

FIG. 4 is a diagram showing a problem of a conventional semiconductor device,

[Explanation of symbols]

 1 is a semiconductor chip, 1a is a bonding pad, 1b is a zap pad, 1c is an element formation region, 1d is an idle region, 2 is a lead frame, 2a is a lead, 3 is a wire,

Claims (1)

[Claims] 1. A semiconductor device having a semiconductor chip (1) provided with a zap pad (1b), wherein the centers of adjacent zap pads (1b) are not on a straight line, and at zigzag line break points. A semiconductor device having a semiconductor chip (1), characterized in that opposite sides of the zap pads (1b) are arranged in parallel.