JPH0540553A - Personal computer - Google Patents

Abstract

PURPOSE:To execute a high-speed processing by comparing command data to be transmitted with fixed value prepared in advance, inactivating the personal computer when they are equal, and realizing compatibility. CONSTITUTION:This personal computer is composed of a microprocessor 10, controller 20, keyboard controller 30, buffer 40, logic circuit 50 and K/B 60. When the command data are issued from the microprocessor 10 to the K/B controller 30, the command data are stored in the latch storing means of the controller 20 and compared with the value of command data, which are prepared by a hardware as fixed value in advance, by a comparing means. Corresponding to the state of control bits in the command data, a control signal 100 of address lines 120 is generated and reported from the controller 20 to the logic circuit 50. Then, the signal is ANDed with a specified address 110 and outputted as the address line 120 of the system.

Description

Detailed Description of the Invention

[0001]

BACKGROUND OF THE INVENTION 1. Field of the Invention The present invention relates to a personal computer in which command data sent from a microprocessor to a keyboard controller is recognized by hardware.

[0002]

2. Description of the Related Art FIG. 7 is a block diagram showing a personal computer equipped with a microprocessor and a keyboard controller and handshaking with each other. 7, a conventional personal computer comprises a microprocessor 10, a logic circuit 20, a keyboard controller 30, and a keyboard 40. As shown in the flowchart of FIG. 8, the microprocessor 10 and the keyboard controller 30 are shown.
Command data is transmitted and received between and by the handshake protocol. The operation of the keyboard controller 30 will be described based on the flowchart of FIG. Microprocessor 10 to keyboard controller 30
When the input buffer of the keyboard controller 30 is full when the command data is sent to the computer, the waiting is always waited until the buffer becomes empty (step 10). When the input buffer into which the command data is fetched has an empty space, the command data is transferred (step 20), and the command data is fetched (step 30). Then, the command is checked to see if it is the desired command, and if it does not match, the process corresponding to that command is executed, and if it matches, the second command data is transferred, but if the input buffer is full, the buffer Continue to wait until it is free (step 40). Next, the same processing as described above is performed for the second command data (steps 50 and 60), 2
If the second command data also match, a one-chip microcomputer control signal is generated (step 70). As described above, in the conventional personal computer, the handshake is performed between the microprocessor 10 and the keyboard controller 30 by software.

[0003]

In the conventional personal computer, since the handshake is performed by software between the microprocessor and the keyboard controller, even if command data is sent from the microprocessor to the keyboard controller, the keyboard controller is sent. When the input buffer inside is full, it has to keep waiting. Furthermore, it takes tens of microseconds to 20 several microseconds to analyze the command data, so the processing speed is slow and the system performance deteriorates. ..

[0004]

The present invention has been made in view of this point, and has a keyboard controller for controlling a keyboard and uses a microprocessor having upward compatibility with the 8088 and 8086. In a personal computer, storage means for storing command data from the microprocessor to the keyboard controller, registration means for registering desired command data, command data stored in the storage means and the registration information Comparing means for comparing the command data, the generating means for generating the control signal of the address line when the comparison result matches, the signal output from the generating means and the signal having the specific memory capacity or more (the address line 21). And a logic circuit that performs a logical product with To provide a null computer.

[0005]

[Operation] 80286, 8038 configured as described above
Up to now 808 even on IBM compatible personal computers with 6 or 80486 microprocessors
The command data sent from the microprocessor to the keyboard controller is the desired command data in order for the application program running on the IBM personal computer equipped with the 8,8086 microprocessor to run without any change. The comparison is performed with a fixed value created by hardware in advance, and when they match, the compatibility is realized by deactivating a specific address line.

[0006]

Embodiments of the present invention will be described below with reference to the drawings. 1 is a block diagram of a personal computer showing an embodiment of the present invention, FIG. 2 is a block diagram of a controller used in the personal computer showing an embodiment of the present invention, and FIG. 3 is a block diagram of the present invention. FIG. 4 is a timing chart when a control signal of an address line of a personal computer showing an embodiment is generated. FIG. 4 shows a case where a command of a first byte coincides with a command of a second byte in a personal computer showing an embodiment of the invention. 5 is a timing chart in the case where the data of FIG.
FIG. 6 is a timing chart when the first byte command does not match in the personal computer showing the embodiment of the present invention, and FIG. 6 shows the control signals by hardware in the personal computer showing the embodiment of the present invention. FIG. 8 is a flowchart for generation, FIG. 7 is a block diagram of a conventional personal computer, and FIG.
FIG. 6 is a flowchart of a conventional personal computer in which a control signal is generated by software. In FIG. 1, the personal computer of the present invention includes a microprocessor 10, a controller 20, a K / B controller 30, a buffer 40, a logic circuit 50, and a KEY.
BOARD (hereinafter referred to as K / B) 60. In FIG. 2, the controller 20 used in the personal computer of the present invention is a Latch storage means 2
00, comparison means 210, timing generator 22
0 and control logic 230. The operation will be described based on FIGS. 1 and 2. When command data is issued from the microprocessor 10 to the K / B controller 30, the command data is stored in the Latch storage means 200 inside the controller 20, and the value of the command data previously created by hardware as a unique value and the comparison means. 210 for comparison. As for this command data, a 1-byte instruction command is issued twice, and a timing chart when the respective commands match is shown in FIG.
Command data is sent immediately without performing g. The operation will be described based on FIG. When the IOWR signal is in the LOW level, it indicates that the command is issued, and then the Latch-clock signal becomes HIG.
When in the H level state, each issued command is Latc
h Indicates that it is stored in the storage unit 200. Then, each command is compared by the comparison means 210 with the value of the command data previously created by hardware as a unique value, and the Equal1 signal and the Equal2 signal are HIG
It shows that they match when in the H level state. In this case, as shown in FIG. 6, the address line control signal 100 is generated according to the state of the control bit of the command data (step 1), and the controller 20 outputs the address line control signal 100 to the logic circuit 50 as shown in FIG. The control signal 100 is notified. Then, the control signal 10 of the above-mentioned address line
0 is logically ANDed with the specific address 110 output from the microprocessor 10 in the logic circuit 50 and output as the address line 120 of the system. 80286,8 used in the personal computer of the present invention
This ANDed address line 120 is used by the 0386 or 80486 microprocessor to access 1M bytes when addressing more than 1M bytes of the address space covered by the lower microprocessors 8088, 8086. Make sure that addresses beyond the byte are not accessed, and
Application programs running on 088, 8086 microprocessor are 80286, 80386
It is also compatible to work on 80486 microprocessors. Next, the operation will be described with reference to FIGS. 4 and 6. Microprocessor 10 to K /
When the first command data is issued to the B controller 30, the Latch-clock signal becomes a high level state, and the comparison means 210 compares it with the value of the command data previously created by the hardware as an eigenvalue. In this case, since the Equal1 signal is in the high level state, the microprocessor 10 outputs K / B.
This shows that the command data issued to the controller 30 matches the command data registered in advance. Next, the second command data is issued from the microprocessor 10 to the K / B controller 30, but the pseudo IBF flag data is read inside the controller 20 so that the input buffer inside the controller 20 can operate without waiting. Since it is vacant, the command data for the second time is fetched and compared by the comparison means 210 with the value of the command data previously created by the hardware as the unique value as in the case of the command data for the first time. As shown in the timing chart of FIG. 4, the Equal2 signal indicates the LOW level state, which indicates that the second command data does not match. When the second command data do not match, the first command and the second command data are controlled so as to be transmitted from the controller 20 to the K / B controller 30 through the buffer 40 (step 2). The K / B controller 30 inactivates the handshake signal because the data of the command is set in the internal input buffer, and inhibits the transmission of the next command data. Wait until IBF flag is cleared
is performed, and if there is an empty space, the command data for the second time is transferred and all controls are completed. Next, the operation will be described with reference to FIGS. When the command data is issued twice from the microprocessor 10 to the K / B controller 30, the Equal1 signal and the Equal2 signal show the LOW level state as shown in the timing chart of FIG. Indicates that it does not match command data created in advance as a unique value by hardware. In this case, data which is not a predetermined command is transmitted to the K / B controller 30 through the buffer 40 (step 3).

[0007]

According to the present invention, an application program running on an 8088 or 8086 microprocessor is kept compatible with the microprocessor so as to be compatible with the 80286, 80386 or 80486 microprocessor. / B controller does not send and receive commands and command data using the handshake protocol, but the hardware built into the controller determines the commands and command data, so high-speed processing is performed while maintaining compatibility. ..

[Brief description of drawings]

FIG. 1 is a block diagram of a personal computer showing an embodiment of the present invention.

FIG. 2 is a block diagram of a controller used in a personal computer according to an embodiment of the present invention.

FIG. 3 is a timing chart when a control signal for an address line of a personal computer is generated according to an embodiment of the present invention.

FIG. 4 is a timing chart when the command of the first byte matches and the data of the second byte does not match in the personal computer showing the embodiment of the present invention.

FIG. 5 is a timing chart when the first byte command data does not match in the personal computer according to the embodiment of the present invention.

FIG. 6 is a flow chart when a control signal is generated by hardware in a personal computer showing an embodiment of the present invention.

FIG. 7 is a block diagram of a conventional personal computer.

FIG. 8 is a flow chart when a control signal is generated by software in a conventional personal computer.

[Explanation of symbols]

 10 Microprocessor 20 Controller 30 K / B Controller 40 Buffer 50 Logic Circuit 60 KEYBOARD (K / B)

Claims (1)

[Claims] 1. In a personal computer using a microprocessor having a keyboard controller for controlling a keyboard and having upward compatibility with 8088 or 8086, command data from the microprocessor to the keyboard controller is stored. A storage means, a registration means in which desired command data is registered, a comparison means for comparing the command data stored in the storage means with the registered command data, and an address when the comparison result matches. And a logic circuit for performing a logical product operation of a signal output from the generation means and a signal having a specific memory capacity or more (21st address line). A personal computer that does.