JPH0538134A - Load control power supply - Google Patents

Abstract

PURPOSE:To realize boosting and maintaining the gate electrode voltage of N-channel MOSFET to be used as high-side switch without increasing a chip area and while a high-speed operation is made possible and ON resistance is held low. CONSTITUTION:A capacitor to be charged with electricity, when a source electrode 7 reaches a ground potential, is provided as boosting circuit 11 and a potential detection circuit 12 for monitoring a gate-source voltage Vgs is also provided at an apparatus. When Vgs drops to a predetermined value even while the apparatus operates on full duty, a gate control circuit 13 lowers the potential of a gate electrode 8 by a signal from the potential detection circuit 12 to turn OFF MOSFET1 to restart the boosting circuit 11.

Description

Detailed Description of the Invention

[0001]

BACKGROUND OF THE INVENTION 1. Field of the Invention The present invention particularly relates to a load control power supply device using a PWM driving power IC using an N-channel MOSFET.

[0002]

N-channel MOSFETs for power ICs
When is used as a high-side switch, it is necessary to boost the gate electrode above the power supply voltage. As a conventional load control power supply device for this purpose, there is a load control power supply device using a charge pump circuit as a booster circuit, as proposed in JP-A-58-500835. As shown in FIG. 7, the oscillator 137 oscillates and outputs MO in response to a signal input to the input terminal 5.
In the device for controlling SFET1, the oscillator 137 and M
Diode and capacitor 2 between OSFET1 and
The converter 138 having 2'is provided to double the control voltage of the gate electrode 8 of the MOSFET 1.

In addition to this, as shown in FIG.
There is also used a bootstrap circuit in which is connected between the source electrode 7 and the gate electrode 8 via the gate control circuit 3. In addition, a circuit in which a charge pump and a bootstrap circuit are combined is also used.

[0004]

However, when a charge pump is used, it is difficult to make a large capacitor inside the IC because it causes an increase in the chip area, and it is at most several tens pF. Therefore, it takes a very long time to charge a very large gate capacitance of several thousands pF level, and it is impossible to operate at high speed. Especially in the case of PWM drive,
It is necessary to set the operating frequency outside the audible range, but this method is difficult.

Further, since the capacitor is usually made of a MOS structure, the reliability of the gate oxide film becomes problematic as the number of times of charging and discharging increases, so that the operating frequency of the oscillator must be limited. Furthermore, if the capacitor of the charge pump circuit is externally attached, the number of terminals will be at least 2
This leads to an increase in the chip area and an increase in the mounting cost.

In the bootstrap circuit, a capacitor having a large capacity, originally having the capacitor 2 as an external component, can be used, and the problem of operating speed is improved. However, when operating at full duty, no new charge is supplied to the capacitor 2, and the charge stored in the gate decreases with time due to the leak current of the gate oxide film, the diode, etc. When operating at full duty for a long time, the gate-source voltage Vgs becomes low, and
There is a problem that the device is driven in a state where the on resistance of T1 is high.

The combination of the charge pump and the bootstrap circuit naturally complicates the circuit configuration. In particular, in the case of PWM driving, new charges are regularly supplied except when the duty is full, so that the charge pump is not always required, and there are problems in terms of mounting and cost.

Therefore, an object of the present invention is to provide a high-reliability MOSFET gate voltage control device which can operate at high speed without increasing the chip area and has a low on-resistance at a low cost.

[0009]

Therefore, the present invention is based on FIG.
As shown in, an N-channel MO that controls the current to the load 4 based on the potential of the gate electrode 8 by connecting the drain electrode 6 and the source electrode 7 to the power supply terminal 9 and the load terminal 10, respectively.
SFET1, a booster circuit 11 connected to the source electrode 7 for generating a voltage higher than a power supply voltage in accordance with the potential of the source electrode, and an external signal entering an input terminal 5 by using the output of the booster circuit 11. In response to the gate control circuit 13 for controlling the potential of the gate electrode 8 and the gate-source voltage of the MOSFET 1 are detected and the voltage is lowered to a predetermined value, or the gate electrode 8 or the source electrode 7 is set to a high potential. When a predetermined time has passed after the operation, the gate control circuit 13
The gate control circuit 13 receives the signal from the potential detection circuit 12, lowers the potential of the gate electrode 8 and restarts the booster circuit 11.

[0010]

With the activation of the booster circuit, sufficient charges are supplied to the gate electrode 8 and the increase in the on resistance of the MOSFET 1 due to the decrease in Vgs is eliminated.

[0011]

FIG. 2 shows an embodiment of the present invention. First, the overall configuration will be described. The gate control circuit 13 connected to the gate electrode 8 of the MOSFET 1, the booster circuit 11 connected to the source electrode 7, and the gate electrode 8 and the source electrode 7.
And a potential detection circuit 12 connected to the.

The gate control circuit 13 controls the potential of the gate electrode 8 to control the conduction state of the MOSFET 1. When the potential of the source electrode 7 is low, the booster circuit 11 accumulates the electric charge in the capacitor 102, transfers the electric charge to the gate electrode 8 as the source potential rises, and raises it to the power supply voltage or more so that the MOSFET 1 is driven. Set to a low on-resistance state.

The potential detection circuit 12 detects the gate-source voltage Vgs, and sends a signal to the gate control circuit 13 to restart the booster circuit 11 when the voltage drops to a predetermined value. That is, when the signal from the potential detection circuit 12 is received, the timer 108 causes the FET 104 of the gate control circuit for a predetermined time corresponding to the charging time of the capacitor 102.
Conduct to turn on the gate electrode 8 and turn off the MOSFET 1. The capacitor 102 of the booster circuit 11 is a MOSF.
When ET1 is off, that is, when the source electrode 7 is at the ground potential, a voltage substantially equivalent to VDD obtained by subtracting the forward voltage (about 0.7 V) of the diode 105 from the power supply voltage VDD is applied and charged.

As the MOSFET 1 is turned on and the potential of the source electrode 7 rises, the potential at the terminal A of the capacitor 102 becomes higher than VDD. As a result, the capacitor 10
The charge of 2 flows into the gate electrode 8 of the MOSFET 1 via the FET 103 of the gate control circuit 13. The movement of charges stops when the source potential becomes stable.

According to this structure, when the PWM operation is performed, as shown in FIG.
Since T1 is turned off, charges are periodically stored in the gate electrode. Therefore, Vgs is kept high and the MOSFET
1 is driven with a low on-resistance.

When operating at full duty, as shown in FIG. 4, the state where no new charges are injected into MOSFET 1 continues for a long time. A high electric field is applied to the gate oxide film, and the gate charge leaks through the oxide film and gradually decreases. During this period, the potential detection circuit 1
Reference numeral 2 monitors Vgs as needed while the signal is being input to the input terminal 5, and outputs a signal to the gate control circuit 13 when the Vgs drops to a predetermined value Vt.

The gate control circuit 13 uses the potential detection circuit 1
In response to the signal from 2, the electric charge stored in the gate electrode 8 of the MOSFET 1 is once extracted and turned off. As a result, the potential of the source electrode 7 drops to the ground potential, and the capacitor 102 is charged by applying a voltage substantially equivalent to the power supply voltage VDD. Gate control circuit 13 is capacitor 1
When the electric charge is sufficiently stored in 02, the potential of the gate electrode 8 is raised again to turn on the MOSFET 1. As a result, the gate electrode 8 is boosted above the power supply voltage.

The time for charging the capacitor 102 is determined by its capacity and the resistor 106. Condenser 102 is 10 nF
However, if the resistance 106 is about 10Ω, the charging time constant is 0.1 μS, which is sufficiently short. This time constant 3
If the time is doubled, the voltage across the capacitor 102 becomes 95% of the applied voltage. Therefore, the off time is about 0.3 μS. Since this time is considerably shorter than the PWM cycle and the motor mechanical time constant, there is almost no effect on the load of the PWM driven motor or the like.

Next, FIG. 5 shows a second embodiment. Here, the potential detection circuit 22 includes a timer 107 therein, and measures the time from when the potential of the gate electrode 8 is boosted or when the potential of the source electrode 7 is increased, and the maximum energization calculated from the gate capacitance and the leakage current is measured. When the available time is reached, a signal is output to the gate control circuit 13 to lower the potential of the gate electrode 8 and charge is stored in the capacitor 102 as in the first embodiment. After that, the timer 108 causes the condenser 1
After a predetermined time corresponding to the charging time of 02, the potential of the gate electrode 8 is raised again.

In the above-described two embodiments, the capacitor 1
Since one terminal of 02 can be shared with the load terminal 10, there is an advantage that only one terminal needs to be added even if it is externally attached, and the chip area and the mounting cost can be reduced.

FIG. 6 shows a third embodiment, in which a booster circuit driving MOSF is provided separately from the main MOSFET 1 for driving a load.
ET31 is provided. The potential detection circuit 12 is MO
When the source-gate electrode voltage Vgs of the SFET 1 is detected to drop to a predetermined value and a signal is output, the gate control circuit 33 lowers only the potential of the gate electrode 38 of the MOSFET 31 for driving the booster circuit 11. This MOSFET
Since the source electrode 37 of 31 is grounded via the resistor 308 which is a dummy load, the source potential drops to the ground level, and the capacitor 102 in the booster circuit 11 starts charging. At that time, the load 4 remains operating. The potential detection circuit may include a timer as in the second embodiment.

The gate voltage control circuit 33 includes a capacitor 10
When sufficient charge is stored in 2, MOSF for driving the booster circuit again
MOSFET by raising the potential of the gate electrode 38 of ET31
31 is turned on. After that, the gate electrode 8 is boosted to the power supply voltage VDD or higher, as in the first embodiment.

In the first and second embodiments, the potential of the gate electrode 8 of the MOSFET 1 is lowered by M when performing the boosting operation.
Since the OSFET 1 is turned off, the operation of the load 4 is interrupted even for a short time, but in the present embodiment, the boosting operation can be performed while the load 4 is being driven.

[0024]

As described above, according to the present invention, a bootstrap circuit that can use a large capacitor as a booster circuit is used as a load control power supply device, and a voltage detection between the gate-source voltage Vgs or the potential of each electrode is detected. Since the circuit is provided and the booster circuit is restarted when a predetermined condition (reduction to a predetermined voltage or a predetermined time elapses), there is the following advantage. (1) It is possible to prevent a decrease in the gate-source voltage Vgs that occurs when the device is driven at full duty for a long time, which is a drawback of the conventional bootstrap circuit, and to always drive the power MOSFET with a low on-resistance. Greatly improved. (2) A high operation speed can be secured, and the PWM frequency can be easily set outside the audible zone.

[Brief description of drawings]

FIG. 1 is a block diagram showing a configuration of the present invention.

FIG. 2 is a diagram showing an embodiment of the invention.

FIG. 3 is a potential diagram during PWM operation.

FIG. 4 is a potential diagram during full duty operation.

FIG. 5 is a diagram showing a second embodiment.

FIG. 6 is a diagram showing a third embodiment.

FIG. 7 is a diagram showing a conventional example.

FIG. 8 is a diagram showing another conventional example.

[Explanation of symbols]

 1 MOSFET 6 Drain Electrode 7 Source Electrode 8 Gate Electrode 11 Booster Circuit 12, 22 Potential Detection Circuit 13, 33 Gate Control Circuit 31 Booster Circuit Driving MOSFET 102 Capacitor 107 Timer 108 Timer

Claims (1)

1. An N-channel MOSFET in which a drain electrode and a source electrode are connected to a power supply terminal and a load terminal, respectively, and the current to the load is controlled based on the potential of the gate electrode.
A booster circuit connected to the source electrode to generate a voltage equal to or higher than a power supply voltage in accordance with the potential of the source electrode; and an output of the booster circuit to adjust the potential of the gate electrode in response to an external input signal. Gate control circuit for controlling and gate control circuit when a gate-source voltage is detected and the voltage drops to a predetermined value, or when a predetermined time elapses from when either the gate electrode or the source electrode is set to a high potential A load control power supply device having a potential detection circuit for outputting a signal to the gate control circuit, the gate control circuit receiving a signal from the potential detection circuit to lower the potential of the gate electrode and restarting the booster circuit. ..