JPH10323026A - Discharge control circuit and series regulator - Google Patents

Abstract

PROBLEM TO BE SOLVED: To gradually shorten the operating time width of an output transistor, by switching the output transistor based on the control signal inputted from the outside, and performing discharge operation based on stopping of the input of the control signal. SOLUTION: According to the decrease of output voltage VO, the voltage level of an input signal IN is decreased, but an input signal CS is further decreased. By action thus operated in a short time, an output OUT1 is placed in a condition fixed to an L level, and the output voltage VO is generated in a ground GND level. Accordingly, when a control signal CTL is placed in an L level, the output voltage VO, according to a decrease of voltage of the input signal CS, is decreased to the ground GND level based on control of a DC/DC converter 11 itself. Here, a time t1 required for decreasing the output voltage VO from fixed voltage to the ground GND level is almost determined by a time constant set by a capacitor 20 and a resistor R3.

Description

DETAILED DESCRIPTION OF THE INVENTION

[0001]

BACKGROUND OF THE INVENTION 1. Field of the Invention The present invention relates to a control circuit for controlling an output voltage of a DC / DC converter or the like.

2. Description of the Related Art In a portable electronic device that operates using a battery as a power source, when it is necessary to supply a DC voltage different from the battery voltage to an internal circuit, a DC / DC converter that operates using a battery as a power source supplies a desired DC voltage. Has been generated. When using multiple power supply voltages,
If the sequence of turning on and off each power supply is not taken into consideration, the device may be damaged. Therefore, it is necessary to appropriately control the rise and fall of the output voltage of the DC / DC converter.

[0003]

2. Description of the Related Art FIG. 7 shows a conventional example of a DC / DC converter used as a power supply circuit of a semiconductor integrated circuit device such as a CPU and a microcomputer.

The DC / DC converter 1 comprises a control circuit 2 formed on a one-chip integrated circuit, and a number of external elements. The control circuit 2 has a control signal C
TL is input, and control circuit 2 is activated based on the input of H-level control signal CTL.

The first output signal OUT1 of the control circuit 2
Is input to the gate of an output transistor 3 composed of an N-channel MOS transistor, and the drain of the output transistor 3 is connected to a power supply Vcc.

The source of the output transistor 3 is connected to the drain of a synchronous rectification transistor 4 composed of an N-channel MOS transistor, and the gate of the transistor 4 is connected to the second output signal OUT2 of the control circuit 2.
And the source is connected to the ground GND.

The source of the output transistor 3 is connected to an output terminal To via an output coil 5. The source of the output transistor 3 is connected to the cathode of the flywheel diode 6, and the anode of the diode 6 is connected to the ground GND. The output terminal To
Is connected to the ground GND via the capacitor 7.

In the DC / DC converter 1 configured as described above, when the control circuit 2 is activated, the control circuit 2 outputs the first and second output signals OUT1 and OUT2. The first and second output signals OUT1 and OUT2 are output as complementary pulse signals. Therefore,
The output transistor 3 and the synchronous rectification transistor 4 are turned on alternately.

By the switching operation of the output transistor 3, the output current of the output transistor 3 is smoothed by the output coil 5 and the capacitor 7. When the output transistor 3 is turned off, the output voltage Vo output from the output terminal To is smoothed by the current supplied from the capacitor 7 to the output coil 5 via the flywheel diode 6.

When the output transistor 3 is turned off, the synchronous rectification transistor 4 is turned on by the second output signal OUT2, and the flywheel diode 6 is turned on.
Is almost "0", and the smoothing efficiency is improved.

At this time, the transistor 4 for synchronous rectification is
Since the output transistor 3 is turned on after being turned off and turned off before the output transistor 3 is turned on, the power supply V
No through current flows from cc to the ground GND via the output transistor 3 and the synchronous rectification transistor 4.

By such an operation, the DC output voltage Vo is output from the output terminal To, and by adjusting the duty of the first and second output signals OUT1 and OUT2 of the control circuit 2, the voltage level of the output voltage Vo is adjusted. Is kept constant.

[0013]

SUMMARY OF THE INVENTION DC / D as described above
In the C converter, when the control signal CTL goes low from the state where the output transistor 3 is performing a switching operation and the control circuit 2 is inactivated, the output transistor 3 and the synchronous rectification transistor 4 are turned off. Will be maintained.

Then, the charge of the capacitor 7 is transferred to the output terminal To.
, The output voltage Vo drops to the ground GND level as shown in FIG.

At this time, the output voltage Vo is changed to the ground GND.
The time required to decrease to the level depends on the current value of the discharge current flowing through the load, and is determined by the time constant of the capacitor 7 and the discharge current flowing through the load. Therefore, the time required for the output voltage Vo to drop to the ground GND level depends on the load connected to the output terminal To.

In such a situation, the time until the power supply to the load is cut off based on the fall of the control signal CTL is not constant, so that in a semiconductor integrated circuit device operating with a plurality of power supply voltages, Therefore, there is a possibility that a CPU or the like connected as a load malfunctions.

Therefore, as shown by a dotted line in FIG. 7, the control signal CTL is applied between the output terminal To and the ground GND.
An N-channel MOS transistor that is turned on when the level becomes the level is connected as the discharging transistor 8. Also,
The current driving capability of the discharging transistor 8 is set to be sufficiently larger than the discharging current driving capability of the load.

With this configuration, the output voltage V based on the fall of the control signal CTL to the L level can be obtained.
The falling speed of o becomes substantially constant based on the time constant of the capacitor 7 and the discharging transistor 8 irrespective of the load.

However, in the above configuration, it is necessary to add a discharging transistor 8 having a large current driving capability.
This raises the cost and hinders downsizing of the DC / DC converter.

On the other hand, if the synchronous rectifying transistor 4 is turned on when the control signal CTL becomes L level, it is not necessary to newly add the discharging transistor 8 as described above.

However, in such a configuration, the control signal C
When TL goes low, transistor 4 for synchronous rectification
Needs to be added to the control circuit 2.
Therefore, there is a problem that the chip area of the semiconductor device including the control circuit 2 increases, which hinders downsizing of the DC / DC converter.

An object of the present invention is to provide a discharge control circuit capable of controlling the fall of the output voltage irrespective of the load when the constant voltage output operation of the output transistor is stopped, and capable of reducing the circuit area. It is in.

[0023]

FIG. 1 is a diagram for explaining the principle of claim 1. That is, the first control unit 33 switches the output transistor 13 based on the control signal CTL input from the outside. The second control unit 34
By the discharging operation based on the stop of the input of the control signal CTL, the operation time width of the output transistor 13 is gradually reduced.

According to a second aspect of the present invention, the second control unit includes a discharge circuit that discharges at a predetermined time constant based on the stop of the input of the control signal, an output signal of the discharge circuit, and a predetermined signal output from the oscillator. A comparison unit that generates an output signal that gradually reduces the operation time width of the output transistor based on a comparison with a triangular wave of a frequency.

According to a third aspect of the present invention, the comparing section includes a voltage signal based on a potential difference between any one of a low-level voltage of a preset reference voltage and an output voltage of the discharge control circuit and the DC output voltage. And an comparator for comparing the output signal of the error amplifier with the triangular wave to generate and output the output signal.

According to a fourth aspect of the present invention, the comparing section includes an error amplifier that outputs a voltage signal based on a potential difference between a preset reference voltage and the DC output voltage, an output signal of the error amplifier, and an output signal of the discharge circuit. And a second comparator for comparing the triangular wave with any low-level voltage among the output voltages to generate and output the output signal.

According to a fifth aspect of the present invention, the discharging circuit includes a capacitor constituting a soft start circuit and a time constant element for discharging a charge of the capacitor with a predetermined time constant based on the stop of the control signal. And a switching circuit for connecting.

According to a sixth aspect of the present invention, the second control section includes a bias maintaining section that maintains the second control section in an active state from the stop of the control signal until the output voltage of the capacitor becomes a predetermined value or less. A circuit is provided.

According to a seventh aspect of the present invention, the time constant element is constituted by a current source through which a constant discharge current flows. According to claim 8, by connecting an output transistor driven by the discharge control circuit between a power supply and a load, the power supply supplied to the load is controlled by the output transistor.

(Operation) In the first aspect, when the input of the control signal CTL is stopped, the operation of the second control unit 34 causes
The operation time width of the output transistor 13 is gradually reduced,
The output voltage of the output transistor 13 decreases.

According to another aspect of the present invention, an output signal of a discharge circuit that discharges at a predetermined time constant based on the stop of the input of the control signal;
A triangular wave having a predetermined frequency is compared by a comparator, and the output signal of the comparator gradually reduces the operation time width of the output transistor, thereby lowering the output voltage of the output transistor.

According to a third aspect of the present invention, a voltage signal based on a potential difference between any one of a low-level voltage of the preset reference voltage and the output voltage of the discharge circuit and the DC output voltage is output from the error amplifier. You. An output signal of the error amplifier and the triangular wave are compared by a comparator to generate an output signal, and the operation time width of the output transistor is gradually reduced by the output signal.

According to the present invention, a voltage signal based on a potential difference between a preset reference voltage and a DC output voltage is output from the error amplifier. The comparator compares one of the low-level voltages of the output signal of the error amplifier and the output voltage of the discharge circuit with the triangular wave to generate an output signal, and the output signal determines the operation time width of the output transistor. It is gradually shortened.

According to a fifth aspect of the present invention, the capacitance constituting the soft start circuit is connected to a time constant element for discharging the charge of the capacitance with a predetermined time constant by the switching circuit, thereby forming a discharge circuit.

According to the sixth aspect, the bias maintaining circuit provides:
The second control unit is maintained in an active state from the stop of the control signal until the output voltage of the capacitor becomes a predetermined value or less.
According to the seventh aspect, the discharge current of the capacitor is discharged via the current source, and the output voltage of the discharge circuit decreases linearly.

According to the present invention, when the input of the control signal is stopped, the voltage supplied from the output transistor to the load is gradually reduced by the operation of the discharge control circuit.

[0037]

BEST MODE FOR CARRYING OUT THE INVENTION

(First Embodiment) FIG. 2 shows a first embodiment in which the present invention is embodied in a DC / DC converter.

The DC / DC converter 11 comprises a control circuit 12 formed on a one-chip integrated circuit, and a number of external elements. A first output signal OUT1 of the control circuit 12 is input to a gate of an output transistor 13 composed of an N-channel MOS transistor,
The drain of the output transistor 13 is connected to the power supply Vcc.

The source of the output transistor 13 is N
The drain of a synchronous rectification transistor 14 composed of a channel MOS transistor is connected to the gate of the transistor 14, the second output signal OUT2 of the control circuit 12 is input, and the source is connected to ground GND.

The source of the output transistor 13 is connected to an output terminal To via an output coil 15. The source of the output transistor 13 is connected to the cathode of the flywheel diode 16, and the anode of the diode 16 is connected to the ground GND. The output terminal To is connected to the ground GND via the capacitor 17.

The operations of the output transistor 13, the transistor 14 for synchronous rectification, the output coil 15, the flywheel diode 16 and the capacitor 17 are the same as those of the conventional example.

The output terminal To is connected to the ground GND via the resistors R1 and R2. The resistors R1, R2
Is to divide the output voltage Vo based on its resistance value in order to detect the output voltage Vo output from the output terminal To. Then, the divided voltage is applied to the control circuit 1.
2 is input as an input signal IN to the minus input terminal of the error amplifier 18a.

The error amplifier 18a has first and second positive input terminals. Of the input voltages of the two positive input terminals, the difference between the lower-level input voltage and the input voltage of the negative input terminal is determined. An output voltage based on the potential difference is output. That is, if any positive input terminal voltage is higher than the negative input terminal voltage, the output voltage increases according to the potential difference, and if any positive input terminal voltage becomes lower than the negative input terminal voltage. The output voltage decreases according to the potential difference.

A first positive input terminal of the error amplifier 18a is connected to a switching circuit 19 and to a ground G via a capacitor 20 connected as an external element.
Connected to ND.

The switching circuit 19 includes an input circuit 3 described later.
1, the capacitor 20 is connected to one of the contacts a and b. The contact a is connected to a current source 21 for supplying a constant current I, and the contact b is connected to the ground G via a resistor R3.
Connected to ND.

Therefore, when the switching circuit 19 is connected to the contact a, the capacitance 2 is supplied by the constant current I supplied from the current source 21.
When 0 is charged and connected to the contact b, the charge of the capacitor 20 is discharged to the ground GND via the resistor R3.

With such a configuration, the error amplifier 1
The charge / discharge voltage of the capacitor 20 is input to the first positive input terminal 8a as an input signal CS. The switching circuit 19 is constituted by the current source 21, the switching circuit 19 and the capacitor 20.
Is switched to the contact point a, a soft start circuit is configured to gradually raise the input signal CS with a time constant set by the constant current I and the capacitance 20.

The reference voltage Vref1 is input to the second positive input terminal of the error amplifier 18a. Reference voltage V
ref1 is a voltage level lower than the power supply Vcc, and is set to a voltage obtained by dividing a desired output voltage Vo by resistors R1 and R2.

The output signal of the error amplifier 18a is input to the positive input terminals of the first and second PWM comparators 22a and 23a. The first and second PWM comparators 2
A triangular wave having a constant frequency is input from the oscillator 24 to the negative input terminals of 2a and 23a. First and second P
The WM comparators 22a and 23a are connected to the bias voltage generation circuit 2
5 is activated by the bias voltage VB supplied from the terminal 5. The reference voltage Vref1 is generated by a reference voltage generation circuit (not shown) based on the bias voltage VB.

The first PWM comparator 22a compares a negative input terminal voltage with a positive input terminal voltage,
When the positive input terminal voltage becomes higher than the negative input terminal voltage, an H-level output signal is output to the first output circuit 26.

The second PWM comparator 23a compares the negative input terminal voltage with the positive input terminal voltage,
When the positive input terminal voltage becomes higher than the negative input terminal voltage, an H level output signal is output to the second output circuit 27.

The first output circuit 26 is provided with a first PWM
An output signal OUT1 obtained by buffering the output signal of the comparator 22a is output to the gate of the output transistor 13, and the second output circuit 27 outputs the first PWM comparator 2
The output signal OUT2 is inverted and the buffered output signal OUT2 is output to the gate of the synchronous rectification transistor 14.

Therefore, the output signal OUT1 becomes a pulse signal having the same frequency as the output signal of the oscillator 24, and the higher the output voltage level of the error amplifier 18a, the longer the time of the H level.

The output signal OUT2 is a pulse signal having the same frequency as the output signal of the oscillator 24,
As the output voltage level of the signal 8a rises, the time during which the signal becomes the L level becomes longer, and it becomes an inverted signal of the output signal OUT1.

It should be noted that the output transistor 13 is supplied from the power supply Vcc.
And the ground GN via the synchronous rectifying transistor 14.
In order to prevent the generation of a through current flowing through D, the output signal OUT2 is set within the range where the output signal OUT1 is at L level.
May be set to the H level. In order to achieve such a configuration, for example, the output signal of the error amplifier 18a may be stepped down by a predetermined voltage width and input to the plus input terminal of the second PWM comparator 23a.

The input signal CS is input to the negative input terminal of the comparator 28, and a low voltage of, for example, about 50 mV is applied to the positive input terminal of the comparator 28 by the reference voltage Vre.
Entered as f2. The comparator 28 receives the input signal CS
Outputs an H-level output signal when the input signal CS becomes lower than the reference voltage Vref2, and outputs an L-level output signal when the input signal CS becomes higher than the reference voltage Vref2.

The output signal of the comparator 28 is inverted by the inverter circuit 29 and input to the OR circuit 30. The inverter circuit 29 includes the bias voltage generation circuit 25
And operates using the bias voltage VB supplied from the power supply. The comparator 28, the inverter circuit 29 and the OR circuit 30 constitute a bias maintaining circuit.

The input circuit 31 has an external control signal CT.
L is input. The input circuit 31 has a control signal CTL.
Becomes H level, an H level output signal is output to the OR circuit 30 and the switching circuit 19. When the control signal CTL goes to L level, an output signal of L level is output.

When the output signal of the input circuit 31 goes high, the switching circuit 19 connects the capacitor 20 to the current source 21 and when the output signal of the input circuit 31 goes low.
The capacitor 20 is connected to the resistor R3.

Next, the DC / DC configured as described above
The operation of the converter will be described with reference to FIG. Control signal C
When TL rises from L level to H level, the output signal of input circuit 31 goes to H level and the output signal of OR circuit 30 goes to H level. Then, the bias voltage VB is supplied from the bias voltage generation circuit 25 to each circuit, the reference voltage Vref1 is supplied to the error amplifier 18a, and the reference voltage Vref2 is supplied to the comparator 28. The switching circuit 19 connects the current source 21 to the capacitor 19.

Then, the voltage level of input signal CS of error amplifier 18 gradually increases due to the time constant of current source 21 and capacitor 20. Then, the input signal IN becomes the ground GN
Even at the D level, the error amplifier 18a outputs the input signal IN
Operates based on a comparison between the input signal C
Since S gradually increases, the output signal does not increase sharply, and the ON time of the output transistor 13 does not become much longer than the OFF time.

Then, as shown in FIG. 3, the power supply voltage Vcc
Also, regardless of the load connected to the output terminal To, the output signal Vo rises slowly with the rise of the input signal CS. Accordingly, the load circuit is prevented from being adversely affected by the rapid rise of the output voltage Vo when the control signal CTL rises.

When the input signal CS exceeds the reference voltage Vref1, the output signal Vo becomes a constant voltage. That is, the error amplifier 18a outputs an output signal based on the potential difference between the input signal IN and the reference voltage Vref1, and outputs the output signal and the reference voltage Vref1.
ref1 is compared by the first and second PWM comparators 22a and 23a. And the first and second PWM comparators 22
Pulse signals are output from the first and second output circuits 26 and 27 as output signals OUT1 and OUT2 based on the output signals of the signals a and 23a.

Then, the output signal O of the first output circuit 26
The output transistor 13 performs a switching operation based on UT1. The output current of the output transistor 13 is smoothed by the output coil 15 and the capacitor 17 by the switching operation of the output transistor 13. When the output transistor 13 is turned off, the output voltage Vo is smoothed by the current supplied from the capacitor 17 to the output coil 15 via the flywheel diode 16.

When the output transistor 13 is turned off, the synchronous rectification transistor 14 is turned on by the output signal OUT 2 of the second output circuit 27, and the forward voltage drop of the flywheel diode 16 is almost “0”.
And the smoothing efficiency is improved.

With such an operation, the input signal IN of the error amplifier 18a based on the output voltage Vo is changed to the reference voltage Vref1.
If it is lower, the output voltage of the error amplifier 18a increases, and the time width of the H level of the first output signal OUT1 increases.

Then, the on-time of the output transistor 13 becomes longer, and the output voltage Vo rises. When the voltage level of the input signal IN of the error amplifier 18a based on the output voltage Vo is higher than the reference voltage Vref1, the output voltage of the error amplifier 18a decreases, and the time width of the H level of the output signal OUT1 decreases. Then, the ON time of the output transistor 13 is shortened, and the output voltage Vo is reduced.

By such an operation, the output voltage Vo converges to a voltage at which the input signal IN of the error amplifier 18a matches the reference voltage Vref1, and becomes a constant voltage. Output voltage V
When the control signal CTL goes low while the voltage o is maintained at a constant voltage, the output signal of the input circuit 31 goes low, and the operation of the switching circuit 19 connects the capacitor 20 to the resistor R3.

Then, the charge of the capacitor 20 is discharged to the ground GND via the resistor R3, and the input signal CS of the error amplifier 18a gradually decreases due to the time constant of the capacitor 20 and the resistor R3. At this time, the input signal CS changes to the reference voltage Vre.
Until f2, the comparator 28 outputs an L-level output signal, the inverter circuit 29 outputs an H-level output signal, and the OR circuit 30 outputs an H-level output signal.

Then, the bias voltage VB is output from the bias voltage generation circuit 25 until the input signal CS falls below the reference voltage Vref2. Based on the bias voltage VB, the reference voltage Vref1 is maintained at a predetermined level.
8a.

In this state, the input signal CS changes to the reference voltage V
When the voltage becomes lower than ref1, the output voltage of the error amplifier 18a decreases, and the time width of the H level of the output signal OUT1 decreases. Then, the ON time of the output transistor 13 is reduced, and the ON time of the synchronous rectification transistor 14 is increased, so that the output voltage Vo is reduced.

As the output voltage Vo decreases, the voltage level of the input signal IN decreases, but the input signal CS further decreases.
T1 is fixed at the L level, and the output voltage Vo
Is at the ground GND level.

Therefore, when the control signal CTL goes to L level, the output voltage Vo is reduced based on the control of the DC / DC converter 11 itself as the voltage of the input signal CS decreases.
Since the output voltage Vo is reduced to the ground GND level, the time t1 required for the output voltage Vo to decrease from the constant voltage to the ground GND level is substantially determined by a time constant set by the capacitor 20 and the resistor R3.

In the DC / DC converter as described above,
The following operation and effect can be obtained. (A) When the H-level control signal CTL is input, the output voltage Vo can be gradually increased by the soft start circuit. (B) When the control signal CTL is maintained at the H level, the output voltage Vo of a constant voltage set by the reference voltage Vref1 and the resistors R1 and R2 can be output. (C) When the control signal CTL falls from the H level to the L level, the output voltage Vo is controlled for a fixed required time without being affected by the load, based on the time constant set by the capacitor 20 and the resistor R3. It can be lowered to the ground GND level. (D) A soft stop circuit that achieves the above effects can be formed by using the capacitor 20 that forms the soft start circuit and by using the resistor R3 and the switching circuit 19. (E) By controlling the discharge of the capacitor 17 by the output transistor 13, the output voltage Vo can be reduced in a fixed time, so that it is not necessary to connect a new element for discharge control. Further, it is necessary to newly provide the comparator 28, the inverter circuit 29, the OR circuit 30, and the like in the control circuit 12, but these are sufficiently small in comparison with the circuit scale of the entire control circuit 12. Therefore, the DC / DC converter 11 does not increase in size. (Second Embodiment) FIG. 4 shows a second embodiment of the present invention. The same components as those in the first embodiment are denoted by the same reference numerals, and description thereof will be omitted.

In the first embodiment, the input signal CS
In this embodiment, the input signal CS is supplied to the first and second PWM comparators 22b and 23a.
b is input to the plus input terminal. That is, only the reference voltage Vref1 is input to the positive input terminal of the error amplifier 18b, and the output signal of the error amplifier 18b is input to the first positive input terminals of the first and second PWM comparators 22b and 23b. At the same time, the input signal CS is input to the second positive input terminals.

The first and second PWM comparators 22b,
23b compares the low-level input voltage and the negative-side input terminal voltage among the input voltages input to the first and second positive-side input terminals.

In such a DC / DC converter, control signal CTL switches from L level to H level,
When the capacitor 20 is connected to the current source 21 via the switching circuit 19, the capacitor 20 is charged, and the voltage level of the input signal CS gradually increases from the ground GND level.

At this time, the output voltage Vo is equal to the ground GND.
Since the level is at the level, the output voltage of the error amplifier 18b increases, but the first and second PWM comparators 22b and 23b perform a comparison operation between the oscillator 24 and the input signal CS. Then, the time width of the H level of the output signal of the first PWM comparator 22b gradually increases, and the time width of the H level of the output signal of the second PWM comparator 23b gradually decreases, so that the output voltage Vo Rises slowly. Therefore, the same soft start operation as in the first embodiment can be performed.

When the input signal CS becomes higher than the output voltage of the error amplifier 18b, the first and second PWM comparators 22
b and 23b are the output signal of the error amplifier 18b and the oscillator 24
Is output, and the output voltage Vo is a constant voltage set based on the reference voltage Vref1 and the resistors R1 and R2, as in the first embodiment.

When the control signal CTL goes low from the state in which the constant output voltage Vo is being output, the capacitance 20
Is connected to the resistor R3 via the switching circuit 19, and the charge of the capacitor 20 is discharged via the resistor R3.

Then, the voltage level of the input signal CS decreases based on the time constant of the capacitor 20 and the resistor R3, and the first and second PWM comparators 22b and 23b output the input signal CS and the output signal of the oscillator 24, respectively. Is output.

Then, the time width of the H level of the output signal OUT1 decreases, the time width of the H level of the output signal OUT2 increases, and the output voltage Vo decreases. Therefore, the same operation and effect as those of the first embodiment can be obtained. (Third Embodiment) FIG. 5 shows a third embodiment of the present invention. In this embodiment, the resistor R3 of the first embodiment is replaced with a current source 32, and the other configuration is the same as that of the first embodiment.

In such a configuration, the discharge current of the capacitor 20 can be kept constant irrespective of its charging voltage, so that the voltage level of the input signal CS can be reduced linearly during the discharging operation of the capacitor 20. . Therefore, in addition to the effects of the first embodiment, the control signal CTL is set to H
When the level is changed from the level to the L level, the output voltage Vo can be reduced linearly.

In each of the above embodiments, DC / DC
Although the present invention is embodied in a control circuit for controlling the output voltage Vo of the converter, the present invention is not limited to a DC / DC converter, and the discharge control circuit of the present invention may be used to control the output current of an output transistor. .

For example, as shown in FIG. 6, a transistor 36 operating as a series regulator for supplying a power supply Vcc to a load circuit 35 is controlled by a discharge control circuit 37 of the present invention. The transistor 36 may be an NPN transistor or a MOS transistor in addition to the PNP transistor.

With such a configuration, when the control signal CTL goes to L level, the falling time of the power supply voltage supplied to the load circuit 35 is discharged by gradually reducing the time width during which the transistor 36 is turned on. It can be controlled by the control circuit 37.

[0087]

As has been described in detail above, the present invention enables the discharge transistor to control the fall of the output voltage irrespective of the load when the constant voltage output operation of the output transistor is stopped, and to reduce the circuit area. A control circuit can be provided.

[Brief description of the drawings]

FIG. 1 is a diagram illustrating the principle of the present invention.

FIG. 2 is a circuit diagram showing a first embodiment.

FIG. 3 is a waveform chart showing an operation of the first embodiment.

FIG. 4 is a circuit diagram showing a second embodiment.

FIG. 5 is a circuit diagram showing a third embodiment.

FIG. 6 is a circuit diagram showing another usage example of the discharge control circuit.

FIG. 7 is a circuit diagram showing a conventional example.

FIG. 8 is a waveform chart showing the operation of the conventional example.

[Explanation of symbols]

 13 output transistor 33 first control unit 34 second control unit CTL control signal

 ──────────────────────────────────────────────────続 き Continued on the front page (72) Inventor Takashi Matsumoto 2-1844-2 Kozoji-cho, Kasugai-shi, Aichi Prefecture Inside Fujitsu VSI Co., Ltd. (72) Inventor Toshiyuki Matsuyama 2-1844-2 Kozoji-cho, Kasugai-shi, Aichi Fujitsu Fujitsu Limited (72) Inventor Seiya Kitagawa Seika Kitagawa 4-1-1 Kamikadanaka, Nakahara-ku, Kawasaki City, Kanagawa Prefecture

Claims (8)

[Claims] An operation time width of the output transistor is reduced by a first control unit that performs switching driving of an output transistor based on a control signal input from the outside and a discharge operation based on stoppage of input of the control signal. A discharge control circuit comprising: a second control section that gradually reduces the length of the discharge control circuit. 2. A discharge circuit for discharging a predetermined time constant based on a stop of input of a control signal, a second control unit, an output signal of the discharge circuit and a triangular wave of a predetermined frequency output from an oscillator. 2. The discharge control circuit according to claim 1, further comprising: a comparison unit configured to generate an output signal that gradually reduces the operation time width of the output transistor based on the comparison. 3. The error detecting unit according to claim 1, wherein the comparing unit outputs a voltage signal based on a potential difference between a low-level voltage of any one of a preset reference voltage and an output voltage of the discharging circuit and the DC output voltage. Amplifier, comparing the output signal of the error amplifier and the triangular wave,
3. The discharge control circuit according to claim 2, further comprising a comparator configured to generate and output the output signal. 4. An error amplifier that outputs a voltage signal based on a potential difference between a preset reference voltage and the DC output voltage, wherein the comparison unit includes: an error amplifier that outputs an output signal of the error amplifier and an output voltage of the discharge circuit; 3. The discharge control circuit according to claim 2, further comprising: a comparator that compares one of the low-level voltages with the triangular wave to generate and output the output signal. 5. The discharging circuit connects the capacitor to a capacitor constituting a soft start circuit and a time constant element for discharging a charge of the capacitor at a predetermined time constant based on the stop of the control signal. 3. The discharge control circuit according to claim 2, further comprising a switching circuit. 6. The control circuit according to claim 1, further comprising a bias maintaining circuit for maintaining the control circuit in an active state from when the control signal is stopped until the output voltage of the capacitor becomes a predetermined value or less. The discharge control circuit according to claim 5. 7. The discharge control circuit according to claim 5, wherein said time constant element comprises a current source for flowing a constant discharge current. 8. A series regulator, wherein an output transistor driven by the discharge control circuit according to claim 1 is interposed between a power supply and a load circuit.