JP2773476B2 - Load control power supply - Google Patents

Description

DETAILED DESCRIPTION OF THE INVENTION

[0001]

BACKGROUND OF THE INVENTION 1. Field of the Invention The present invention relates to a load control power supply device using a power IC for driving a PWM using an N-channel MOSFET.

[0002]

2. Description of the Related Art N-channel MOSFET of a power IC
Is used as a high-side switch, it is necessary to boost the gate electrode to a power supply voltage or higher. A conventional load control power supply for this purpose uses a charge pump circuit as a boosting circuit, as proposed in Japanese Patent Publication No. 58-500835. As shown in FIG. 7, the oscillator 137 oscillates and outputs a signal in response to a signal input to the input terminal 5.
In the device for controlling SFET1, oscillator 137 and M
A diode and a capacitor 2 between the OSFET 1;
A converter 138 having 2 'is provided to double the control voltage of the gate electrode 8 of the MOSFET 1.

[0003] In addition, as shown in FIG.
Is connected between the source electrode 7 and the gate electrode 8 via the gate control circuit 3. In addition, a circuit combining a charge pump and a bootstrap circuit is also used.

[0004]

However, when a charge pump is used, it is difficult to form a large capacitor inside the IC due to an increase in chip area, and it is at most several tens of pF. Therefore, it takes a very long time to charge a very large gate capacitance of several thousands pF level, and high-speed operation cannot be performed. Especially in the case of PWM drive,
The operating frequency must be outside the audible range, but this is difficult.

[0005] Further, since the capacitor is usually made of a MOS structure, if the number of times of charging and discharging increases, a problem arises in the reliability of the gate oxide film, so that the operating frequency of the oscillator must be limited. Furthermore, if the capacitor of the charge pump circuit is externally connected, at least two terminals are required.
The number increases, resulting in an increase in chip area and an increase in mounting cost.

In the bootstrap circuit, a capacitor having an external capacitor and a large capacity can be used, and the problem of the operation speed is improved. However, when operating at full duty, no new charge is supplied to the capacitor 2, and the charge stored in the gate decreases with time due to the leak current of the gate oxide film and the diode. When operated at full duty for a long time, the gate-source voltage Vgs becomes low, and the MOSFE
There is a problem that the driving is performed in a state where the on-resistance of T1 is high.

When the charge pump and the bootstrap circuit are combined, the circuit configuration is naturally complicated. In particular, in the case of PWM driving, a new charge is supplied periodically except at the time of full duty, so that a charge pump is not always required, and there is a problem in mounting and cost.

Accordingly, an object of the present invention is to provide a highly reliable MOSFET gate voltage control device which can operate at high speed without increasing the chip area, has a low on-resistance, and has high reliability.

[0009]

SUMMARY OF THE INVENTION For this reason, the present invention has been described with reference to FIG.
As shown in FIG. 7, an N-channel MO in which a drain electrode 6 and a source electrode 7 are connected to a power supply terminal 9 and a load terminal 10, respectively, and controls a current to the load 4 based on the potential of the gate electrode 8.
An SFET 1, a booster circuit 11 connected to the source electrode 7 for generating a voltage equal to or higher than a power supply voltage in accordance with the potential of the source electrode, and an external signal input to the input terminal 5 using an output of the booster circuit 11. A gate control circuit 13 for controlling the potential of the gate electrode 8 in response thereto, and detecting a gate-source voltage of the MOSFET 1 and reducing the voltage to a predetermined value, or setting the gate electrode 8 or the source electrode 7 to a high potential. When a predetermined time has passed since the start, the gate control circuit 13
The gate control circuit 13 receives the signal from the potential detection circuit 12, lowers the potential of the gate electrode 8, and restarts the booster circuit 11.

[0010]

A sufficient charge is supplied to the gate electrode 8 by the activation of the booster circuit, so that the on-resistance of the MOSFET 1 does not increase due to the decrease in Vgs.

[0011]

FIG. 2 shows an embodiment of the present invention. First, the overall configuration will be described. The gate control circuit 13 connected to the gate electrode 8 of the MOSFET 1, the booster circuit 11 connected to the source electrode 7, the gate electrode 8 and the source electrode 7
Is provided with a potential detection circuit 12 connected to the power supply.

The gate control circuit 13 controls the potential of the gate electrode 8 to control the conduction state of the MOSFET 1. When the potential of the source electrode 7 is low, the booster circuit 11 accumulates the electric charge in the capacitor 102, transfers the electric charge to the gate electrode 8 as the source electric potential rises, makes the electric charge equal to or higher than the power supply voltage, and drives the MOSFET 1 Make the on-resistance low.

The potential detection circuit 12 detects the gate-source voltage Vgs, and when the voltage drops to a predetermined value, sends a signal to the gate control circuit 13 to restart the booster circuit 11. That is, when receiving the signal from the potential detection circuit 12, the timer 108 causes the FET 104 of the gate control circuit to operate for a predetermined time corresponding to the charging time of the capacitor 102.
Is conducted, the gate electrode 8 is grounded, and the MOSFET 1 is turned off. The capacitor 102 of the booster circuit 11 is a MOSF
When ET1 is off, that is, when the source electrode 7 is at the ground potential, a voltage substantially equal to VDD obtained by subtracting the forward voltage (about 0.7 V) of the diode 105 from the power supply voltage VDD is applied and charged.

As the MOSFET 1 is turned on and the potential of the source electrode 7 rises, the potential at the terminal A of the capacitor 102 becomes higher than VDD. As a result, the capacitor 10
The charge of No. 2 flows to the gate electrode 8 of the MOSFET 1 via the FET 103 of the gate control circuit 13. When the source potential is stabilized, the movement of charges stops.

According to this configuration, when the PWM operation is performed, as shown in FIG.
Since T1 is turned off, charges are periodically stored in the gate electrode. Therefore, Vgs is kept high and MOSFET
1 is driven with a low on-resistance.

When operating at full duty, a state in which no new charge is injected into the MOSFET 1 for a long time continues as shown in FIG. A high electric field is applied to the gate oxide film, and the gate charge leaks through this oxide film and gradually decreases.
2 monitors Vgs at any time while a signal is being input to the input terminal 5 and outputs a signal to the gate control circuit 13 when the voltage drops to a predetermined value Vt.

The gate control circuit 13 includes the potential detection circuit 1
In response to the signal from 2, the charge stored in the gate electrode 8 of the MOSFET 1 is once extracted and turned off. As a result, the potential of the source electrode 7 drops to the ground potential, and the capacitor 102 is charged by applying a voltage substantially corresponding to the power supply voltage VDD. The gate control circuit 13 includes the capacitor 1
When a sufficient charge is stored in the gate electrode 02, the potential of the gate electrode 8 is raised again and the MOSFET 1 is turned on. Thereby, the gate electrode 8 is boosted to a power supply voltage or higher.

The time for charging the capacitor 102 is determined by its capacitance and the resistance 106. The capacitor 102 is 10 nF
When the resistance 106 is about 10Ω, the charging time constant is sufficiently short at 0.1 μS. This time constant 3
If the time is doubled, the voltage across capacitor 102 will be 95% of the applied voltage. Therefore, an off time of about 0.3 μS is sufficient. Since this time is considerably shorter than the PWM cycle and the motor mechanical time constant, there is almost no effect on loads such as a motor driven by PWM.

FIG. 5 shows a second embodiment. Here, the potential detection circuit 22 includes a timer 107 therein, measures time from when the potential of the gate electrode 8 is boosted or the potential of the source electrode 7 is increased, and calculates the maximum energization calculated from the gate capacitance and the leak current. When the available time is reached, a signal is output to the gate control circuit 13 to lower the potential of the gate electrode 8 and accumulate the electric charge in the capacitor 102 as in the first embodiment. After that, the capacitor 1
After a lapse of a predetermined time corresponding to the charging time of 02, the potential of the gate electrode 8 is increased again.

In the above two embodiments, the capacitor 1
Since one of the terminals 02 can be shared with the load terminal 10, there is an advantage that only one terminal needs to be added even when externally attached, and the chip area and mounting cost can be reduced.

FIG. 6 shows a third embodiment, in which a booster circuit driving MOSF is provided separately from a load driving main MOSFET1.
ET31 is provided. When the potential detection circuit 12
When detecting a decrease in the source-gate electrode voltage Vgs of the SFET 1 to a predetermined value and outputting a signal, the gate control circuit 33 lowers only the potential of the gate electrode 38 of the MOSFET 31 for driving the booster circuit 11. This MOSFET
Since the source electrode 37 of 31 is grounded via the resistor 308 which is a dummy load, the source potential drops to the ground level, and the capacitor 102 in the booster circuit 11 starts charging. At that time, the load 4 remains operating. The potential detection circuit may include a timer as in the second embodiment.

The gate voltage control circuit 33 includes the capacitor 10
When the charge is sufficiently stored in the MOSF2, the MOSF for driving the booster circuit is again turned on.
Increase the potential of the gate electrode 38 of the ET31 to increase the MOSFET
31 is turned on. Thereafter, as in the first embodiment, the gate electrode 8 is boosted to the power supply voltage VDD or higher.

In the first and second embodiments, the potential of the gate electrode 8 of the MOSFET 1 is lowered when the boosting operation is performed.
Since the OSFET 1 is turned off, the operation of the load 4 is interrupted even for a short time. However, in this embodiment, the boosting operation can be performed while the load 4 is driven.

[0024]

As described above, the present invention provides a load control power supply using a bootstrap circuit in which a large capacitor can be used as a booster circuit, and detects a gate-source voltage Vgs or the potential of each electrode. A circuit is provided, and the booster circuit is restarted when a predetermined condition (reduction to a predetermined voltage or a predetermined time has elapsed) has the following advantages. (1) The voltage Vgs between the gate and the source, which is a drawback of the conventional bootstrap circuit when driving at full duty for a long time, can be prevented from lowering, and the power MOSFET can always be driven with a low on-resistance, thereby improving reliability. Significantly improved. (2) A high operation speed can be secured, and the PWM frequency can be easily set outside the audible band.

[Brief description of the drawings]

FIG. 1 is a block diagram showing a configuration of the present invention.

FIG. 2 is a diagram showing an embodiment of the present invention.

FIG. 3 is a potential diagram during a PWM operation.

FIG. 4 is a potential diagram during a full duty operation.

FIG. 5 is a diagram showing a second embodiment.

FIG. 6 is a diagram showing a third embodiment.

FIG. 7 is a diagram showing a conventional example.

FIG. 8 is a diagram showing another conventional example.

[Explanation of symbols]

 DESCRIPTION OF SYMBOLS 1 MOSFET 6 Drain electrode 7 Source electrode 8 Gate electrode 11 Booster circuit 12, 22 Potential detecting circuit 13, 33 Gate control circuit 31 Booster circuit driving MOSFET 102 Capacitor 107 Timer 108 Timer

Claims (1)

(57) [Claims] An N-channel MOSFET having a drain electrode and a source electrode connected to a power supply terminal and a load terminal, respectively, and controlling a current to a load based on a potential of a gate electrode.
A booster circuit connected to the source electrode to generate a voltage equal to or higher than a power supply voltage according to the potential of the source electrode, and using the output of the booster circuit to change the potential of the gate electrode in response to an external input signal. A gate control circuit for controlling, and a gate control circuit for detecting a gate-source voltage and for elapse of a predetermined time after the voltage drops to a predetermined value or when either the gate electrode or the source electrode is set to a high potential A load control power supply device, wherein the gate control circuit receives a signal from the potential detection circuit, lowers the potential of the gate electrode, and restarts the booster circuit. .