JPH0537382A - D/a converter - Google Patents

Abstract

PURPOSE:To obtain a high precise analog output which is hardly affected by a noise or jitter, in a D/A converter using an over sampling and a noise shaping. CONSTITUTION:In a waveform shaping circuit 14, signals Ba and Bb obtained by dividing a bit stream output B from a noise shaper 12 are respectively supplied to one input terminal of each AND gate 24 and 26, and a clock signal phis on which the noise or jitter may be superimposed, and a signal Nphis obtained by inverting the clock signal phis by an invertor 28 are respectively supplied to the other input terminal of each gate 24 and 26. In an analog conversion circuit 18, waveform shaped outputs Ca and Cb from the gates 24 and 26 are respectively converted into analog signals Fa and Fb by low pass filters 30 and 32, the signal Fa is added to the signal Fb by an adder 34, and an analog output AO can be obtained. The noise or jitter appearing at the waveform shaped outputs Ca and Cb to a direction opposed to each other, can be canceled by the addition of the adder 34.

Description

Detailed Description of the Invention

[0001]

BACKGROUND OF THE INVENTION 1. Field of the Invention The present invention relates to a DA converter using an oversampling technique and a noise shaping (delta sigma modulation) technique, and in particular, the output of a noise shaper is separately provided as a clock signal and an inverted clock signal.
By converting the two waveform shaping outputs obtained by ND calculation into analog signals and adding them, a highly accurate analog output with less influence of noise and jitter can be obtained.

[0002]

2. Description of the Related Art Conventionally, as a DA converter utilizing the oversampling technique and the noise shaping technique, the one exemplified in FIG. 3 has been proposed.

In FIG. 3, 10 is a digital filter for oversampling a multi-bit digital input DI, and 12 is a delta-sigma modulation (fine integration process) of the multi-bit digital signal A from the digital filter 10 to reduce the number of bits. A noise shaper (delta sigma modulator) for transmitting the digital signal B, a waveform shaping circuit 14 for shaping the pulse forming the digital signal B from the noise shaper 12 in accordance with a shaping clock signal, and a frequency f _s. A clock generator for generating a system clock signal φ _s having 18
Is an analog conversion circuit composed of a low-pass filter for filtering the pulse output C from the circuit 14 and converting it into an analog output AO corresponding to the input DI.

The circuit portion surrounded by the alternate long and short dash line IC is configured as a monolithic or hybrid type integrated circuit and arranged in one package, and 16A is a crystal oscillator externally attached to the clock generator 16. I am a child. In some cases, the digital circuit 10 and its related portion (the portion surrounded by the broken line) are integrated into a circuit.

The digital input DI is, for example, waveform data containing 16-bit (1 word) data for each sample, and the data transmission frequency is 44.1 KHz. The frequency of the system clock signal φ _s is 1
6.9 MHz, and the data transmission frequency f _a from the digital filter 10 to the noise shaper 12 is usually f _s.
/ 2 (for example, 8.45 MHz).

The noise shaper 12 is provided to reduce the oversampling frequency in the oversampling DA conversion. Noise shaper 12
When a primary or secondary noise shaper is used as, a pulse density modulation (bit stream) output is obtained as the noise shaper output B, and when a tertiary or higher-order noise shaper is used, the pulse width is output B A modulated output is obtained.

In the noise shaper 12, the digital signal is converted into a representation with a reduced number of bits, and the error caused by such conversion becomes larger in the higher frequency region. That is, FIG. 4 shows the power spectrum of the ideal output of the noise shaper 12.
The system clock frequency f _s of 2 has a sharp peak P _s , and the maximum noise power is at the frequency of f _s / 2 as shown by the solid line. The spectrum shape, f _s, 2f _s, is repeated for each 3f _s ... and f _s, is not shown. White noise that exceeds the ideal state actually exists, but is not shown in FIG.

Since various noises are added to the ideal state of the noise shaper output B due to fluctuations when subjected to digital processing, the output B is directly converted to the analog conversion circuit 18.
When converted to an analog output at, an error occurs due to the noise component. Therefore, the noise shaper output B is fed to the waveform shaping circuit 1
At 4, the waveform is shaped by performing an AND operation on the basis of the system clock signal φ _s and then supplied to the analog conversion circuit 18 to reduce the error due to the noise component.

In the waveform shaping circuit 14, the noise shaper output B and the system clock signal φ _s are substantially multiplied, and the noise is returned to the sum and difference frequencies of the respective frequencies.

[0010]

According to the above-mentioned conventional device, the digital signal sent from the digital filter 10 at the sending frequency f _a flies through the space from the input terminal pin to the clock oscillation terminal (of the crystal oscillator 16A). Enters the connection terminal) as noise. Further, noise and jitter are mixed in the clock signal via the power supply line and the ground line. Therefore, when the spectrum of the output of the clock generator 16 is observed, the frequency component of f _s , which is originally shown as P _{s in} FIG. 5, appears, but the digital signal is transmitted as shown by the broken line in FIG. A component of frequency f _a and _a frequency component near f _a appear as noise. f
_{When a} is f _s / 2, the mixed noise based on f _a appears in f _s / 2 and its vicinity, and the appearance position is shown in FIG.
Then, as indicated by the broken line, it corresponds to the point where the noise power is maximum.

In the waveform shaping circuit 14, aliasing noise occurs due to multiplication of noise mixed into the system clock based on f _a and large noise near f _s / 2 in FIG. 4, but aliasing noise corresponding to the frequency of the difference is generated. Noise occurs in the audible frequency band R shown in FIG. 4, and S / N in this band R
Was making the ratio worse.

In the above description, the noise mixed into the system clock based on f _a has been _a problem. However, in the case where the digital filter 10 is included in FIG. 3 to form an integrated circuit, the digital input D to the digital filter 10 is used.
The noise mixed into the system clock based on the sending frequency f _{i of} I becomes a problem. That is, digital input DI
Is, for example, 44.1K in sample (word) units
Although the transmission frequency is Hz, the input frequency is usually in the bit serial format, and therefore the transmission frequency is about 8 MHz in terms of bits. Therefore, as in the case of f _a , f _i
Based on the above, noise is mixed into the system clock signal φ _s , and aliasing noise is generated in the audible frequency band R based on this mixed noise to deteriorate the S / N ratio.

Further, when noise is mixed into the shaping clock signal in the circuit 14, noise or jitter is generated in the waveform shaping output C, which deteriorates the accuracy of the analog output AO.

An object of the present invention is to provide a highly accurate analog output which is less affected by noise and jitter in the above-mentioned oversampling type DA converter.

[0015]

A DA converter according to the present invention comprises: (a) means for generating a system clock signal; and (b) a delta based on the system clock signal for an oversampled multi-bit digital input. A noise shaper for transmitting a digital signal having a reduced number of bits by sigma modulation, and (c) a waveform shaping circuit for shaping the pulse forming the digital signal from the noise shaper based on the system clock signal. A circuit section for forming a shaping clock signal based on the system clock signal and a shaping inverted clock signal obtained by inverting the shaping clock signal,
A circuit unit that AND-operates the pulse and the shaping clock signal to send out a first waveform shaping output, and a second circuit that AND-operates the pulse and the shaping inverted clock signal.
And a circuit section for transmitting the waveform shaping output of
(D) Each of the first and second waveform shaping outputs is first
And a conversion means for converting into a second analog signal, and (e)
And an addition unit for adding the first and second analog signals and sending an analog output corresponding to the digital input.

[0016]

According to the structure of the present invention, even if noise and jitter are added to the system clock signal, noise and jitter appear in opposite directions in the first and second waveform shaping outputs, and When the analog signals are added after the second and second waveform shaping outputs are converted into analog signals, noise components and jitter components cancel each other out.

[0017]

DETAILED DESCRIPTION OF THE PREFERRED EMBODIMENTS FIG. 1 shows a DA converter according to an embodiment of the present invention. Parts similar to those in FIG. The feature of the embodiment of FIG. 1 is that
It is in the internal configuration of the waveform shaping circuit 14 and the analog conversion circuit 18.

In the waveform shaping circuit 14, the bit stream output B from the noise shaper 12 is delayed by the delay element 2.
It is divided into first and second signals Ba and Bb via 0 and 22, and these signals Ba and Bb are AND gates 24 and 26.
Is supplied to each one of the input terminals. In addition, the clock signal φ
_The shaping clock signal composed of _s is supplied to the other input end of the AND gate 24, and the shaping inverted clock signal Nφ _s obtained by inverting the shaping clock signal φ _s by the inverter 28 is supplied to the other input end of the AND gate 26. To be done. The shaping clock signal may be appropriately processed by delaying the clock signal φ _s .

In the analog conversion circuit 18, AND
First and second waveform shaping outputs C from the gates 24 and 26
a and Cb are low-pass filter (LPF) 30,
32, and the first and second analog signals Fa and Fb from the LPFs 30 and 32 are supplied to the adder 34. The analog output AO is sent from the adder 34.

The operation of the circuits 14 and 18 will be described with reference to FIG. The clock signals φ _s and Nφ _s have a period of 1 / f _s , and often have noise or jitter. The appearance of noise and jitter is opposite between the falling portion of the signal φ _s and the rising portion of the signal Nφ _s . Delay element 20, 22, the signal phi _s, provided in order to avoid signal Ba respectively, the Bb rising and falling overlap relative Enufai _s, the signal as shown in FIG. 2 φ _{s, Nφ The} signals Ba and Bb are delayed with respect to _s .

A first waveform shaping output Ca as shown in FIG. 2 is obtained by ANDing the signals Ba and φ _s , and a second waveform shaping output Ca as shown in FIG. 2 is obtained by ANDing the signals Bb and Nφ _s . The waveform shaping output Cb of is obtained. In this case, noise and jitter appear in directions opposite to each other in the falling portion of the output Ca and the rising portion of the output Cb. Then, such waveform shaping outputs Ca and Cb are set to L.
When the analog signals Fa and Fb are converted by the PFs 30 and 32 and these signals Fa and Fb are added by the adder 34, noises and jitters in the opposite directions cancel each other. As a result, as the analog output AO composed of the output of the adder 34, a highly accurate analog output AO with less influence of noise and jitter can be obtained.

[0022]

As described above, according to the present invention, the output of the noise shaper is ANDed separately with the clock signal and the inverted clock signal to obtain two waveform shaping outputs, and these waveform shaping outputs are respectively analogized. Since the signal is converted into a signal and the analog signal is added to cancel noise and jitter, the accuracy of analog output or the S / N ratio can be improved.

[Brief description of drawings]

FIG. 1 is a circuit diagram showing a DA converter according to an embodiment of the present invention.

FIG. 2 is a timing chart for explaining the operation of the waveform shaping circuit of FIG.

FIG. 3 is a block diagram showing a conventional DA converter.

FIG. 4 is a graph showing a power spectrum of a noise shaper output.

FIG. 5 is a graph showing a power spectrum of a clock output.

[Explanation of symbols]

10: Digital filter, 12: Noise shaper, 1
4: Waveform shaping circuit, 16: Clock generator, 18: Analog conversion circuit, 20, 22: Delay element, 24, 26: A
ND gate, 28: inverter, 30, 32: low pass filter, 34: adder.

Claims (1)

Claim: What is claimed is: 1. (a) means for generating a system clock signal, and (b) bits by delta-sigma modulating an oversampled multi-bit digital input based on the system clock signal. A noise shaper for transmitting a digital signal of which the number is reduced; and (c) a waveform shaping circuit for shaping the pulses constituting the digital signal from the noise shaper based on the system clock signal. A circuit section for forming a shaping clock signal based on the shaping clock signal and a shaping inverted clock signal obtained by inverting the shaping clock signal, and the pulse and the shaping clock signal
A circuit section for performing ND calculation and transmitting a first waveform shaping output;
A circuit section for ANDing the pulse and the inversion clock signal for shaping to output a second waveform shaping output; and (d) first and second waveform shaping outputs respectively.
And a conversion means for converting to a second analog signal, and (e) an addition means for adding the first and second analog signals and sending an analog output corresponding to the digital input.