JPH0537307Y2 - - Google Patents

Description

[Detailed Description of the Invention] (Industrial Application Field) The present invention relates to an interface when an external device such as a microcomputer takes in data from an A/D converter.

(Prior Art) FIG. 3 is a block diagram showing a conventional multi-channel A/D conversion interface. In FIG. 3, the start of A/D conversion is performed by a command from a microcomputer (not shown). The control signal AD GO for starting this conversion is output from the I/O port of the microcomputer and
It is input to the AD GO terminal on the interface board that implements the D conversion interface. This control signal AD GO resets the counter 201 via the flip-flop 202, and the addresses supplied to the analog multiplexer 203 and decoder 204 are initialized. A/D in order from the analog input channel of this initialized address.
Conversion begins. Analog inputs are sequentially selected by the analog multiplexer 203 via the low-pass filter 205 for each channel according to the address from the counter 201, held by the sample-and-hold amplifier 206, and then sent to the A/D converter 2.
A/D conversion is performed at step 07. Every time the conversion of one channel is completed, the data is latched by the latch circuit 208, and the counter 201 is connected to the A/D converter 2.
Conversion Complete from 07 Configure a clock synchronized with CC with a flip-flop1
It is received from the clock delay circuit 209 and counted up. This count-up starts the conversion of the next channel. When the conversion of all channels is completed in this way, the conversion end signal decoded by the decoder 204 is sent to the flip-flop 202 and the counter 201 is reset. At this time, the flip-flop 202 performs the counting operation and A/D until the next control signal AD GO arrives.
Stop D conversion. The microcomputer is
The time until this conversion is completed is measured by a software counter routine, and data is input after waiting for that time.

(Problems to be solved by the invention) The conventional multi-channel A/D conversion interface has the following problems.

a) Since A/D conversion must be started by software, data cannot be read until the data conversion is completed. In other words, even if you read the data from the time when the control signal AD GO for the command to start conversion is issued until the A/D converter finishes the conversion, the previous data will remain, and the data will not be updated, so there is no point in reading it. Therefore, the software does not read it.

b. Repeated conversion of all channels must also be managed by software, which places a burden on the software.

c. Since a large number of TTLs are used to latch the converted digital data, the number of parts increases and the number of manufacturing steps increases.

The present invention has been made to solve the above problems.

(Means for Solving the Problems) The multi-channel A/D conversion interface of the present invention includes an A/D conversion section that periodically A/D converts the multi-channels, and a conversion data input from the A/D conversion section. There are two sets of memory sections that switch to different states for writing and reading to the outside, and counting operations are prohibited during A/D conversion and while reading converted data, and a count is performed for each A/D conversion of one channel. The present invention is characterized in that it includes an address count for writing converted data that operates.

(Function) The A/D conversion section periodically performs A/D conversion while sequentially switching analog inputs of other channels.
Two sets of memory units are used to store the converted data, and the writing and reading of the converted data to the outside are reversed to share the roles, and the converted data is stored and read from the microprocessor at the same time. I can do it.

(Example) An example of this invention will be described below with reference to the drawings. FIG. 1 is a block diagram of one embodiment of the present invention. In FIG. 1, reference numeral 1 denotes an address counter of a memory for writing conversion data, which is composed of a first counter 1a, a second counter 1b, a third counter 1c, and a first gate 1d. Counting operation is prohibited during A/D conversion of the converter and while reading conversion data from a buffer (described later) from a microprocessor (not shown), and the counting operation is performed independently of the timing of the microprocessor due to the cycle of the clock CLK. will be held. 2 is a control signal generation circuit that generates a control signal and a memory write timing signal, and the control signal R/C from the second gate 2a, the third
A memory write timing signal is obtained from gate 2b of. 3 is a memory address switching circuit, which has first and second multiplexers 3a and 3b, the most significant bit of the address counter 1 is connected to the selection terminal SEL of each multiplexer 3a and 3b, and the third counter 1c The address for writing from address counter 1 and the address for reading from microprocessor are determined by the state of output QD (the most significant bit of address counter 1).
ADDR A0 to A4 are exchanged. That is,
For example, when the first multiplexer 3a selects an address for writing, the second multiplexer 3b selects an address for reading, and different addresses are selected. 4 are two sets of memory sections, the first RAM 4a and the second RAM 4a.
It has a RAM 4b and first, second, third, and fourth data switching circuits 4c, 4d, 4e, and 4f each consisting of a tristate buffer. first
Like the multiplexers 3a and 3b, the RAM 4a or the second RAM 4b is designated by the most significant bit of the address counter 1 to switch which one will share the role of the write memory or the read memory. The memory write timing is specified, and the memory address switching circuit 3 inputs a write address or a read address. Furthermore, the data switching circuits 4c, 4d, 4e, and 4f are composed of two types: a path for importing A/D conversion data to the RAM 4a or 4b, which will be described later, and a path for outputting data read from the RAM 4a or 4b to the CPU bus. Accordingly, the active state and high impedance state are determined by the most significant bit of the address counter 1 in the first RAM 4a and the second RAM 4, respectively.
Switches in conjunction with state b. That is, the first
When the RAM is in the data acquisition state, the second switching circuit 4d among the four data switching circuits 4c, 4d, 4e, and 4f is opened and connected to the data from the A/D converter 6. , second
The RAM 4b is in a data read state, and the third switching circuit 4e is opened and connected to the data bus DATA of the microprocessor. Reference numeral 5 denotes an analog switch section, which includes a channel address counter 5a and an analog switch 5b. The channel address counter 5a divides the control signal R/C from the control signal generation circuit 2 and uses it as an address for the analog switch 5b, and the analog switch 5b switches the input channel according to the sequentially updated address. 6 is A/D
A sample-and-hold circuit 6a, which is a conversion section, samples and holds the analog input switched by the analog switch 5b, and performs A/D conversion of multi-channel analog signals inputted via the sample-and-hold circuit 6a at the timing of the control signal R/C. The A/D converter 6b starts with a pulse and performs periodic operation, and the data switching circuits 4d and 4f of the memory unit 4 latch the A/D converted digital data.
It has first and second latch circuits 6c and 6d that output to.

In the circuit configuration shown in Fig. 1, the operation is
This will be explained with reference to timing charts shown in Figures a and 2b. Here, for convenience of explanation, FIG. 2a shows the counter 1 based on the STS from the A/D converter 6b.
The state is shown assuming that a, 1b, and 1c are not stopped, and the time interval between the outputs of the third counter 1c is shortened and displayed. Figure 2b is STS
Indicates the case where the stop is performed by

The analog input is selected by analog switch 5b. The channel is selected by the channel address counter 5a that counts the control signal R/C from the second gate 2a of the control signal generation circuit 2.
selected by. Moreover, this control signal R/C
is a timing pulse for starting A/D conversion, and when a negative timing pulse of the control signal R/C is input to the A/D converter 6b, this causes the A/D conversion to start.
Start D conversion, status signal STS during conversion
Set to “1”. When the conversion is completed, the status signal STS is reset to "0". latch circuit 6c,
6d latches the A/D converted digital data from the falling edge when the status signal STS is released. Here, the 8-bit
The 12-bit data is divided into two circuits for writing to RAMs 4a and 4b. In this way, each time one channel of A/D conversion is completed, the A/D converter 6b
The status signal STS becomes "0", and the counters 1a and 1 are output through the inverter 6e and the gate 1d.
Enable b and 1c and update the memory write address. This address is input to the first and second multiplexers 3a and 3b. The multiplexer 3a or 3b connects the most significant bit QD of the third counter 1c to SEL, and depending on the state, either one selects this address, and the first or second RAM 4
It is output to a or 4b. For example, when the first multiplexer 3a selects a write address, the second multiplexer 3b selects read addresses ADDR A0 to A4, and operate mutually exclusively. The write operation is permitted only when the multiplexers 3a and 3b select the address from the address counter 1, and the write timing starts when the conversion is started by the control signal R/C and the status signal STS is "1".
After the conversion is completed and STS becomes “0”,
written. That is, in this state, the memory write address is given to the first RAM 4a, and the write timing signal is given to the third gate 2b.
When the data is applied to the first RAM 4a from the write address, the data converted by the A/D converter 6b and latched by the latch circuits 6c and 6d is transferred to the first RAM 4a via the data switching circuit 4d. is written to the RAM 4a. This write writes 12-bit data to 8-bit RAM 4a and 4.
Since it is written to b, it is written in two parts. In other words, the address is advanced by one during this period. When one cycle of A/D conversion for all channels is completed, multiplexers 3a and 3b invert their states according to the most significant bit QD of the third counter 1c, and therefore, the data is applied to the first RAM 4a and the second RAM 4b. The read and write addresses are reversed.

Data reading is executed by a standard read command from a microprocessor, but in order to read data, the microprocessor outputs I/OSEL, and the first, second, and third counters 1a, 1
b and 1c are inhibited, read addresses ADDR A0 to A4 are selected, for example, by the second multiplexer 3b, and the data in the second RAM 4b is read out and output to the bus from the third data switching circuit. At this time, in the past, a command to start the conversion was output and the data was read after the conversion time, resulting in a wait for the conversion time, but the microprocessor only needs to read the data. On the other hand, for example, the first
Data that has been sequentially A/D converted is written into the RAM 4a in accordance with the timing controlled by the address counter 1.

(Effects of the invention) As explained above, according to the invention, when performing multi-channel A/D conversion and importing it into a microcomputer, all A/D conversion operations can be automated by hardware, and multi-channel analog 2. Writes A/D-converted data periodically while sequentially switching inputs, and reads data to the outside.
By reversing the roles of each memory section in each pair, it is possible to store conversion data and read it from the microprocessor at the same time, and the microcomputer only needs to read the data, eliminating the need for software control. , the software design burden can be reduced, and two sets of RAM can be used instead of multiple TTLs for data storage elements.
By using this, the number of parts can be reduced, which is effective in simplifying the design of the A/D converter, reducing manufacturing costs, and reducing component costs.

[Brief explanation of the drawing]

Fig. 1 is a block diagram of an embodiment of the present invention;
This figure is also a time chart of one embodiment, and FIG. 3 is a block diagram showing a conventional multi-channel A/D conversion interface. 1...Address counter, 1a, 1b, 1c...
...Counter, 2...Control signal generation circuit, 3...Memory address switching circuit, 3a, 3b...Multiplexer, 4...Memory section, 4a, 4b...
RAM, 4c, 4d, 4e, 4f...data switching circuit, 5...analog switch section, 5a...
Channel address counter, 5b...analog switch, 6...A/D converter, 6a...sample hold circuit, 6b...A/D converter, 6
c, 6d...Latch circuit.

Claims (1)

[Scope of utility model registration request] A/D that periodically converts multi-channel A/D
A conversion unit, two sets of memory units that switch to different states for writing conversion data from the A/D conversion unit and reading the conversion data to the outside, and a counting operation during A/D conversion and while reading conversion data. Forbidden,
A multi-channel A/D conversion interface comprising a converted data writing address counter that counts every A/D conversion of one channel.