JPH0537303A - Data exchange device of d-type flip-flop - Google Patents

Abstract

PURPOSE:To surely execute a data exchange between D-type flip-flops, even if the D-type flip-flops are both placed in distant places due to restrictions of a wiring pattern on a chip, and a delay caused by the wiring capacity of their connecting line can not be disregarded. CONSTITUTION:A timing by which a master circuit and a slave circuit in the inside of D-type flip-flops 7, 8 become a holding state of data, respectively is provided. Accordingly, even in the case it is necessary to place separately the D-type flip-flops 7, 8 on a chip, a data exchange can be executed surely between the D-type flip-flops 7, 8.

Description

Detailed Description of the Invention

[0001]

BACKGROUND OF THE INVENTION 1. Field of the Invention The present invention relates to a D-type flip-flop data exchange apparatus suitable for exchanging data between two D-type flip-flops.

[0002]

2. Description of the Related Art FIG. 4 is a diagram showing a conventional D-type flip-flop data exchange apparatus, for example, an internal configuration of a microcomputer. In FIG.
(1) and (2) are D-type flip-flops, and the Q ₁ terminal output of the D-type flip-flop (1) is a D-type flip-flop.
(2) is transferred as the D ₂ terminal input, and the Q ₂ terminal output of the D type flip-flop (2) is the D type flip flop.
It is designed to be transferred as the D ₁ terminal input of (1).
That is, the input / output paths of the D-type flip-flops (1) and (2) form a loop.

A control signal AB is applied to one input of each of the OR gates (3) and (4). Here, the input / output of the D-type flip-flop (1) is connected not only to the D-type flip-flop (2) but also to other configurations such as a data bus.
It may be necessary to stop the input / output operation of the D-type flip-flop (2) and perform data transfer between the D-type flip-flop (1) and other components. The control signal A is used at this time. That is, the control signal A becomes "1" when the D-type flip-flop (1) is operated and "0" when both the D-type flip-flops (1) and (2) are operated. The same applies to the D-type flip-flop (2), and the control signal B is "1" when operating the D-type flip-flop (2) and "0" when operating both the D-type flip-flops (1) and (2). It will be. Also, the OR gate (3)
The other input of (4) is D-type flip-flop (1) (2)
Exchange instruction signal E for instructing data exchange between the two
XCHNG is reversely applied. That is, the exchange instruction signal EX
CHNG is "0" when data is exchanged and "1" when data is not exchanged.

The outputs of the OR gates (3) and (4) are applied to one input of the AND gates (5) and (6), respectively, and the clock CLOCK is commonly applied to the other input. That is, when the output of the OR gate (3) is "1", specifically, only when the control signal A is "1" or the exchange instruction signal EXCHNG is "0", the clock CLOCK is output from the AND gate (5). By applying the output of the AND gate (5) to the CLK ₁ terminal, the D-type flip-flop (1) operates. Similarly, the clock CLOCK is output from the AND gate (6) only when the output of the OR gate (4) is "1", specifically, when the control signal B is "1" or the exchange instruction signal EXCHNG is "0". Then, the output of the AND gate (6) is applied to the CLK ₂ terminal to operate the D-type flip-flop (2).

Here, the internal structure of the D-type flip-flops (1) and (2) will be described with reference to FIG. Both of the D-type flip-flops (1) and (2) basically have a structure in which a master circuit is provided in the front stage and a slave circuit which receives the master circuit output is provided in the rear stage. Inside the D-type flip-flop (1), the inverters (7) and (8) and the transfer gate
(9) constitutes a master circuit, and the inverters (10), (11) and the transfer gate (12) constitute a slave circuit, and the master circuit has a transfer gate for receiving the D ₁ terminal input as an input. (13) is provided, and a transfer gate (14) for taking in the output of the master circuit is provided at the input of the slave circuit.
Further, the transfer gates (9) and (14) are on / off controlled by directly applying the CLK ₁ terminal input, and the transfer gates (12) and (13) are on / off controlled by inverting the CLK ₁ terminal input. . That is, the transfer gates (9) (14) and the transfer gates (12) (13) operate complementarily. Where D-type flip-flop
(2) Concerning the internal configuration, D-type flip-flop (1)
Therefore, the internal structure of the D-type flip-flop (1) is shown with a dash.

The operation of FIG. 4 will be described below with reference to the timing chart of FIG. D-type flip-flop (1)
When exchanging data between (2), control signal AB
Are both "0". In this state, when it is not instructed to exchange data, the exchange instruction signal EXCHNG is "1", so that the outputs of the AND gates (5) and (6) are both "0". That is, the master circuit and the slave circuit inside each of the D-type flip-flops (1) and (2) are cut off, the slave circuits inside the D-type flip-flops (1) and (2) form a loop, and the D-type flip-flop (1) (2) The internal master circuit enters the input state without forming a loop. For example,
The data Y is held by the slave circuit of the D-type flip-flop (1) and taken into the master circuit of the D-type flip-flop (2) via the Q ₁ terminal and the D ₂ terminal, and
It is assumed that the data X is held in the slave circuit of the D-type flip-flop (2) and taken in by the master circuit of the D-type flip-flop (1) via the Q ₂ terminal and the D ₁ terminal (this is the other party. The timing Z _i is for fetching the data held by the D-type flip-flop).

From this state, when it is instructed to exchange data and the exchange instruction signal EXCHNG becomes "0",
At the timing when the clock CLOCK becomes “1”, the CLK ₁ and CLK ₂ inputs of the D-type flip-flops (1) and (2) both become “1”. That is, the D-type flip-flops (1) and (2) are cut off, the master circuit of the D-type flip-flops (1) and (2) forms a loop and becomes a holding state, and the D-type flip-flops (1) and (2) The slave circuit enters the holding data of the preceding master circuit without forming a loop.
Specifically, the data X is held in the master circuit of the D-type flip-flop (1) and is output from the slave circuit, and the data Y is held in the master circuit of the D-type flip-flop (2) and is output from the slave circuit. Is output. That is, the data output from the D-type flip-flops (1) and (2) are exchanged (this is the timing Z _mo for holding and outputting the data fetched from the counterpart D-type flip-flop).

Between the D-type flip-flops (1) and (2)
Data exchange is completed and the exchange instruction signal EXCHNG is restarted.
And "1", the C of D-type flip-flops (1) and (2)
LK ₁, CLK₂Since both inputs are "0",
Z_iIt becomes the operation of. That is, data X is a D flip
It is held by the slave circuit of flop (1) and Q₁end
Child and D₂The D-type flip-flop (2)
The data Y is taken into the star circuit and the data Y
It is held by the slave circuit of the flip-flop (2) and Q₂
Terminal and D₁The D-type flip-flop (1)
It will be taken into the master circuit.

By repeating the above operation, data exchange of the D-type flip-flops (1) and (2) is performed.

[0010]

When the circuit shown in FIG. 4 is used as an internal configuration of an integrated circuit such as a microcomputer, the D-type flip-flops (1) (2) are limited due to the restriction of the circuit layout pattern on the chip. ) May have to be placed at separate locations. In this case, AND
Output of gate (5) and CLK of D-type flip-flop (1)
The length of the connecting line L _{1 to} the ₁ terminal and the length of the connecting line L ₂ between the output of the AND gate (6) and the CLK ₂ terminal of the D-type flip-flop (2) are extremely different. , The wiring capacitance of one of the connection lines cannot be ignored. For example, if the direction of the length of the connection line L ₂ has become greater than the connection lines L _1, compared to an AND gate (5) output for transmission to the CLK ₁ terminal of the D-type flip-flop (1), Output of AND gate (6) to D-type flip-flop (2)
Therefore, a delay will occur in transmitting the signal to the CLK ₂ terminal. This transmission delay causes the problem shown in FIG. This problem will be described below.

First, in order to exchange data between the D-type flip-flops (1) and (2), when the control signal AB is both "0" and the exchange instruction signal EXCHNG is "1",
The data Y is held in the slave circuit of the D-type flip-flop (1) and taken in by the master circuit of the D-type flip-flop (2) via the Q ₁ terminal and the D ₂ terminal (timing Z _i1 ). X is a D-type flip-flop
It is held in the slave circuit of (2) and also has the Q ₂ terminal and D ₁
It is in a state of being taken into the master circuit of the D-type flip-flop (1) via the terminal (timing Z _i2 ).

From this state, the exchange instruction signal EXCHNG
Becomes "0", the CLK ₁ input of the D-type flip-flop (1) becomes "1" at the timing when the clock CLOCK becomes "1", and the data X becomes the D-type flip-flop (1).
_Is held by the master circuit and is output from the slave circuit (timing Z _mo1 ). But at this time, AND
Even if “1” is simultaneously output from the gates (5) and (6), the wiring capacitance of the connection line L ₂ cannot be ignored, so the CLK ₂ terminal input of the D-type flip-flop (2) is the D-type flip-flop ( with a delay from the timing of CLK ₁ terminal 1) is "1", becomes "1" (timing Z _MO2). Therefore, D
The master circuit of the flip-flop (2) is originally data Y
However, the data X output from the D-type flip-flop (1) is taken in, and the data X is retained in the master circuit again at the timing Z _mo2 inside the D-type flip-flop (2). At the same time, the slave circuit outputs the data again, which causes a problem that data cannot be exchanged between the D-type flip-flops (1) and (2).

Therefore, according to the present invention, the D-type flip-flops (1) and (2) are restricted by the restriction of the wiring pattern on the chip.
Even if the two are arranged at distant places and the delay due to the wiring capacitance of these connection lines cannot be ignored, the D-type flip-flops (1) and (2) can reliably exchange data. It is an object to provide a data exchange device for flip-flops.

[0014]

The present invention has been made to solve the above problems, and is characterized in that a master circuit for inputting, holding and outputting data and an output of the master circuit are provided. In a data exchange device of a D-type flip-flop for exchanging data between a first D-type flip-flop and a second D-type flip-flop having a slave circuit for inputting, holding and outputting data, the master circuit is provided. First means for bringing the slave circuit into an input state and holding and outputting the slave circuit; second means for holding the master circuit in a holding state and holding and outputting the slave circuit; and the master circuit. Third means for holding and outputting the slave circuit and for inputting and outputting the slave circuit.

[0015]

According to the present invention, since the master circuit and the slave circuit inside the first and second D-type flip-flops are provided with the timings in which the data is held, respectively, the first and second D-type flip-flops are provided. Data can be reliably exchanged between the first and second D-type flip-flops even in the case where they must be arranged separately on the chip.

[0016]

The details of the present invention will be described in detail with reference to the drawings. FIG. 1 is a diagram showing the device of the present invention, which is assumed to be provided inside a microcomputer, for example.
In FIG. 1, (7) and (8) are the first and second D-type flip-flops, respectively.
_{The 1-} terminal output is taken as the D ₂ terminal input of the D-type flip-flop (8), and the Q ₂ terminal output of the D-type flip-flop (8) is taken as the D _1- terminal input of the D-type flip-flop (7), that is, The input / output paths of the D-type flip-flops (7) and (8) form a loop.

The control signal AB is applied to one input of each of the OR gates 9 and 10. Here, the input / output of the D-type flip-flop (7) is connected not only to the D-type flip-flop (8) but also to other components such as a data bus.
It may be necessary to stop the input / output operation of the D-type flip-flop (8) and perform data transfer between the D-type flip-flop (7) and other components. The control signal A is used at this time. That is, the control signal A becomes "1" when operating the D-type flip-flop (7) and becomes "0" when operating the D-type flip-flops (7) and (8) together. The same applies to the D-type flip-flop (8), and the control signal B is "1" when operating the D-type flip-flop (8) and "0" when operating the D-type flip-flops (7) and (8) together. It will be. Also, the OR gate (9) (1
The other input of (0) is an exchange instruction signal EX for instructing data exchange between the D-type flip-flops (7) and (8).
CHNG is reversely applied. That is, the exchange instruction signal EXC
HNG is "0" when data is exchanged and "1" when data is not exchanged. Further, the exchange instruction signal EXC
HNG is also applied to the EX ₁ and EX ₂ terminals of the D-type flip-flops (7) and (8).

The outputs of the OR gates (9) and (10) are applied to one input of the AND gates (11) and (12), respectively, and the clock CLOCK is commonly applied to the other input. That is, the clock CLOCK is output from the AND gate (11) only when the output of the OR gate (9) is "1", specifically, when the control signal A is "1" or the exchange instruction signal EXCHNG is "0". The D-type flip-flop (1) operates by applying the output of the AND gate (11) to the CLK ₁ terminal. Similarly, the clock CLOCK is output from the AND gate (12) only when the output of the OR gate (10) is "1", specifically, when the control signal B is "1" or the exchange instruction signal EXCHNG is "0". Then, the output of the AND gate (12) is applied to the CLK ₂ terminal to operate the D-type flip-flop (8).

When the D-type flip-flops (7) and (8) are arranged on the microcomputer chip, the D-type flip-flops (7) and (8) are arranged at distant positions on the chip due to the restriction of the arrangement pattern. Shall be done. In this case, the output of the AND gate (11) and the D-type flip-flop
Compared to the connection line L ₁₁ with the CLK ₁ terminal in (7), AN
Output of D gate (12) and CL of D type flip-flop (8)
The connecting line L _{1 2 to} the K ₂ terminal becomes longer,
Further, the exchange instruction signal EXCHNG is compared with the connection line L ₂₁ for applying the exchange instruction signal EXCHNG to the EX ₁ terminal of the D type flip-flop (7).
It is assumed that the connection line L _{2 2} for applying to the EX ₂ terminal in (8) is longer. As a result, the connecting line L
Resistance _{component 12} has (13) and the line capacitance (14), connecting lines L ₂₂
The resistance component (15) and the wiring capacitance (16) of the device cannot be ignored.

Here, the internal configuration of the D-type flip-flops (7) and (8) connected as shown in FIG. 1 will be specifically described with reference to FIG. Inside the D-type flip-flop (7), the inverters (17) and (18) and the transfer gate (19) form a master circuit, and the transfer gate (19) is used for holding data in the master circuit. Further, the inverters (20) (21) and the transfer gate (22) form a slave circuit, and the transfer gate (22) is used for holding data in the slave circuit. (twenty three)
Is a transfer gate for taking the D ₁ terminal input into the master circuit, and (24) is a transfer gate for taking the holding output of the master circuit as an input of the slave circuit. The transfer gate (23) is on / off controlled by the exchange instruction signal EXCHNG, the transfer gate (19) is on / off controlled by an inverted signal of the exchange instruction signal EXCHNG obtained via the inverter (25), and the transfer gate (24) is AND gate (11)
ON / OFF is controlled by a clock CLOCK obtained from the transfer gate 22 and ON / OFF is controlled by an inverted clock obtained via an inverter 26.
Here, since the internal structure of the D-type flip-flop (8) is the same as the internal structure of the D-type flip-flop (7), the reference numerals of the constituent elements of the D-type flip-flop (7) are shown with dashes. And In the D-type flip-flops (7) and (8), transfer gates (23) (23 '), (19) (19'), (2
4) (24 ') and (22) (22') correspond to the first, second, third, and fourth gates, respectively.

Hereinafter, with reference to the timing chart of FIG.
The operation of FIG. 1 will be described. First, D-type flip-flop
When data is exchanged between (7) and (8), the control signal AB is
Both are “0”. In this state, the exchange instruction signal EXCH
When NG is "1", both OR gates (9) and (10) outputs
Since it is "0", the clock CLO is output from the AND gates (11) (12).
CK is not output, and the AND gate (11) (12) outputs are also
It is "0". This allows the D-type flip-flop
(7) (8) The internal master circuit and slave circuit are shielded respectively.
Turned off, master in D-type flip-flops (7) (8)
-The circuit is in the data input state without forming a loop.
Therefore, the slave circuit forms a loop and
Become. For example, the data Y is a D-type flip-flop (7)
It is held by the slave circuit and Q₁Terminal, D₂Terminal and
And transfer gate (23 ')
It is taken into the master circuit of (8) (timing
Z _i1), The data X is a D-type flip-flop (8)
Is held by the circuit₂Terminal, D₁Terminal and tiger
D-type flip-flop (7) via the transfer gate (23)
Is in the state of being taken into the master circuit of
Z_i2). Here, the exchange instruction signal EXCHNG of "1",
OR gates (9) (10) that receive the signal and output "0",
A which receives the output of the OR gates (9) and (10) and outputs "0"
The ND gates (11) and (12) form the first means.

From this state, the D-type flip-flop (7)
Data exchange between (8) is instructed, and exchange instruction signal EXCH
When NG becomes "0" and the clock CLOCK is "0", the master circuit and the slave circuit inside the D-type flip-flop (7) are still in the cutoff state,
Furthermore, the D-type flip-flops (7) and (8) are cut off from each other,
These master circuit and slave circuit form a loop and are in a data holding state. That is, the master circuit and the slave circuit in the D-type flip-flop (7) are in the state of holding the data X and Y, respectively (timing Z _m1 ). On the other hand, the exchange instruction signal EXCHNG applied to the EX ₂ terminal of the D-type flip-flop (8) has a delay time determined by the delay components of the resistor (15) and the capacitor (16) as compared with the input of the EX ₁ terminal. Becomes "0". In this case, the clock CLOCK
Is 0, the master circuit and the slave circuit inside the D-type flip-flop (8) are still in the cut-off state, and the D-type flip-flops (7) and (8) are cut off from each other, and these master circuits are cut off. Also, the slave circuit forms a loop and enters a data holding state. That is, the master circuit and the slave circuit in the D-type flip-flop (8) are in the holding state of the data Y and X, respectively (timing Z _m2 ).
That is, all the master circuits and slave circuits inside the D-type flip-flops (7) and (8) independently form a loop and are in a data holding state. Here, the exchange instruction signal EXCHNG of "0", the OR gates (9) and (10) which receive the signal and output "1", and the clock CLOC of "0"
AND gates (11) (12) which receive K and output "0",
It constitutes a second means.

Then, in the middle of the timing Z _m2 , that is, D
When the clock CLOCK rises to "1" while the master circuit and the slave circuit of the type flip-flop (8) hold the data Y and X respectively, the CLK ₁ terminal input becomes "1", so that the D type The master circuit of the flip-flop (7) is still in the data holding state, and the slave circuit is in the data input state without forming a loop. That is, in the D-type flip-flop (7), the data X continues to be held in the master circuit and is output from the slave circuit in the subsequent stage. At this time, since the D ₂ terminal input of the D-type flip-flop (8) is cut off by turning off the transfer gate (23 ′), the data output from the slave circuit of the D-type flip-flop (7) It is possible to prevent X from being mistakenly taken into the master circuit of the D-type flip-flop (8) (timing Z _o1 ). On the other hand, the CLK ₂ terminal input of the D-type flip-flop (8) has a higher resistance (13) and a higher capacitance than the CLK ₁ terminal input.
It rises to "1" with the delay time determined by the delay component of (14). That is, in the middle of the timing Z _o1 , that is, _when the data X is held in the master circuit of the D-type flip-flop (7) and is output from the slave circuit, C
When the LK ₂ terminal input rises to “1”, the master circuit of the D-type flip-flop (8) continues to hold data, and the slave circuit does not form a loop and the master circuit hold data of the preceding stage is input. It becomes a state. That is, in the D-type flip-flop (8), the data Y is continuously held in the master circuit and is output from the slave circuit in the subsequent stage (timing Z _o2 ). And
The end of data exchange is instructed, and exchange instruction signal EXCHN
When G becomes "1", the operations at the timings Z _i1 and Z _i2 are executed again. Here, the exchange instruction signal EXCHNG of “0”, the OR gates (9) and (10) that receive the signal and output “1”, the outputs of the OR gates (9) and (10) and the clock CLOCK of “1” are output. The AND gates (11) and (12) that receive and output "1" constitute the third means.

From the above, the D-type flip-flops (7) (8)
It means that the data exchange of the data X and Y has been performed. The data exchange of the data X and Y can be performed any number of times by repeatedly executing the operations of the above-mentioned timings Z _i1 , Z _m1 , Z _o1 and Z _i2 , Z _m2 , Z _o2 . In addition, the circuit of this embodiment can deal with the maximum delay of the connection lines L _{12 and} L ₂₂ up to 1/2 cycle of the clock CLOCK. The reason is that if the delay time exceeds 1/2 cycle of the clock CLOCK, the microcomputer itself malfunctions and it is not necessary to deal with it.

Therefore, according to the present embodiment, the D-type flip-flops (7) and (8) must be arranged at distant positions due to the restriction of the arrangement pattern on the microcomputer chip, and these connecting lines are Even if the transmission delay based on the wiring capacity of the D-type flip-flops (7) and (8) cannot be ignored, data exchange can be reliably performed between the D-type flip-flops (7) and (8).

[0026]

According to the present invention, since the master circuit and the slave circuit in the first and second D-type flip-flops are provided with the timings for holding the data, the first and second D-type flip-flops are provided. Even if the flip-flops have to be placed separately on the chip, the first and second
Data can be reliably exchanged between the D-type flip-flops.

[Brief description of drawings]

FIG. 1 is a diagram showing a device of the present invention.

FIG. 2 is a diagram showing a configuration of a D-type flip-flop used in the device of the present invention.

FIG. 3 is a timing chart showing the operation of the device of the present invention.

FIG. 4 is a diagram showing a conventional device.

FIG. 5 is a diagram showing a D-type flip-flop used in a conventional device.

FIG. 6 is a timing chart showing the operation of the conventional device.

FIG. 7 is a timing chart showing a defective operation of the conventional device.

[Explanation of symbols]

(7) (8) D-type flip-flop (9) (10) OR gate (11) (12) AND gate

Claims (2)

[Claims] 1. A first D-type flip-flop and a second D-type flip-flop having a master circuit for inputting, holding and outputting data and a slave circuit for inputting, holding and outputting output data of the master circuit. In a data exchange device of a D-type flip-flop for exchanging data between two devices, first means for putting the master circuit in an input state and holding and outputting the slave circuit, and holding the master circuit in a holding state And second means for holding and outputting the slave circuit, and third means for holding and outputting the master circuit and inputting and outputting the slave circuit. A data exchange device for a D-type flip-flop. 2. The first and second D-type flip-flops are first for inputting data to the master circuit.
Gate, a second gate for holding data in the master circuit, a third gate for inputting output data of the master circuit to the slave circuit, and a data for holding data in the slave circuit A fourth gate of the first and fourth gates is opened by the first means, the second and fourth gates are opened by the second means, and the second and fourth gates are opened by the second means. 2. The D-type flip-flop data exchange device according to claim 1, wherein the third gate is opened by the third means.