JPH05289767A - Signal transmission method between arithmetic blocks - Google Patents

Abstract

PURPOSE:To perform the arithmetic processing for the operation within an arithmetic block at such a high speed as to only requiring the time of delay which is specific to a transistor. CONSTITUTION:Within each arithmetic block 1, 2, 3, an operation is performed by the frequency of a clock CK0 to be generated by a clock generation circuit 4 (a ring oscillator, for instance) provided at the inside of a LSI. Data is inputted from input terminals I1 to I9 and the cylce of a clock CK2 synchronized with this input is more than three times of the cycle of the clock CK0. In a clock control circuit 5, the rise of a clock CK5 is detected, the three cycles of the clock CK0 is outputted as a clock CK1. As for the remaining time, a Low is continued to be outputted as a clock CK1. A three-input selector 11 selects the output by the cycle when an I1 side, an I2 side, an I3 side are successively synchronized with the clock CK. In the same way, three-input selectors 12, 13 also select the output successively.

Description

Detailed Description of the Invention

[0001]

BACKGROUND OF THE INVENTION 1. Field of the Invention The present invention relates to a signal transmission method between operation blocks using a clock for operating the inside of an LSI.

[0002]

2. Description of the Related Art When an arithmetic unit is converted into an LSI, the LS
It is necessary to determine the layout (arrangement) of transistors and wirings connecting transistors inside the I. in this case,
The operation device is divided into several operation blocks, the layout is considered for each operation block, the layout of each operation block is decided, and then the layout between operation blocks is considered, which is a hierarchical method. .. This is because if the entire arithmetic unit is regarded as one circuit, it is too large to be laid out at once.

Since the circuit scale of the layout of each operation block is small, they can be arranged densely. Therefore,
The length of the wiring connecting the transistors is also short, and the time required for a signal to propagate through the wiring (delay due to the wiring) is so small that it can be ignored. In other words, the data is processed within the calculation block only for the delay specific to the transistor.

On the other hand, in the case of the layout of the operation blocks, the sizes of the operation blocks are not uniform, so that it is difficult to shorten the wiring connecting the operation blocks and the wiring becomes long. .. Therefore, the delay due to the wiring is large.

However, when an arithmetic device is to be integrated into an LSI, even if a logic circuit is created in consideration of only a delay peculiar to a transistor, when actually formed into an LSI, the operation block operates normally. There is a case that the data transfer between the two does not work properly (because of the delay time due to the wiring).

As a result, there is a possibility that the operation may be performed only at a low speed.

[0007]

The problem to be solved is that the data transfer between the operation blocks does not operate normally (because the delay time due to the wiring takes too long).

[0008]

According to the present invention, for a clock for operating the inside of an LSI, the absolute time of one cycle in which data is transferred between the operation blocks in the layout is defined as the absolute time of the data between the operation blocks. It is a signal transmission method between arithmetic blocks characterized by making it longer than the absolute time of one cycle without passing.

[0009]

According to this, in the clock for operating the inside of the LSI, the absolute time of one cycle in which data is transferred between operation blocks is the absolute time of one cycle in which data is not transferred between operation blocks. By setting the length longer than that, it is possible to perform the arithmetic processing in the arithmetic block at a high speed, that is, only the delay peculiar to the transistor during the time when the data is not transferred between the arithmetic blocks.

[0010]

EXAMPLE An example of the present invention is shown in FIG. The calculation blocks 1, 2, and 3 are the above-mentioned calculation blocks. It is assumed that the operation block operates in the frequency of the clock CK ₀ generated by the clock generation circuit 4 (for example, a ring oscillator) provided inside the LSI. However, the data is passed between the operation blocks by the wiring 1
It is assumed that ₀ and 20 are long and cannot be performed at the frequency of the clock CK ₀ described above.

As shown in FIG. 2, the operation block 1 uses the data A ₁ in the third cycle, the data A _{2 in} the fourth cycle, and the data A ₂ in the fourth cycle.
The data A ₃ is received from the input terminal 1 in the cycle, the desired operation P1 is performed, and the result OP ₁ is output from the output terminal in the sixth cycle.

As shown in FIG. 2, the operation block 2 receives the data OP ₁ from the input terminal 2 in the 6th cycle, the data A _{4 in} the 6th cycle and the data A ₅ , 8 in the 7th cycle.
The data A ₆ is received from the input terminal 1 in the cycle, the desired operation P2 is performed, and the result OP ₂ is output from the output terminal in the 9th cycle.

As shown in FIG. 2, the operation block 3 receives the data OP ₂ from the input terminal 2 in the 9th cycle, the data A _{7 in} the 9th cycle, the data A ₈ in the 10th cycle,
In the 11th cycle, receive data A ₉ from input terminal 1,
Perform a desired operation P3, and outputs the result to OP ₃ from the output terminal 12 cycle.

In this way, the calculation result is output from the output terminal O.
OP₃Can be output. However, here
The clock is the clock supplied to the arithmetic block 1.
CK ₁It is the cycle of.

The entire circuit is a circuit which receives the data A _{1 to} A ₉ and outputs the operation result OP ₃ .

Now, from the input terminals I _{1 to} I _{9 as} shown in FIG. 3, data A _{1 to} A ₉ , A ₁ ′ to A ₉ ′, A ₁ ″ to A _{1
When 9} ″ is input, the clock synchronized with this input is CK _2. However, it is assumed that the cycle of the clock CK ₂ is larger than 3 times the cycle of the clock CK ₀ (see FIG. 3).

In the clock control circuit 5, the clock CK ₂
Of the clock CK ₀ is output as the clock CK ₁ , and the remaining time is output as the clock CK _1.
It continues to output Low as ₁ (see FIG. 3). The 3-input selector 11 sequentially selects the I ₁ side, the I ₂ side, and the I ₃ side in a cycle synchronized with the clock CK ₁ . Similarly, the 3-input selectors 12 and 13 are also sequentially selected.

The outputs of the selectors 11, 12, and 13 are input to the input terminals 1 of the arithmetic blocks 1, 2, and 3 via two unit delay elements (register: R) synchronized with the clock CK ₁ .

Therefore, as shown in FIG. 3, the operation block 1
Receives the data A _{1 to} A _{3 in the 3rd} to 5th cycles, and
The result OP ₁ of the operation P ₁ is output in the cycle, the data A ₁ ′ to A ₃ ′ is received in the 6th to 8th cycles, the result OP ₁ ′ of the operation P ₁ is output in the 9th cycle, and the 9th to 11th cycles The data A ₁ ″ to A ₃ ″ are received in the eye and the result OP ₁ ″ of the operation P1 is output in the 12th cycle.

Operation block 1 at the 6th, 9th and 12th cycles
Data OP ₁ , OP ₁ ′, O output from the output terminals of
P ₁ ″ is transmitted through the wiring 10 and is input to the input terminal 2 of the arithmetic block 2. However, since the wiring 10 takes a propagation time, it is slightly delayed as shown in FIG.

However, since the sixth, ninth and twelfth cycles are longer than one cycle of the clock CK ₀ , the time (the period T in FIG. 3) less the propagation time in the wiring 10 is 1 of the clock CK ₀ . The operation block 2 is longer than the cycle time, and in the sixth, ninth, and twelfth cycles (to be exact, the latter half period T of the sixth, ninth, and twelfth cycles), the operation block 2 outputs the data OP ₁ , OP
_The operation P2 can be performed by receiving ₁ ′ and OP ₁ ″.

That is, the data OP ₁ is received from the input terminal 2 in the 6th cycle, and the data A _{4 to} A in the 6th to 8th cycles.
₆ is received, the result OP ₂ of the operation P ₂ is output in the 9th cycle, the data OP ₁ ′ is received from the input terminal 2 in the 9th cycle, and the data A ₄ ′ to A ₆ ′ is received in the 9th to 11th cycles. , The result OP ₂ ′ of the operation P ₂ is output in the 12th cycle, and the data OP ₁ ″ is input from the input terminal 2 in the 12th cycle.
Is received, and data A ₄ ″
A ₆ ″ is received, and the result of calculation P ₂ is OP in the 15th cycle
Output ₂ ″.

At the 9th, 12th, and 15th cycles, the data OP ₂ , OP ₂ ', outputted from the output terminal of the operation block 2 are
Similarly, for OP ₂ ″, there is a propagation time in the wiring 20, but since the ninth, the twelfth, and the fifteenth cycles are longer than the time of one cycle of the clock CK ₀ , the operation block 3 uses the data O.
The operation P3 can be performed by receiving P ₂ , OP ₂ ′ and OP ₂ ″.

Thus, according to the above-described device, in the clock for operating the inside of the LSI, the absolute time of one cycle in which data is transferred between the operation blocks is equal to the absolute time of one cycle in which data is not transferred between the operation blocks. By making the time longer than the absolute time, it is possible to perform the operation processing in the operation block at a high speed, that is, only the delay peculiar to the transistor during the time when the data is not passed between the operation blocks.

Although FIG. 3 shows that the clock CK ₀ and the clock CK ₂ are synchronized (5 cycles of CK ₀ = 1 cycle of CK ₂ ), they may not be synchronized.

[0026]

According to the present invention, in the clock for operating the inside of the LSI, the absolute time of one cycle in which data is transferred between operation blocks is equal to the absolute time of one cycle in which data is not transferred between operation blocks. By making the time longer than the absolute time, it has become possible to perform the arithmetic processing in the arithmetic block at a high speed such as only the delay peculiar to the transistor when the data is not passed between the arithmetic blocks. ..

[Brief description of drawings]

FIG. 1 is a configuration diagram of an example of a device to which a signal transmission method between arithmetic blocks according to the present invention is applied.

FIG. 2 is a diagram for explaining the explanation.

FIG. 3 is a diagram for explaining the explanation.

[Explanation of symbols]

 1-3 Operation block 4 Clock generation circuit 5 Clock control circuit 10, 20 Wiring 11, 12, 13 Selector R Unit delay element (register)

Claims (5)

[Claims] 1. Regarding a clock for operating the inside of an LSI, an absolute time of one cycle in which data is transferred between operation blocks on a layout is an absolute time of one cycle in which data is not transferred between the operation blocks. A signal transmission method between operation blocks, which is characterized in that it is longer than the time. 2. The clock generating means according to claim 1, wherein a clock generating circuit is provided inside, and the output of the clock generating circuit is generated by gating the output with a reference signal from the outside. Signal transmission method between arithmetic blocks. 3. A signal transmission method between arithmetic blocks, wherein a ring oscillator independent of an input data rate is used as the clock generation circuit in claim 2. 4. A signal transmission method between operation blocks, wherein a signal synchronized with input data is used as the external reference signal according to claim 2. 5. A signal transmission method between arithmetic blocks, wherein a signal synchronized with input data is used as the external reference signal according to claim 3.