JPH0536934U - Latch-up prevention circuit - Google Patents

Abstract

(57) [Abstract] [Purpose] To provide a latch-up prevention circuit capable of surely preventing latch-up with a simple configuration. The output buffer circuit 7 has a transistor 10 having an open collector structure, and its collector is connected to a second power supply 4 via a pull-up resistor 9. Therefore, when the transistor 10 is off, the CM
The input line of the OSIC2 is brought to a high state by the pull-up resistor 9, while the input line of the CMOSIC1 is brought to a low state when the transistor 10 is in a conducting state, so that the so-called floating state does not occur.
In addition, current does not flow from the pull-up resistor 9 into the CMOS IC1, and latch-up is surely prevented.

Description

[Detailed description of the device]

[0001]

[Industrial application]

 The present invention relates to a latch-up prevention circuit for preventing latch-up that occurs in a CMOS integrated circuit, and in particular, a circuit in which CMOS integrated circuits (hereinafter referred to as “CMOS IC”) connected to separate power supplies are cascaded. The present invention relates to a latch-up prevention circuit for preventing a latch-up that occurs in a computer.

[0002]

[Prior art]

 A CMOS IC, which is known as a typical CMOS device, has a very low power consumption because a current does not flow in a steady state of a logic circuit and a current flows transiently only when a logic state changes. It is a feature. However, it is known that in such a CMOS IC, a phenomenon called latch-up occurs in which a current flows from the power supply line to the ground triggered by noise current or noise voltage. For example, when a circuit configuration is adopted in which CMOSICs connected to independent power sources that are independent of each other are cascaded, latch-up is particularly likely to occur, so such a circuit configuration should be used in principle. However, such a circuit configuration may be unavoidable depending on the conditions such as circuit elements. FIG. 2 shows a schematic configuration in the case where CMOS ICs connected to independent power sources in this way are cascade-connected, and the latch-up in this case will be described below with reference to the same figure. .. In this circuit example, the output of the CMOSIC1 is connected to the input of the CMOSIC2, and the CMOSIC1 and the CMOSIC2 are cascade-connected. A power supply voltage is applied to the CMOSIC 1 from the first power supply 3, and a power supply voltage is applied to the CMOSIC 2 from the second power supply 4. The first power source 3 and the second power source 4 are electrically separate and independent, and each can be turned on and off independently. In addition, the usage state of the entire circuit may be such that the first power source 3 is turned off (non-operating state) while the second power source 4 is turned on (operating state).

In such a circuit configuration, if only the first power supply 3 is turned off while both the first power supply 3 and the second power supply 4 are turned on as in the above-described precondition, The input of the CMOSIC2 is in a so-called floating state in which the electric potential is not fixed and is in a state where it is susceptible to external noise. On the other hand, during the moment when the first power supply 3 is turned off, pulse-like noise is generated due to the transient phenomenon generated inside the first power supply 3, and this noise is applied to the floating input line of the CMOS IC2. Input. Then, such pulse noise triggers a latch-up in which a current continues to flow from the second power source 4 to the ground side through the CMOSIC2, and eventually the CMOSIC2 is damaged by burning or the like. There is. Therefore, as a general rule, the circuit should not be configured by using CMO SICs that are driven by different power sources as shown in FIG. 2, but in order to satisfy the required circuit characteristics, etc. In some cases, there is no choice but to adopt a different configuration. In such a case, as one technique for preventing latch-up, for example, taking the circuit shown in FIG. 2 as an example, the output side of the CMOSI1 is forcibly grounded when the first power supply 3 is turned off. In this state, the input line of CMOSIC2 connected to this output is set to the ground potential, and the control circuit that prevents the above-mentioned floating state from occurring is provided to prevent latch-up. It is possible to do it.

As another technique, for example, in FIG. 2, the output line of the CMOS IC 1, that is, the input line of the CMOS IC 2 is connected to the second power supply 4 via a so-called pull-up resistor 5 as shown by a dotted line. However, there is a so-called pull-up technique that prevents the input line of the CMOSIC2 from entering the floating state.

[0005]

[Problems to be solved by the device]

 However, when the control circuit is provided as in the former case, there is a problem that the circuit becomes complicated and becomes expensive as a whole. In the latter case of pull-up, the current from the second power supply 4 flows in through the pull-up resistor 5 and the protection diode 6 built in the CMOS IC 1, and the potential of the first power supply 3 itself. However, when the first power supply 3 is operated, normal output voltage and current cannot be obtained.

The present invention has been made in view of the above circumstances, and it is an object of the present invention to provide a latch-up prevention circuit that can reliably prevent latch-up with a simple structure.

[0007]

[Means for Solving the Problems]

 In order to solve the above problems, a latch-up prevention circuit according to the present invention is a latch-up prevention circuit for a CMOS integrated circuit which has a separate power supply and is connected in cascade, wherein the two CMOS integration circuits are connected in cascade. A buffer circuit whose output stage has an open collector structure is provided between the circuits, and the collector of the output stage of the buffer circuit is connected to the power supply line of the CMOS integrated circuit of the next stage via a pull-up resistor. is there.

[0008]

[Action]

 Among the CMOS integrated circuits connected to the respective separate power sources and cascaded via the buffer circuit, the power source of the CMOS integrated circuit of the previous stage is turned off and the power source of the CMOS integrated circuit of the next stage is turned on. In this case, the collector of the transistor, which is the final stage of the buffer circuit, is maintained at the power supply voltage for the CMOSIC of the next stage via the pull-up resistor, but the collector of this transistor is inside the buffer circuit or the CMOS integrated circuit of the previous stage. Since it is an open collector that is not connected to any of the inside, the collector current of this transistor does not flow unless the base current flows, and even if the collector current flows, this collector current is It will flow into the ground side through the emitter that is normally grounded, and will flow into the power supply for the CMOS IC in the previous stage as in the past. Such that there is no.

[0009]

【Example】

 An embodiment of the latch-up prevention circuit according to the present invention will be described with reference to the circuit diagram of FIG. The latch-up prevention circuit according to the present embodiment includes an output buffer circuit 7 provided between CMOSIC1 and CMOSIC2, an input buffer circuit 8 provided between the output buffer circuit 7 and the CMOSIC2, and the output buffer described above. And a pull-up resistor 9 for pulling up the output of the circuit 7. To describe the overall circuit configuration, first, the CMOS ICs 1 and 2 themselves are publicly known and well known, and therefore detailed description thereof will be omitted. Further, the circuit constituted by the CMOSICs 1 and 2 is not limited to a specific application, but in this embodiment, it is assumed to be a logic circuit. It should be noted that the CMOS ICs 1 and 2 are not specified in any kind of logic circuit because they do not interfere with the operation of the latch-up prevention circuit.

The power supply line of the CMOSIC 1 is connected to the first power supply 3, and the power is supplied from the first power supply 3. The output is also input to the output buffer circuit 7. The output buffer circuit 7 is a buffer circuit for reducing the electrical influence between the CMOS ICs 1 and 2, and the final stage thereof has an open collector transistor 10. The collector of the transistor 10 is connected to the input line of the input buffer circuit 8 and also connected to the second power supply 4 via the pull-up resistor 9, and the predetermined voltage is supplied from the second power supply 4. Is applied. The input buffer circuit 8 is basically the same as the above-described output buffer circuit 7 in that it is a buffer circuit, but the output buffer circuit 8 is that it is not an open collector transistor at the final stage. Different from circuit 7. Further, the input buffer circuit 8 is preferably composed of a bipolar element having a large latch-up resistance. The output of the input buffer circuit 8 is connected to the input line of the CMOSIC2. The input buffer circuit 8 is supplied with a power supply voltage from the second power supply 4.

The CMOSIC 2 is in a cascade connection with the CMOSIC 1 through the output buffer circuit 7 and the input buffer circuit 8 described above, and the power source thereof is supplied from the second power source 4. .. Next, the circuit operation in the above configuration will be described below. First, when both the first power supply 3 and the second power supply 4 are in the operating state, the CMOSIC 1 outputs a signal according to an input signal from the preceding stage (not shown), and the transistor 10 of the output buffer circuit 7 receives the input from the CMOSIC 1. It will operate according to the signal. That is, when an input signal such that a base current flows into the base of the transistor 10 is input to the output buffer circuit 7, a collector current flows into the collector of the transistor 10 via the pull-up resistor 9. , The transistor 10 becomes conductive, and the potential of the collector becomes the ground potential (so-called "Low" state). Therefore, both the input and output of the input buffer circuit 8 are in the Low state, the input line of the CMOSIC2 is also in the Low state, and the output of the CMOSIC2 is in the Low state or the High state (the output is a constant positive voltage state) according to the Low input. . On the other hand, when a signal for turning off the transistor 10 of the output buffer circuit 7 is input from the CMOSIC 1 to the output buffer circuit 7, the transistor 10 is in the non-conducting state, so that its collector and the input buffer circuit are turned on. Both input lines 8 are held at the power supply voltage of the second power supply 4 (High state). Therefore, the output of the input buffer circuit 8 is also in the High state and is input to the CMOSIC 2. The CMOSIC2 will output a Low or High signal in response to this High input. Thus, when the first and second power supplies 3 and 4 operate together and the entire circuit is in the operating state, the output buffer circuit 7, the input buffer circuit 8, and the pull-up resistor 9 are The circuit operates normally without any hindrance.

Next, when only the first power supply 3 is in a non-operating state, that is, when the first and second power supplies 3 and 4 are both operating, the CMOSIC 1 is in a non-operating state. The current does not flow into the base of the transistor 10 of the output buffer circuit 7. Therefore, even if the collector of the transistor 10 is held at the power supply voltage of the second power supply 4 via the pull-up resistor 9, the transistor 10 becomes non-conductive and current flows into the output buffer circuit 7 and the first power supply 3. There is no. On the other hand, since the transistor of the output buffer circuit 7 becomes non-conductive, the input line of the input buffer circuit 8 is maintained at the power supply voltage of the second power supply 4 via the pull-up resistor 9. The output is in the High state, and this High signal is input to the CMOSIC2. Since the input buffer circuit 8 has a large latch-up resistance, the latch-up in the CMOS IC 2 is made difficult to occur.

Contrary to the above, when the first power supply 3 is in the operating state and the second power supply 4 is in the non-operating state, the collector of the transistor 10 is at zero potential, The transistor 10 is in a non-conducting state regardless of the input state of the base. Therefore, since the input of the input buffer circuit 8 has a zero potential, no excessive voltage is applied to the CMOSIC 2, and the occurrence of latch-up becomes extremely small. Further, even in the transition process from the operating state to the non-operating state or from the non-operating state to the operating state of the second power supply 4, the transistor 10 of the output buffer circuit 7 is in the non-conducting state or the conducting state. However, the excessive voltage will not be applied to the CMOS IC2.

The latch-up prevention circuit of this embodiment cascades two CMOS ICs 1 and 2 connected to separate power sources through an output buffer circuit 7 having an open collector structure at the final stage. , The collector of the transistor 10 of the output buffer circuit 7 is connected to the second power supply 4 for the CMOSIC 2 at the next stage connected to the output side of the output buffer circuit 7, and a so-called pull-up structure is adopted, whereby the output buffer When the transistor 10 of the output circuit 7 is turned off, the input line of the CMOSIC 2 is set to the high state, and when the transistor 10 of the output buffer circuit 7 is turned on, the input line of the CMOSIC 2 is turned on. Is in the Low state, and in any case it will not be in the so-called floating state. The situation is prevented.

Although the input buffer circuit 8 is provided in the present embodiment, it is not always necessary, and at least the output buffer circuit 7 and the pull-up resistor for pulling up the final stage of the open collector are provided. Any device that includes the container 9 may be used. Moreover, the output buffer circuit 7 does not necessarily have to be composed of a plurality of stages of transistors, and may be a single open collector transistor.

[0016]

[Effect of the device]

 According to the present invention, a buffer circuit having an open collector structure at the final stage is provided between two CMOS integrated circuits which are supplied with power from separate power sources and are connected in cascade, and a CMOS integrated circuit is provided through this buffer circuit. By connecting the circuits in cascade and connecting the collector at the final stage of the buffer circuit to the power supply of the CMOS integrated circuit connected to the output side of this buffer circuit via a pull-up resistor. , The current flowing from the power supply through the pull-up resistor only flows into the final stage transistor of the buffer circuit, it does not flow into the CMOS integrated circuit as in the past, and unnecessary current that causes latch-up. Since it does not flow into the CMOS integrated circuit, it is possible to reliably prevent latch-up with a simple configuration without requiring a complicated control circuit. It is kill things.

[Brief description of drawings]

FIG. 1 is a circuit diagram of an embodiment of a latch-up prevention circuit according to the present invention.

FIG. 2 is a circuit diagram for explaining latch-up in a conventional CMOS integrated circuit.

[Explanation of symbols]

1, 2 ... CMOSIC, 3 ... 1st power supply, 4 ... 2nd power supply, 7 ... Output buffer circuit, 8 ... Input buffer circuit, 9 ... Pull-up resistor, 10 ... Transistor

 ─────────────────────────────────────────────────── ─── Continuation of the front page (72) Creator Toshiyuki Eda 2-3-3 Toranomon, Minato-ku, Tokyo Kokusai Electric Co., Ltd.

Claims (1)

[Scope of utility model registration request] 1. A CM that has a separate power supply and is cascaded.
A latch-up prevention circuit for an OS integrated circuit, wherein a buffer circuit having an open collector structure at an output stage is provided between the two CMOS integrated circuits connected in cascade, and a collector of the output stage of the buffer circuit is pulled up. A latch-up prevention circuit characterized by being connected to a power supply line of a CMOS integrated circuit in the next stage through a resistor.