JPH0536929U - Digital Attenuator - Google Patents

Abstract

(57) [Summary] [Purpose] An object of the present invention is to provide a digital attenuator that does not generate noise when a sudden change occurs in the gain setting of the attenuator or during muting. [Structure] Register 1 that holds the set value, register output LL
Comparator 3 that compares A and counter output LLP, has a counter 2 that stops counting when LLA = LLP, and counts down when LLA <LLP, and multiplier 5 digitally uses counter value LLP as a multiplier. The input signal DIN is multiplied to obtain the digital output signal DOUT.

Description

[Detailed description of the device]

[0001]

[Industrial application]

 The present invention relates to a digital attenuator used in a digital audio reproducing apparatus such as a CD player, DAT (digital audio disc recorder), CD-I (interactive CD) or the like.

[0002]

[Prior art]

 BACKGROUND ART In a digital muting circuit, a technique of using a digital attenuator to gradually attenuate a digital signal when muting is turned on and to gradually amplify the digital signal when muting is turned off is disclosed in, for example, Japanese Patent Application Laid-Open Those described in JP-A-6-155381 are known. Here, the digital attenuator means a digital output signal of a desired level obtained by setting predetermined data in the output level coefficient register and multiplying the digital input signal by the predetermined data. Is.

FIG. 2 is a diagram showing a conventional digital muting circuit. As shown in the figure, this type of digital muting circuit is composed of an attenuator circuit 104 including a time constant timer 101, an output level coefficient register 102 and a multiplier 103. When the mute-on signal is input, the time constant timer 101 counts down, the timer value is held in the output level coefficient register 102, and the register value and the digital input signal DIN are multiplied by the multiplier 103. Therefore, the analog output signal AN which is D / A converted in the DAC (D / A converter) 105 and output is as shown in FIG. When the mute-off signal is input, the time constant timer 101 counts up, and the output level gradually increases.

As described above, in the digital muting circuit, the multiplier is gradually changed when the mute is turned on / off by the action of the time constant timer 101, so that the gain of the attenuator circuit does not abruptly change and the noise is reduced. Does not occur.

[0005]

[Problems to be solved by the device]

 However, since the above-mentioned conventional digital attenuator multiplies the digital input signal by the target level data to obtain the output signal of a desired level, when a sudden change occurs in the gain of the attenuator. Noise is generated. Therefore, there is a demand for a digital attenuator that does not cause a sudden change in gain and does not generate noise like the digital muting circuit described above, but such a digital attenuator has not existed in the past.

The present invention has been made in view of the above-mentioned problems, and an object thereof is to provide a digital attenuator that does not cause a sudden change in gain and does not generate noise.

[0007]

[Means for Solving the Problems]

 In order to solve the above-mentioned problems, the present invention provides a digital attenuator that obtains a desired level of digital output signal by multiplying a digital input signal consisting of a sequence of digital data by a multiplier. Data holding means for holding data, counting means for gradually increasing or decreasing the current multiplier to increase or decrease the current multiplier, and target level data held by the data holding means and increasing or decreasing by the counting means. And comparing the reduced multipliers, and when the target level data and the multiplier have the same value, the counting of the counting means is stopped based on the result of the comparing means.

[0008]

[Action]

 According to the present invention, the digital attenuator is constructed as described above, the target level is held in the data holding means, and the counting means is stepped or reverses until the target level is reached. Then, since the digital input signal is multiplied by using the output of the counting means as a multiplier, noise does not occur even when there is a sudden change in the gain setting.

Further, the function of the muting circuit can be achieved by setting the "0" level in the data holding means.

[0010]

【Example】

 Embodiments of the present invention will be described below with reference to the drawings. FIG. 1 is a block diagram showing the configuration of a digital attenuator according to the present invention. In the figure, 1 is a register for holding a set value, 2 is a counter, 3 is a comparator, 4 is a flip-flop, 5 is a multiplier, 6 is an inverter circuit, and 7 is a DAC (D / A converter). Is.

First, the register 1 will be described. The register 1 latches a set value from a control circuit (not shown). A latch clock BCLK, an enable signal EN, an initial (initialization) signal INIT and a reset signal RST are applied to the register 1, and the enable signal EN is at "L" level as shown in FIG. 4 (a). At the rising edge of the latch clock BC LK, the predetermined set value data LRPD0 to 7 corresponding to the target gain are latched. The target gain and the set value data have a relationship as shown in FIG. Here, a gain value of 0 dB means that the output level of the input signal is output, and a gain value of -∞ dB means that the output signal level is 0. Further, the output data L LA0 to 7 of the register 1 can be set by inputting the initial signal INIT and the reset signal RST as shown in FIG. 4 (c).

Next, the counter 2 and the comparator 3 will be described. These are for comparing the multiplier and the counter value and up or down the counter 2 to a set level. The register outputs LLA0 to 7, initial signal INIT, counter clock SYSCLK, mode switching signal MODE, count enable signal ENLL, up-down switching signal U / D and reset signal RST are input to the counter 2. The register outputs LLA0 to 7 and counter outputs LLP0 to 7 are input to the comparator 3. When (register output) = (counter output), LLEQ is set to (register output) <(counter output). In this case, ZL LUP becomes "H".

The counter 2 can be initialized by inputting it as shown in FIG. 4C like the register 1 by the initial signal INIT and the reset signal RST. When the count enable signal ENLL is "L", it counts up or down at the rising edge of the counter clock SYSCLK. When "L" is input to the up / down switching signal U / D, the counter 2 counts up, that is, advances, and when "H" is input, the counter 2 counts down, that is, reverses. The flip-flop 4 latches LLEQ and outputs it to the counter 2 when the output of the inverter circuit 6 rises, that is, when SYSCLK falls.

Further, the counter 2 of this embodiment is capable of mode switching described below. (1) When "H" is input to mode, the LLA set in the register 1 can be directly loaded and the multiplier of the multiplier 5 can be set directly. That is, it operates like a conventional attenuator. In such a case, the output LLA of the register 1 is loaded from the INA of the counter 2 and output to the multiplier 5 as LLP. Further, since LLA = LLP in the comparator 3, LLEQ becomes "H" and the counter 2 stops counting.

(2) When “L” is input to mode, the counter 2 is caused to count, so that the multiplier of the multiplier 5 is changed stepwise until the value set in the register 1 is reached. To do. Therefore, in this mode, it is possible to prevent a sudden change in gain due to a change in multiplier. In such a case, the value LRPD to be set is set in the register 1 and the register 1 is latched by the BLCK signal and the EN signal. The output LLA of register 1 is compared with the counter output LLP to determine whether the counter is up or down. That is, when A <B, ZLLUP becomes "H" and the counter 2 counts down. When A ≧ B, ZLLUP becomes “L” and the counter 2 counts up. The counter 2 counts up or down based on ZLLUP at every rising edge of SYSCLK, and when the counter value becomes equal to the register value LLA, LLEQ becomes "H". LLEQ is latched by the flip-flop 4 at the falling edge of SYSCLK, outputs the ENLL signal to the counter 2, and the counter 2 stops counting.

For example, when the target gain is set to −∞ (mute on) and the target gain is set to a predetermined value (corresponding setting value is “X (H)”) after the muting is completed, As shown in FIG. 5, the counter value of the counter 2 changes.

The case of the mode (2) will be further described below. FIG. 6A is a diagram showing the timing when the mute is on. First, "00 (H)" is input to LRPD, EN is "L" and latched in register 1 at the rising edge of BCLK, and LLA becomes "00 (H)". If the current counter value LLP is "80 (H)", LLA and LLP are compared in the comparator 3 and ZLLUP becomes "H", so the counter 2 becomes a subtraction counter. Also, because LLA ≠ LLP, LLEQ goes to "L" level, flip-flop 4 latches LLEQ at the falling edge of SYSCLK, ENLL goes to "L", and counter 2 is ready to count (count enable). Bull). Then, every time SYSCLK rises, the counter value changes to "7F (H)", "7E (H)", "7D (H)", ... (Count down). Therefore, the input signals DIN and LLP are multiplied in the multiplier 5, and the output signal DOUT is obtained. The analog output signal AN obtained by D / A converting DOUT by the DAC 7 is sequentially attenuated as shown in FIG.

When the counter value LLP becomes “00 (H)”, LLEQ becomes “H”. Then, at the falling edge of SYSCLK, ENLL becomes "H", the counter 2 becomes uncountable (count disable), and stops counting (count hold). Since LLP is "00 (H)" at this point, the output level of the analog output signal AN also becomes zero and the muting is completed.

FIG. 7A is a diagram showing the timing when the mute is off. In this case, contrary to the case of muting, "80 (H)" is set in the register 1 and LLA becomes "80 (H)". Since LLA and LLP are compared in the comparator 3 and ZLLUP becomes "L", the counter 2 becomes an addition counter. Also, because LLA ≠ LLP, LLEQ becomes "L" level, flip-flop 4 latches LLEQ at the falling edge of SYSCLK, ENLL becomes "L", and counter 2 is in a countable state (count enable). ). Thereafter, the counter value changes to "01 (H)" and "02 (H)" at each rising edge of SYSCLK. Therefore, the analog signal output AN gradually increases as shown in FIG.

The case where the counter value LLP becomes “80 (H)” is the same as when muting is on, and the counter 2 stops counting.

In the present embodiment, a control circuit (not shown) converts the target gain into a set value in advance and holds the set value data LRPD in the register 1. The conversion circuit between the target gain and the set value By providing, it becomes possible to set the target gain directly from the control circuit. In such a case, as shown in FIG. 8, the MSB bit is set as the enable bit of the gain value, and when the MSB is "0", it is converted to the set value corresponding to the lower 7 bits, and when the MSB is "1". Sets the gain to "-∞", that is, the set value to "00 (H)".

[0022]

[Effect of the device]

 As described in detail above, according to the present invention, the following excellent effects can be obtained. (1) Holds the set value in the register, counts up or down the counter until the set value is reached, and multiplies the digital input signal by using the output of the counter as a multiplier. No noise is generated even when

(2) Since the comparator compares the register value with the counter value, the multiplier can be set to an arbitrary level.

(3) By setting "00 (H)" or "80 (H)" in the data holding means, the function of the muting circuit can be fulfilled.

(4) Since the data held in the register can be directly used as a multiplier, it can function as a conventional attenuator.

[Brief description of drawings]

FIG. 1 is a block diagram showing a configuration of a digital attenuator according to the present invention.

FIG. 2 is a diagram showing a conventional digital muting circuit.

FIG. 3 is a diagram showing an analog output signal by a conventional digital muting circuit.

4A and 4B are diagrams illustrating a register 1, where FIG. 4A is a diagram showing a latch timing and FIG. 4B is a diagram showing a relationship between a gain and a set value. FIG. 3C is a diagram for explaining the data setting of the register 1.

FIG. 5 is a diagram showing changes in the counter value of the counter 2.

FIG. 6 is a diagram showing timing and analog output signals when muting is turned on.

FIG. 7 is a diagram showing timing and analog output signals when muting is off.

FIG. 8 is a diagram showing an example of conversion between a target gain and a set value.

[Explanation of symbols]

 1 Register 2 Counter 3 Comparator 4 Flip Flop 5 Multiplier 6 Inverter Circuit 7 DAC (D / A Converter)

 ─────────────────────────────────────────────────── ─── Continuation of the front page (72) Katsushi Koyama 2-14-9 Tamagawadai, Setagaya-ku, Tokyo Kyocera Corporation, Tokyo Yoga Works (72) Hiroyuki Tsuda, Keihanhondori 2-chome, Moriguchi City, Osaka Prefecture Address Sanyo Electric Co., Ltd. (72) Creator Tomofumi Watanabe 2-18 Keihan Hondori, Moriguchi City, Osaka Sanyo Electric Co., Ltd.

Claims (1)

[Scope of utility model registration request] 1. A digital attenuator for obtaining a digital output signal of a desired level by multiplying a digital input signal consisting of a digital data sequence by a multiplier, and a data holding a set target level data. Data holding means, counting means for increasing or decreasing the current multiplier to gradually change the multiplier, target level data held in the data holding means, and multipliers increased or decreased by the counting means. A digital attenuator comprising: a comparing means for comparing, wherein when the target level data and the multiplier have an equal value, the counting of the counting means is stopped based on the result of the comparing means.