JPH0536914A - Insulated gate type field effect transistor and semiconductor device using the same - Google Patents

Abstract

PURPOSE:To provide a semiconductor device which can operate at a high speed, has no latchup, etc., and excellent radiation resistant characteristic by manufacturing an insulated gate type field effect transistor in which stray capacitances of a source and a drain are reduced. CONSTITUTION:A single crystalline layer for constituting at least a channel region of an insulated gate type field effect transistor is formed of nonporous single crystalline layers 4, 5 on a light transmission insulator base 1 obtained by oxidizing a silicon base made porous from a nonporous single crystalline layer on the silicon base made porous.

Description

Detailed Description of the Invention

[0001]

BACKGROUND OF THE INVENTION 1. Field of the Invention The present invention relates to an insulated gate field effect transistor and a semiconductor device using the same, and particularly to an insulated gate field effect transistor in which an insulated gate field effect transistor is formed on a light transmissive insulator substrate. The present invention relates to an effect transistor and a semiconductor device using the same.

[0002]

2. Description of the Related Art The formation of a single crystal Si semiconductor layer on an insulator is widely known as a silicon-on-insulator (SOI) technique, and is unattainable in a bulk Si substrate for producing an ordinary Si integrated circuit. Much research has been done because the device utilizing the SOI technology has an advantage. In other words, by using SOI technology,
． Dielectric isolation is easy and high integration is possible. Excellent radiation resistance ,. Stray capacitance is reduced and speedup is possible. The well process can be omitted. Latch-up can be prevented. Advantages such as a fully depleted field effect transistor can be obtained by thinning the film.

In order to realize the many advantages in device characteristics as described above, a method for forming an SOI structure has been researched for several decades. This content can be found in, for example, Special Issue: "Single-crystal silicon on no
n-single-crystal insulators "; edited by GWCulle
n, Journal of Crystal Growth, volume 63, no 3, pp4
29-590 (1983).

Further, SOS (silicon on sapphire), which is formed by heteroepitaxy Si on a single crystal sapphire substrate by CVD (chemical vapor deposition) method, has been known for a long time and is the most mature. Although it was successful as an SOI technology, a large amount of crystal defects due to the lattice mismatch between the Si layer and the underlying sapphire substrate interface, mixing of aluminum from the sapphire substrate into the Si layer, and above all, the high cost of the substrate The delay in increasing the area prevents the spread of its application. In recent years, attempts have been made to realize an SOI structure without using a sapphire substrate. This attempt is roughly divided into the following two. (1) After the surface of the Si single crystal substrate is oxidized, a window is opened and Si is
The substrate is partially exposed and laterally epitaxially grown using the portion as a seed to form a Si single crystal layer on SiO ₂ (in this case, Si layer is deposited on SiO ₂ ). (2) Using the Si single crystal substrate itself as the active layer,
SiO ₂ is formed thereunder (this method does not involve deposition of a Si layer).

Various semiconductor devices and integrated circuits made of them have been formed on a silicon layer on an insulator formed by these methods.

[0006]

As means for realizing the above (1), a single crystal layer Si is directly formed by a CVD method.
Lateral epitaxial growth, amorphous Si deposition, and solid phase lateral epitaxial growth by heat treatment, electron beam on the amorphous or polycrystalline Si layer,
A method of converging and irradiating an energy beam such as a laser beam to grow a single crystal layer on SiO ₂ by melting and recrystallization, and a method of scanning a melting region in a band shape with a rod heater (Zone melting recrystallization) are known. ing. Each of these methods has advantages and disadvantages,
There are still many problems in its controllability, productivity, uniformity, and quality, and none has been industrially put to practical use. For example, the CVD method requires sacrificial oxidation to achieve a flat thin film, and the solid phase growth method has poor crystallinity. Further, the beam annealing method has problems in processing time by convergent beam scanning, controllability such as beam overlapping and focus adjustment. Of these, the Zone Melting Recrystallization method is the most mature, and relatively large-scale integrated circuits have been prototyped, but crystal defects such as sub-grain boundaries still occur.
Majority remains and has not led to the creation of minority carrier devices. Moreover, since neither method requires a Si substrate, a good quality Si single crystal layer cannot be obtained on a transparent amorphous insulator substrate such as glass.

In the method of (2) above, in which the Si substrate is not used as seeds for epitaxial growth, there are the following four types of methods.

[0008] An oxide film is formed on a Si single crystal substrate in which V-shaped grooves are anisotropically etched on the surface, a polycrystalline Si layer is deposited on the oxide film to be as thick as the Si substrate, and then polished from the back surface of the Si substrate. Is a method for forming a Si single crystal region surrounded by V-grooves and dielectrically isolated on a thick polycrystalline Si layer. In this method, the crystallinity is good, but the step of depositing polycrystalline Si to a thickness of several hundreds of microns, and
This requires a step of polishing the single crystal Si substrate from the back surface to leave only the separated Si active layer, which is problematic in terms of controllability and productivity.

[0009]. SIMOX: Seperati
This is a method of forming a SiO ₂ layer by ion implantation of oxygen in a Si single crystal substrate called “on by ion implanted oxygen”, which is the most mature method at present because it has good compatibility with the Si process. However, in order to form the SiO ₂ layer, oxygen ions are added at 10 ¹⁸ ions / cm ^2.
It is necessary to implant the above, the implantation time is long, the productivity cannot be said to be high, and the wafer cost is high. Further, many crystal defects remain, and from an industrial point of view, the quality is not sufficient to produce a minority carrier device.

[0010]. Another S obtained by thermally oxidizing a Si single crystal substrate
It is a method of forming an SOI structure by bonding to an i single crystal substrate or a quartz substrate using heat treatment or an adhesive. This method requires a uniform thinning of the active layer for the device. That is, it is necessary to polish a Si single crystal substrate having a thickness of several hundreds of microns to the micron order or less. Therefore, in this method, there are many problems in productivity, controllability, and uniformity. Further, the cost is high because two substrates are required.

[0011]. This is a method of forming an SOI structure by dielectric isolation by oxidation of porous Si. This method is
Ion implantation of N-type Si layer on the surface of type Si single crystal substrate (Imai et al., J. Crystal Growth, vol 63, 547 (1983)),
Alternatively, it is formed into an island shape by epitaxial growth and patterning, and only the P-type Si substrate is made porous by an anodization method in a HF solution so as to surround the Si island from the surface, and then the N-type Si island is increased by accelerated oxidation. It is a method of dielectric separation. This method has a problem that the separated Si region is determined before the device process, which may limit the degree of freedom in device design.

By the way, forming a semiconductor element on a light-transmissive substrate is important in constructing a contact sensor which is a light-receiving element and a projection type liquid crystal image display device. Furthermore, to further increase the density, resolution, and definition of pixels (pixels) of sensors and display devices,
High-performance drive elements are required. In addition, the number of terminals of the switching element for switching the pixel and its drive circuit and peripheral circuit becomes enormous, and the connection between them after making them separately becomes a density that is no longer possible by mechanical connection. As a result, it is desirable that the semiconductor device and the peripheral drive circuit are formed in the same substrate by the same process, and the mutual connection is performed in a normal integrated circuit. Moreover, it should be formed by patterning a conductive thin film, and only then can high-density mounting be possible. Further, from the inevitable industrial demand for higher performance of products to be produced, it is necessary to produce a device provided on a light transmissive substrate by using a single crystal layer having excellent crystallinity.

However, on a light-transmissive substrate typified by glass, in general, only a polycrystalline layer is formed, which is amorphous or good, reflecting the disorder of the crystal structure, and the defect Due to the large number of crystal structures, it has been difficult to fabricate a driving element having sufficient performance required or required in the future. This is due to the fact that the crystal structure of the substrate is amorphous, and simply depositing a Si layer will not yield a good-quality single crystal layer. When a semiconductor element or the like is formed on a light transmissive substrate, any of the above methods using a Si single crystal substrate is unsuitable for the purpose of obtaining a good quality single crystal layer on the light transmissive substrate. Is.

The present invention is a field effect transistor which is a basic unit of an integrated circuit which can be formed on a high quality single crystal semiconductor layer on a light transmissive insulator substrate which can meet the above problems and the above requirements. , And an integrated circuit comprising them.

A further object of the present invention is to provide a semiconductor integrated circuit which realizes the advantages of the conventional SOI structure. Further, the present invention provides a semiconductor element and an integrated circuit on a semiconductor-on-insulator substrate, which can replace expensive SOS and SIMOX even when manufacturing a large-scale integrated circuit having an SOI structure and have higher quality. The purpose is to do.

[0016]

According to another aspect of the present invention, there is provided an insulated gate field effect transistor comprising a non-porous silicon substrate on which a single crystal layer constituting at least a channel region of the insulated gate field effect transistor is made porous. The porous single crystal layer is characterized by being the non-porous single crystal layer on the light transmissive insulator substrate obtained by oxidizing the porous silicon substrate.

The semiconductor device of the present invention uses the above-mentioned insulated gate field effect transistor.

[0018]

[Operation] Generally, the thermal oxidation rate of Si single crystal is about 1 hour / hour.
About micron (1200 ℃, wet oxidation, under atmospheric pressure)
Therefore, it takes hundreds of hours to oxidize the entire Si wafer having a thickness of hundreds of microns while leaving the surface layer. Moreover, it is known that when Si is oxidized to SiO ₂ , the volume expansion of 2.2 times is accompanied, and when the Si substrate is oxidized as it is, a stress exceeding the elastic limit is applied to the surface residual Si layer, There are problems that the Si layer is cracked or warped.

Here, since the porous layer has a large amount of voids formed therein, the density thereof is reduced to less than half.
As a result, the surface area is drastically increased as compared with the volume, so that the oxidation rate is increased 100 times or more as compared with the oxidation rate of a normal single crystal layer. Further, by controlling the density of the porous Si, it is possible to suppress the volume expansion thereof.

Further, the density of the porous silicon is the single crystal S
Compared with i, the single crystallinity is maintained even though it is less than half, and it is possible to epitaxially grow the single crystal Si layer on the upper part of the porous layer.

The present invention utilizes such properties of porous silicon to form a single crystal semiconductor layer on a light transmissive insulator substrate, and an insulated gate field effect transistor is formed on this single crystal semiconductor layer. To do. That is, according to the present invention, after forming a non-porous single crystal layer having excellent crystallinity on a porous silicon substrate, the oxidation rate is increased as compared with a normal single crystal layer. By oxidizing the modified silicon substrate, a single crystal semiconductor layer is formed on the light transmissive insulator substrate (oxidized porous silicon substrate),
An insulated gate field effect transistor was produced on this single crystal semiconductor layer.

In the present invention, on a Si single crystal layer formed on a light-transmissive substrate, which is economical, is even and flat over a large area, has extremely excellent crystallinity, and has extremely few defects. Since an element is formed in the semiconductor device, an insulated gate field effect transistor with reduced stray capacitance of the source and drain can be manufactured, high-speed operation is possible, a semiconductor device excellent in radiation resistance characteristics without latch-up phenomenon, etc. Can be provided.

[0023]

Embodiments Embodiments of the present invention will be described in detail below with reference to the drawings.

FIG. 1 is a schematic sectional view of an embodiment of a semiconductor device according to the present invention. In the figure, the substrate 1 is a light-transmitting substrate made of SiO ₂ formed by oxidizing porous Si as described later.

An N-channel field effect transistor 2 and a P-channel field effect transistor 3 are formed on the substrate 1, and a complementary field effect semiconductor device is manufactured by connecting both elements to each other.

The steps of manufacturing the transistors 2 and 3 will be described below with reference to FIG. 2 from the step of manufacturing the single crystal semiconductor layer on the light transmissive substrate.

2 (a) to 2 (c) are process drawings for explaining a method for manufacturing a semiconductor substrate according to the present invention, each of which is shown as a schematic sectional view in each process.

First, as shown in FIG. 2A, a P-type S
The surface of the i single crystal substrate 21 is ion-implanted with protons to obtain N
The mold single crystal layer 22 is formed. Alternatively, the intrinsic or low-concentration N-type layer 22 is formed by epitaxial growth by a vapor phase method.

Next, as shown in FIG. 2B, P-type Si
The single crystal substrate 21 is transformed into a porous Si substrate 23 from the back surface by an anodization method using an HF solution. This porous Si layer has a density of 1.1 to 0.6 g / cm ³ by changing the density of the single crystal Si from 2.33 g / cm ³ to an HF solution concentration of 50 to 20%. It can be changed into a range. This porous layer is difficult to be formed on the intrinsic or low-concentration N-type Si layer due to the following reasons.
It is easily formed only on the P-type Si substrate. According to observation with a transmission electron microscope, holes having an average diameter of about 10 angstroms are formed in this porous Si layer. Although its density is less than half that of single crystal Si,
The single crystal is maintained, and the single crystal S is added to the upper part of the porous layer.
It is also possible to epitaxially grow the i layer. However, at 1000 ° C. or higher, rearrangement of internal pores occurs, and the property of accelerated oxidation described later is lost.

Porous Si is described in 1956 by Uhlir et al.
It was discovered in the research process of electropolishing of semiconductors in 2010 (A.
Uhlir, Bell Syst.Tech.J., vol 35, p.333 (1956)). Also, Unagami et al. Studied the dissolution reaction of Si in anodization and reported that the anodic reaction of Si in HF solution requires holes, and the reaction is as follows (T .
Unagami: J. Electrochem. Soc., Vol.127, p.476 (198
0)).

Si + 2HF + (2-n) e ⁺ → SiF ₂ + 2H ⁺ + ne ^- SiF ₂ + 2HF → SiF ₄ + H ₂ SiF ₄ + 2HF → H ₂ SiF ₆ or Si + 4HF + (4 -λ) e ⁺ → SiF ₄ + 4H ⁺ + λe ^- SiF ₄ + 2HF → H ₂ SiF ₆ Here, e ⁺ and e ⁻ represent a hole and an electron, respectively. Further, n and λ are the numbers of holes required for dissolving one silicon atom, respectively, and porous silicon is formed when the condition of n> 2 or λ> 4 is satisfied.

From the above, P-type silicon having holes is made porous, but N-type silicon is not made porous. The selectivity of this porosification has been demonstrated by Nagano et al. And Imai (Nagano, Nakajima, Anno, Ohnaka, Kajiwara; IEICE technical report, vol 79, SSD 79-
9549 (1979), (K. Imai; Solid-State Electronics vo
l 24,159 (1981)).

However, there is also a report that high-concentration N-type Si is made porous (RP Holmstrom and JY Chi.
Appl.Phys.Lett. Vol.42,386 (1983)), P type and N type, it is important to select a substrate that can realize porosity.

Further, since the porous layer has a large amount of voids formed therein, its density is reduced to less than half. As a result, the surface area increases dramatically compared to the volume,
Its oxidation rate is higher than that of a normal single crystal layer.
Accelerated over 100 times (H. Takai, T. Ito, J. Appl. Phys.
vol 60, no1, p.222 (1986)).

That is, as described above, since the oxidation rate of the Si single crystal substrate at 1200 ° C. is about 1 micron / hour, the oxidation rate of the porous Si reaches about 100 micron / hour or more, that is, several hundreds of microns. It is also possible to oxidize the entire wafer having a thickness of 1 to 3 in a practical range. Furthermore, the oxidation time can be further shortened by utilizing the phenomenon that the oxidation rate is increased in the oxidation under a pressure higher than atmospheric pressure (N. Tsubouchi, H.
Miyoshi, A. Nishimoto and H. Abe, Japan J.Appl.Phys.
vol 16, no 5,855, (1977)).

As shown in FIG. 2B, the Si ₃ N ₄ layer 2 is formed on the surface of the intrinsic or low concentration N type Si layer as an antioxidant film.
4 is deposited, and as described above, the P-type porous Si substrate 23 is formed.
Is oxidized to form SiO ₂ and the light-transmissive insulating substrate 25
To create. A thin SiO ₂ layer may be inserted as a buffer layer between the intrinsic or low-concentration N-type Si layer surface and the anti-oxidation film or Si ₃ N ₄ layer 24 in order to avoid introducing defects due to strain.

In general, when a single crystal of Si is oxidized, its volume is increased by about 2.2 times, but by controlling the density of porous Si, it is possible to suppress the volume expansion of the single crystal and to prevent warpage of the substrate. It is possible to avoid cracks introduced into the surface residual single crystal layer. The volume ratio R of the single crystal Si after the oxidation to the porous Si can be expressed as follows.

R = 2.2 × (A / 2.33) where A is the density of porous Si. If R = 1,
That is, when there is no volume expansion after oxidation, A = 1.0
It becomes 6 (g / cm ² ), and volume expansion can be suppressed by setting the density of the porous layer to 1.06.

FIG. 2C shows the semiconductor substrate obtained by the present invention. That is, by removing the Si ₃ N ₄ layer 24 as an antioxidant film in FIG. 2B,
A single crystal Si layer 22 having a crystallinity equivalent to that of a silicon wafer is flatly and uniformly thinned on the SiO ₂ light transmissive insulating substrate 25, and is formed in a large area over the entire wafer.

The semiconductor substrate thus obtained can be preferably used from the viewpoint of producing an electronic element on a light transmissive substrate which is insulated and separated.

The above is the intrinsic or porosity before being made porous.
In this method, a low-concentration N-type layer is formed, and then only the P-type substrate is made porous by anodization.

As described above, the porous Si layer has pores with an average diameter of about 10 angstroms formed by observation with a transmission electron microscope, and its density is half that of single crystal Si. Despite the following, single crystallinity is maintained, and it is also possible to epitaxially grow a single crystal Si layer on top of the porous layer. However, at 1000 ° C or higher, rearrangement of internal pores occurs,
Loss of enhanced oxidation properties. Therefore, for the epitaxial growth of the Si layer, low temperature growth such as low pressure CVD, molecular beam epitaxial growth, plasma CVD, photo CVD, bias sputtering, etc. is suitable.

A method of epitaxially growing a single crystal layer after making the entire P-type substrate porous is also effective.

A method for epitaxially growing a single crystal layer after making all of the P-type substrate porous will be briefly described.

First, a P-type Si single crystal substrate is prepared, and the whole is made porous. Next, epitaxial growth is performed on the surface of the porous substrate by low temperature growth to form a thin film single crystal layer. Then, after depositing silicon nitride of the anti-oxidation film on the surface of the epitaxial layer, it is oxidized to transform the entire porous substrate into silicon oxide. Finally, the anti-oxidation film on the surface is removed to obtain a single crystal layer on the light transmissive insulator substrate.

Next, the single crystal thin layer on the surface of the light transmissive substrate thus produced is separated by the partial oxidation method or island-shaped etching as shown in FIG. Next, P-type impurity ions are formed on the single crystal silicon island (4 in FIG. 1) in which the N channel transistor (2 in FIG. 1) is to be formed, and single crystal silicon in which the P channel transistor (3 in FIG. 1) is to be formed. N-type impurity ions are independently implanted into the island (5 in FIG. 1).

Next, a gate insulating film (6, 7 in FIG. 1) is formed on each of the single crystal silicon layers (4, 5 in FIG. 1), and a gate electrode of polycrystalline silicon (8, FIG. 1) is formed.
9) is patterned and formed.

Source and drain regions are formed by self-aligned ion implantation of impurities using the polycrystalline silicon gate electrode as a mask. A source region (10 in FIG. 1) and a drain region (11 in FIG. 1) are formed by implanting N-type impurity ions into the N-channel transistor (2 in FIG. 1).
For the P-channel transistor (3 in FIG. 1), P-type impurity ions are implanted and the source (1 in FIG.
2) and the drain region (13 in FIG. 1). Source and drain electrodes (14, 15, 16 and 17 in FIG. 1) are formed by depositing and patterning a metal thin film to complete the device. A complementary field effect transistor is manufactured by connecting each element to each other by a thin film electrode.

[0049]

EXAMPLES The present invention will be described below with reference to specific examples. (Example 1) A P-type (10
0) An N-type Si epitaxial layer was grown to 1 micron on the single crystal Si substrate by the CVD method. The deposition conditions are as follows.

Reaction gas flow rate: SiH ₂ Cl ₂ 1000 SCCM H ₂ 230 l / min. PH ₃ (50 ppm) 72 SCCM Temperature: 1080 ° C. Pressure: 80 Torr Time: 2 min. This substrate was anodized in a 50% HF solution. The current density at this time was 100 mA / cm ² . The rate of porosity at this time is 8.4 μm / mi.
n. And a P-type (10
0) The entire Si substrate became porous in 24 minutes. As described above, in this anodization, only the P-type (100) Si substrate was made porous, and the N-type Si epitaxial layer remained unchanged. Next, 0.1 μm of Si ₃ N ₄ was deposited on the surface of this epitaxial layer by a low pressure CVD method to form an antioxidant film, and then only the P-type (100) Si substrate was oxidized. As described above, the thermal oxidation rate of a normal Si single crystal is approximately 1 micron / hour (1200 ° C. wet oxidation, atmospheric pressure), but the oxidation rate of the porous layer is about 100 times higher than that. That is, a porous P-type (100) Si substrate having a thickness of 200 microns was oxidized in 2 hours. After removing the Si ₃ N ₄ layer, a single crystal Si layer having a thickness of 1 μm could be formed on the transparent SiO ₂ substrate.

As a result of cross-sectional observation with a transmission electron microscope, S
No new crystal defect was introduced into the i layer, and it was confirmed that good crystallinity was maintained.

A field effect transistor was formed on the above single crystal silicon thin film and connected to each other to manufacture a complementary element and its integrated circuit. Since a known MOS integrated circuit manufacturing technique is used for the method of manufacturing each transistor, description thereof will be omitted, and only the method of forming a substantial single crystal semiconductor layer will be described. The same applies to the following examples. (Example 2) P-type (10
0) An N-type Si epitaxial layer was grown to 0.5 μm on the Si substrate by the CVD method. The deposition conditions are as follows.

Reaction gas flow rate: SiH ₂ Cl ₂ 1000 SCCM H ₂ 230 l / min. PH ₃ (50 ppm) 72 SCCM Temperature: 1080 ° C. Pressure: 80 Torr Time: 1 min. This substrate was anodized in a 50% HF solution. The current density at this time was 100 mA / cm ² . The porosification rate at this time was 8.4 μm / min. And P-type (100) Si with a thickness of 200 microns
The entire substrate became porous in 24 minutes. As described above, in this anodization, only the P-type (100) Si substrate was made porous, and the N-type Si epitaxial layer remained unchanged. Si ₃ N ₄ was deposited to a thickness of 0.1 μm on the surface of this epitaxial layer by a low pressure CVD method to form an antioxidant film, and then only the P-type (100) Si substrate was oxidized. The thermal oxidation rate of a normal Si single crystal is about 1 micron per hour (1200 ° C. wet oxidation, atmospheric pressure), but the oxidation rate of the porous layer is about 100 times higher. Furthermore, in order to shorten the oxidation time, oxidation was performed under high pressure. 6.57
When wet oxidation at 1200 ° C. was performed under a pressure of kg / cm ² , a 5 times higher oxidation rate was obtained, and a P-type (100) Si substrate having a thickness of 200 μm and made porous was
Oxidation was complete in 24 minutes. After removing the Si ₃ N ₄ layer, a single crystal Si layer having a thickness of 0.5 μm could be formed on the transparent SiO ₂ substrate.

As a result of cross-sectional observation with a transmission electron microscope, S
No new crystal defect was introduced into the i layer, and it was confirmed that good crystallinity was maintained. (Example 3) A P-type (10
0) The single crystal Si substrate was anodized in a 50% HF solution. The current density at this time is 100 mA / cm
^{Was 2} . The porosity rate at this time was 8.4 μm / m.
in. And a P-type (10
0) The entire Si substrate became porous in 24 minutes. On the P-type (100) porous Si substrate, a Si epitaxial layer was grown at a low temperature of 0.5 μm by MBE (Molecular Beam Epitaxy) method. The deposition conditions are as follows.

Temperature: 700 ° C. Pressure: 1 × 10 ⁻⁹ Torr Growth rate: 0.1 nm / sec After the surface of this epitaxial layer was oxidized by 50 nm, Si ₃ N ₄ was deposited by 0.1 μm by the low pressure CVD method,
After forming the antioxidant film, only the P-type (100) Si substrate was oxidized. The porous P-type (100) Si substrate with a thickness of 200 microns was oxidized in 2 hours. After removing the Si ₃ N ₄ layer, a single crystal Si layer having a thickness of 0.5 μm could be formed on the transparent SiO ₂ substrate.

As a result of cross-sectional observation with a transmission electron microscope, S
No new crystal defect was introduced into the i layer, and it was confirmed that good crystallinity was maintained. (Example 4) A P-type (10
0) The single crystal Si substrate was anodized in a 50% HF solution. The current density at this time is 100 mA / cm
^{Was 2} . The porosity rate at this time was 8.4 μm / m.
in. And a P-type (10
0) The entire Si substrate became porous in 24 minutes. On the P-type (100) porous Si substrate, a Si epitaxial layer was grown at a low temperature of 0.5 μm by the plasma CVD method. The deposition conditions are as follows. Gas: SiH ₄ High frequency power: 100 W Temperature: 800 ° C. Pressure: 1 × 10 ^-2 Torr Growth rate: 2.5 nm / sec After oxidizing the surface of this epitaxial layer by 50 nm, Si ₃ N ₄ was 0.1 μm by low pressure CVD method. Pile up,
After forming the antioxidant film, only the P-type (100) Si substrate was oxidized. The porous P-type (100) Si substrate with a thickness of 200 microns was oxidized in 2 hours. After removing the Si ₃ N ₄ layer, a single crystal Si layer having a thickness of 0.5 μm could be formed on the transparent SiO ₂ substrate. As a result of cross-section observation with a transmission electron microscope, Si
It was confirmed that no new crystal defect was introduced into the layer and that good crystallinity was maintained. (Example 5) A P-type (10
0) The single crystal Si substrate was anodized in a 50% HF solution. The current density at this time is 100 mA / cm
^{Was 2} . The porosity rate at this time was 8.4 μm / m.
in. And a P-type (10
0) The entire Si substrate became porous in 24 minutes. A Si epitaxial layer was grown at a low temperature of 0.5 micron on the P-type (100) porous Si substrate by the MBE method. The deposition conditions are as follows.

Temperature: 700 ° C. Pressure: 1 × 10 ⁻⁹ Torr Growth rate: 0.1 nm / sec S was formed on the surface of this epitaxial layer by a low pressure CVD method.
After depositing i ₃ N ₄ to a thickness of 0.1 μm to form an antioxidant film, only the P-type (100) Si substrate was oxidized. In addition,
Oxidation under high pressure was performed to shorten the oxidation time (6.5.
1200 ° C. under a pressure of 7 kg / cm ² , wet oxidation). Porous P with a thickness of 200 microns
The mold (100) Si substrate was completed in 24 minutes. Si ₃ N
After removing the _four layers, a single crystal Si layer having a thickness of 0.5 μm could be formed on the transparent SiO ₂ substrate.

As a result of the cross-section observation by the transmission electron microscope, S
No new crystal defect was introduced into the i layer, and it was confirmed that good crystallinity was maintained. (Example 6) A P-type (10
0) Anodization was performed on a single crystal Si substrate in a 50% HF solution. The current density at this time is 100 mA / c
It was m ² . The porosity rate at this time is 8.4 μm /
min. And a P-type (1
The entire 00) Si substrate was made porous in 24 minutes.

On the P-type (100) porous Si substrate, a Si epitaxial layer was grown at a low temperature of 0.5 μm by the plasma CVD method. The deposition conditions are as follows. Gas: SiH ₄ High frequency power: 100 W Temperature: 800 ° C. Pressure: 1 × 10 ^-2 Torr Growth rate: 2.5 nm / sec After the surface of this epitaxial layer was thermally oxidized by 50 nm, Si ₃ N ₄ was reduced to 0. After depositing 1 μm and forming an antioxidant film, only the P-type (100) Si substrate was oxidized. In addition, in order to shorten the oxidation time, oxidation was performed under high pressure (1 at a pressure of 6.57 kg / cm ^2).
200 ° C, wet oxidation). The oxidized P-type (100) Si substrate having a thickness of 200 μm was completely oxidized in 24 minutes. After removing the Si ₃ N ₄ layer, a single crystal Si layer having a thickness of 0.5 μm could be formed on the transparent SiO ₂ substrate.

As a result of cross-sectional observation by a transmission electron microscope, S
No new crystal defect was introduced into the i layer, and it was confirmed that good crystallinity was maintained. (Example 7) P-type (10
0) N ions are formed on the surface of the Si substrate by ion implantation of protons.
A type Si layer was formed to 1 micron. H ⁺ injection amount is 5 × 1
It was 0 ¹⁵ (ions / cm ² ). 50% of this board
Anodization was performed in the HF solution. The current density at this time was 100 mA / cm ² . The porosification rate at this time was 8.4 μm / min. And the total thickness of the P-type (100) Si substrate with a thickness of 200 microns is 24
Porosified in minutes. As described above, in this anodization, only the P-type (100) Si substrate is made porous and the N-type S is formed.
There was no change in the i layer. The surface of this N-type Si layer is 50
nm thermal oxidation and then Si ₃
After depositing 0.1 μm of N ₄ to form an antioxidant film, only the P-type (100) Si substrate was oxidized. Porous P-type (100) Si with a thickness of 200 microns
The substrate was oxidized in 2 hours. After removing the Si ₃ N ₄ layer, a single crystal Si layer having a thickness of 1 μm could be formed on the transparent SiO ₂ substrate.

As a result of cross-section observation by a transmission electron microscope, S
No new crystal defect was introduced into the i layer, and it was confirmed that good crystallinity was maintained.

[0062]

As described in detail above, according to the insulated gate field effect transistor and the semiconductor device using the same according to the present invention, it is formed on the light transmissive substrate obtained by oxidizing the porous substrate. A high-performance insulated gate field effect transistor is manufactured by forming a high-quality single crystal layer. As a result, it is possible to provide an integrated circuit at a low price, in which the light-transmissive substrate has little stray capacitance and can operate at high speed, and does not have a latch-up phenomenon.

Conventionally, a good quality single crystal layer could not be obtained on a light-transmissive substrate typified by glass because the crystal structure of the substrate is generally amorphous. According to this, since the originally good quality single crystal Si layer on the porous Si substrate is used as a starting material, the single crystal layer can be left only on the surface, and the lower porous Si substrate can be transformed into transparent SiO ₂ . It becomes possible to fabricate a high-performance drive element on a light-transmissive substrate, which is essential for a contact sensor or a projection-type liquid crystal image display device, and it is possible to perform a large number of processes in a short time. There has been a great deal of economic progress.

[Brief description of drawings]

FIG. 1 is a schematic sectional view of a complementary insulated gate field effect transistor according to the present invention.

FIG. 2 is a schematic cross-sectional view for explaining a substrate manufacturing process of the present invention.

[Explanation of symbols]

1 light transmissive silicon oxide substrate, 2 N-channel field effect transistor, 3 P-channel field effect transistor,
4 island-shaped single crystal layer, 5 island-shaped single crystal layer, 6 gate oxide film, 7 gate oxide film, 8 gate electrode, 9
Gate electrode, 10 source region, 11 drain region, 12 source region, 13 drain region, 14
Source electrode, 15 drain electrode, 16 source electrode, 17 drain electrode, 21 Si single crystal substrate,
22 Si single crystal layer, 23 Porous Si substrate, 24
Si ₃ N ₄ antioxidant film, 25 light transmissive SiO ₂ substrate.

Claims (5)

[Claims] 1. A non-porous single crystal layer on a silicon substrate in which a single crystal layer constituting at least a channel region of an insulated gate field effect transistor is made porous. An insulated gate field effect transistor, which is the non-porous single crystal layer on a light-transmitting insulating substrate obtained by oxidation. 2. The insulated gate field effect transistor according to claim 1, wherein the channel region of the insulated gate field effect transistor is an N type channel. 3. The insulated gate field effect transistor according to claim 1, wherein the channel region of the insulated gate field effect transistor is a P type channel. 4. A semiconductor device comprising the insulated gate field effect transistor according to claim 2 or 3 as a constituent element. 5. A complementary field effect semiconductor device comprising the insulated gate field effect transistor according to claim 2 or claim 3 as a constituent element.