JPH0536830A - Shaping method in layout compaction - Google Patents

Abstract

PURPOSE:To minimize the wiring length of a specified wiring layer for minimizing the resistance value of respective nets in wiring region to the utmost. CONSTITUTION:The four steps enumerated as follows are performed: the understanding step of the connection state of respective nets in the wired wiring region by a detailed wiring system (step 12), the downward packing step to minimize the height in the wiring region (step 13), the upward packing step by maintaining the height in the wiring region and eliminating the useless bend in wiring (step 14) and the shaping step by minimizing the wiring length in consideration of the connection state of respective nets in the wiring region (step 15). Through these procedures, the delay value in the circuits such as LSI, etc., can be easily achieved.

Description

Detailed Description of the Invention

[0001]

BACKGROUND OF THE INVENTION 1. Field of the Invention The present invention relates to a layout compaction method for reducing the manufacturing cost of a VLSI or the like by obtaining a layout of a minimum area that satisfies a design rule in a layout system such as a VLSI.

[0002]

2. Description of the Related Art "Nutcracker: Anefficient and int" is a typical representative of conventional practical compaction methods.
elligent channel spacer ”(in Proc. 24th Design Au
to-mation Conf., 1987, pp.298-304) and "High-speed multifunctional channel spacer with via deletion" (IEICE Transactions A Vol. J72-A No. 2 pp.
349-358 (February 1989).

[0003]

According to the conventional compaction method, when compaction is performed in the vertical (vertical) direction with respect to the wiring area wired by the detailed wiring system, the object of compaction (wiring , Contact, etc.), bend the wiring, move the object of compaction to a position closest to the lower side of the wiring area that complies with the design rule, and make the height (or width) of the wiring area to be the bottom justification processing, A position where the height (or width) of the wiring area obtained by this bottom filling processing is maintained, the object of the compaction is searched from the top to the bottom of the wiring area, and design rules are obeyed to eliminate unnecessary wiring bends. Top-up processing to move the object of compaction to the above, and adjustment to delete useless bends that could not be deleted by the above-mentioned packing processing. Consisting of three process steps.
(For details, see “High-speed multifunctional channel spacer with via deletion” (Journal of the Institute of Electronics, Information and Communication Engineers, A Vol. J72).
-A No. 2 pp. 349-358 1989 2
Month))).

This will be described with reference to FIG. 2 showing the layout of the result of the detailed wiring system, FIG. 3 showing the result of the bottom filling process, FIG. 4 showing the result of the top filling process, and FIG. 6 showing the result of the shaping process. To do.

In the conventional method, when performing the top-down processing and the shaping processing, only the horizontal wirings to be compacted (hereinafter referred to as horizontal wirings) and the positions of the respective nets of the contacts that comply with the vertical design rule are considered. It does not consider the connection status or the connection status and wiring layer information. Considering only the positions of the horizontal wiring to be compacted and the nets of the contacts that comply with the design rule in the vertical direction, for example, in the case of net1 in FIG. 2, the positions satisfying the design rule are set to the bottom of FIG. The optimum position can be uniquely located anywhere between the position that satisfies the design rule closest to the lower boundary of the wiring area and the position that satisfies the design rule closest to the upper boundary of the wiring area on the upper side of FIG. This cannot be determined, and in the worst case, as shown in FIG. 4, the vertical wirings LV1 and LV2 of net1 (hereinafter referred to as vertical wirings) may be the longest and the wiring length may not be minimized.

Further, in order to satisfy the delay value of a circuit such as an LSI, the wiring length of a specific wiring layer, for example, a wiring layer having a very large resistance value as compared with other wiring layers such as polysilicon is minimized. Need to be converted. For example, in the resulting layout of the detailed wiring system of FIG.
The horizontal wiring LH102 of FIG.
10 may be used, but if the resistance value of LV103 is much larger than that of LV104, for example, LV10
If 3 is polysilicon wiring and LV104 is aluminum wiring,
LH102 and VIA101 minimize the resistance value of net102 at the position shown in FIG. 9, but if the wiring layer is not considered,
H102 may come to the position shown in Fig. 10. At this time, ne
There is a possibility that the resistance value of t102 is maximized, the delay value of the circuit such as LSI is not satisfied in the worst case, and the circuit does not operate.

The present invention solves these problems, and minimizes the wiring length as much as possible in consideration of the connection state of each net of the wiring in the wiring area and the wiring layer information, and further, the wiring length of a specific wiring layer. It is an object of the present invention to provide a shaping processing method in layout compaction that minimizes the resistance value of each net of the wiring in the wiring region as much as possible by minimizing.

[0008]

In order to solve the above problems, the shaping processing method in the layout compaction of the present invention recognizes the connection state of each net of the wired wiring area by the detailed wiring system and The bottom filling process that minimizes the height of the wiring is performed, the height of this wiring region is maintained, and the top filling process that removes unnecessary bends in the wiring is performed, and the connection state of each net in the wiring region is considered. Then, the wiring length is minimized and shaped.

Further, in the shaping processing method in the layout compaction of the present invention, the detailed wiring system recognizes the connection state of each net of the wiring of the wired wiring area and the wiring layer information to minimize the height of the wiring area. The bottom-up processing is performed to maintain the height of this wiring area, and the top-down processing is performed to remove unnecessary bends in the wiring, and the connection status and wiring layer information of each net in the wiring area In consideration of this, the wiring length of a specific wiring layer is minimized and shaped.

[0010]

With the above configuration, the wiring length of each net is minimized in consideration of the connection state of each net in the wiring region, or the resistance value of each net is determined in consideration of the connection state of each net in the wiring region and the wiring layer. Since it is minimized, it is possible to avoid a situation where the delay value of the LSI or the like cannot be satisfied and the circuit does not operate in the worst case.

[0011]

DETAILED DESCRIPTION OF THE PREFERRED EMBODIMENTS An embodiment of the present invention will be described below with reference to the drawings. FIG. 1 shows a flow chart of a shaping processing method in the layout compaction of the first embodiment of the present invention, which is adapted to the layout of FIG. Here, the compaction is performed in the vertical direction. In FIG. 2, LH1
To LH4 are horizontal wiring, LV1 to LV10 are vertical wiring, VI
A1 to VIA4 are contacts. Further, in FIG. 3, LH4-1 and LH4-2 are wirings that are generated by dividing LH4 into two by downsizing processing, and LV10 is inserted between LH4-1 and LH4-2 at that time and jog and Wiring.

Further, net1 to net4 represent nets. Here, net1 is LH1, LV1, and L
V2, net2 is LH2, LV3 and L
It is composed of V4, VIA1 and VIA2, and net3
Is composed of LV3, LV5, and LV6, and net4
Are LV4, LV7, LV8, LV9, VIA3 and VI
It is composed of A4. For the sake of simplicity, the wiring layer of the layout of FIG.
3, LV4, LV1, LV2, LV5, LV6, LV10
Is the first layer aluminum wiring, LV3, LV4, LV7, LV
8 and LV9 are second layer aluminum wirings, and the wirings have the same resistance value.

In FIG. 1, a process 11 includes wiring data of a design rule and a wiring area necessary for layout compaction (here, wiring data is a shape of the wiring area, horizontal wiring, vertical wiring, contacts, and layout for simplification. The target of compaction processing is horizontal wiring and contacts).

By the process 12, the state of the vertical wiring connected to the horizontal wiring and the contact of each net in the wiring area which is the processing object of the layout compaction is recognized, and weighting is applied to each net composed of the horizontal wiring, the vertical wiring and the contact. I do. If the vertical wiring is connected from the lower boundary of the wiring area to the horizontal wiring and contact that are the compaction target, a negative value is connected, and the vertical wiring is connected from the upper boundary of the wiring area to the horizontal wiring and contact that is the compaction target. If so, each net is given a positive value as a weight. However, since the resistance values of the wirings are the same, it is assumed that the negative value and the positive value have the same absolute value (here, the absolute value is 1).

In FIG. 2, net1 is LH1, LV
1 and LV2, and the weight Wnet1 for net1
LV1 and LV2 are connected to the compaction target LH1 from the lower boundary of the wiring region, respectively.
The weight of net1 is the weight WLV given to net1 by LV1.
1 and LV2 is the sum of the weights WLV2 given to net1. Here, the weight Wnet1 of net1 is: WLV1 = -1 WLV2 = -1 Wnet1 = WLV1 + WLV2 = -1 + (-1) =-2.

Similarly, net2 is LH2, LV3, LV
4, VIA1 and VIA2, LV3 is connected from the lower boundary of the wiring area to VIA1 which is a compaction target, and LV4 is connected from the upper boundary of the wiring area to VIA2 which is a compaction target.
The weight Wnet2 of Wnet2 is Wnet2 = WLV3 + WLV4 = -1 + 1 = 0.

Similarly, net3 is LH3, LV5, LV
6 and LV5 and LV6 are connected to the compaction target LH3 from the lower boundary of the wiring region, respectively. Therefore, the weight Wnet3 of net3 is Wnet3 = WLV5 + WLV6 = -1 + (-1) =-2 net4 is LH4. , LV7, LV8, LV9, VIA
LV7 is connected to the VIA3 which is a compaction target from the lower boundary of the wiring region, and LV8 is a VIA which is a compaction target from the lower boundary of the wiring region.
4 and the LV9 is connected from the upper boundary of the wiring area to the VIA4 which is a compaction target.
The weight Wnet4 of Wnet4 is Wnet4 = WLV7 + WLV8 + WLV9 = -1 + (-1) + 1 = -1.

Process 13 searches for horizontal wiring and contacts from the lower boundary of the wiring area to the upper boundary, automatically inserts a jog in the horizontal wiring and bends the horizontal wiring, and sets the design rule closest to the lower boundary of the wiring area. The horizontal wiring and the contact are moved to the protected position to minimize the height of the wiring area as shown in FIG.

In the process 14, in order to maintain the height of the wiring region minimized in the process 13 and remove the unnecessary bending of the horizontal wiring, the horizontal wiring and the contact are searched from the upper boundary to the lower boundary of the wiring region. Then, as shown in FIG. 4, it moves to a position where the design rule is obeyed and unnecessary bends of the horizontal wiring are removed.

The details of processing 13 and processing 14 are as follows.
“Nutcracker: An efficient and intelligent channel
spacer ”(in Proc. 24th Design Auto-mation Conf.,
1987, pp.298-304) and "High-speed multifunctional channel spacer with via deletion" (IEICE Transactions A)
Vol. J72-A No. 2 pp. 349-358
See February 1989).

The process 15 is executed by the process 12, ie, net1 to net.
In consideration of the weights Wnet1 to Wnet4 attached to 4
Horizontal wiring and contacts are searched from the lower boundary to the upper boundary of the wiring region so as to minimize the wiring lengths of et1 to net4, and the shaping process is performed.

Since the shaping process for net1 is the weight Wnet1 = -2 of net1, the number of vertical wires connected from the lower boundary of the wiring area to the LH1 which is the compaction target of net1 is connected from the upper boundary of the wiring area. It was found that there were more than the number of vertical wirings, and LH1 which is a compaction target of net1 satisfies the design rule,
By moving to a position that is closest to the lower boundary of the wiring area without causing unnecessary bending, the wiring length of net1 is minimized and shaping is performed.

In the shaping process for net2, since the weight Wnet2 of net2 = 0, the number of vertical wires connected to the LH2, VIA1, and VIA2 which are compaction targets of net2 from the lower boundary of the wiring area is the upper boundary of the wiring area. It is found that the number is the same as the number of vertical wirings connected from
The shaping of net2 is performed by moving 2 and VIA1 and VIA2 to a position that is closest to the lower boundary of the wiring area or the upper boundary of the wiring area, which satisfies the design rule and does not cause unnecessary bending. in this case,
LH2, VIA1, and VIA2 may be located anywhere between the positions closest to the lower boundary of the wiring region or the upper boundary of the wiring region.

The shaping process of net3 is performed by weighting W of net3.
Since net3 = -2, it can be seen that the number of vertical wirings connected to the LH3, which is a compaction target of net3, from the lower boundary of the wiring area is larger than the number of vertical wirings connected from the upper boundary of the wiring area. LH3 which is a compaction target of net3 meets the design rule,
By moving to a position closest to the lower boundary of the wiring area without causing unnecessary bending, the wiring length of the net3 is minimized and shaping is performed.

Similarly, in the shaping process of net4, the weight of net4 is Wnet4 = −1, so that LH is the same as for net1.
4, LH5, VIA3, and VIA4 satisfy the design rules, move to a position closest to the lower boundary of the wiring region without causing unnecessary bending, thereby minimizing the wiring length of net4 and performing shaping.

FIG. 5 shows the result of the first embodiment, and FIG. 6 shows the result of the conventional method. According to the conventional method, the wiring length of net1 cannot be minimized. It turns out that the length can be minimized. The first embodiment is also effective for a layout having two or more wiring layers.

FIG. 7 shows a flow chart of the shaping processing method in the layout compaction of the second embodiment of the present invention.
This is adapted to the layout of FIG. Here, the compaction is performed in the vertical direction. In FIG.
LH101 to LH105 and LH are horizontal wiring, LV101 to LV
Reference numeral 111 denotes a vertical wiring and VIA101 to VIA104 contacts. Further, in FIG. 9, LH104 −1 and LH104 −
Reference numeral 2 is a wiring generated by dividing the LH104 by the bottom filling processing, and the LV112 is LH104 −1 and LH104 − at that time.
It is a wire that is inserted between 2 and becomes a jog.

Further, net 101 to net 105 represent nets. net101 is LH101, LV101, LV
102, LET 102, LV 103,
LV104 and VIA101, net103 is LV1
05, LV106 and VIA102, net104 is composed of LH103, LV107 and LV108, and net105
Is LV104, LV109, LV110, LV111, VIA1
03, VIA104. For simplification, the wiring layer of the layout of FIG. 8 is a two-layer wiring of polysilicon and aluminum, and the wiring resistance value is aluminum 1 and polysilicon 100, and LH101 to LH104 and LV101, LV102, LV104.
, LV106, LV107, LV108, LV111, LV112
Is the second layer aluminum wiring, LV103, LV105, LV109
, LV110 are first layer polysilicon wirings.

By the process 101, the design rule and the wiring data of the wiring area necessary for the layout compaction (here, the wiring data are simple, the shape of the wiring area, the horizontal wiring, the vertical wiring, and the contact, and the layout compaction processing target is Horizontal wiring and contacts)
Enter.

By the process 102, the state of the vertical wiring connected to the horizontal wiring and the contact and the wiring layer of each net in the wiring area which is the processing object of the layout compaction is recognized, and each net including the horizontal wiring, the vertical wiring and the contact is recognized. Is weighted. If the vertical wiring is connected from the terminal at the lower boundary of the wiring area to the net consisting of the horizontal wiring and the contact, a negative value is given. From the terminal at which the vertical wiring is at the upper boundary of the wiring area, from the horizontal wiring and the contact. When connecting to a net, the positive value is weighted according to the resistance value (absolute value of positive and negative values is 100 for polysilicon wiring, absolute value of positive and negative value is 1 for aluminum wiring) To). In FIG. 8, n
et101 is composed of LH101, LV101, and LV102,
The weights for the net101 are LV101 and LV102, respectively, from the lower boundary of the wiring area to the compaction target L.
Since it is connected to H101 and has aluminum wiring,
The weight of t101 is the weight WL given to net101 by LV101.
Weight WLV102 given to net101 by V101 and LV102
The sum of Here, the weight Wnet101 of net101 is WLV101 = -1 WLV102 = -1 Wnet101 = WLV101 + WLV102 = -1 + (-1) =-2.

Similarly, net102 is LH102, LV103
, LV104, VIA101, and LV103 is a polysilicon wiring connected from the lower boundary of the wiring area to VIA101 which is a compaction object, and LV104 is an aluminum wiring which is an LH102 which is a compaction object from the upper boundary of the wiring area.
Therefore, the weight Wnet102 of net102 is Wnet102 = WLV103 + WLV104 = −100 + 1 = −99.

Similarly, net103 is LV105, LV106
, VIA102, LV105 is a polysilicon wiring from the lower boundary of the wiring area, and LV106 is an aluminum wiring from the upper boundary of the wiring area.
Since it is connected to the IA102, the weight Wne of the net103 is
t103 is Wnet103 = WLV105 + WLV106 = -100 + 1 = -99 Similarly, net104 is composed of LV103, LV107, and LV108, and LV107 and LV108 are aluminum wirings, and LH103 which is a compaction object from the lower boundary of the wiring area.
Therefore, the weight Wnet104 of net104 is Wnet104 = WLV107 + WLV108 = -1-1 = -2 net105 is LH104, LV109, LV110, LV11.
1, VA103 and VIA104, LV111 is an aluminum wire connected from the upper boundary of the wiring area to VIA104 which is a compaction object, and LV109 is a polysilicon wire which is a VIA which is a compaction object from the lower boundary of the wiring area.
Since the LV110 is connected to 103 and the LV110 is connected to the VIA104 which is a compaction target from the lower boundary of the wiring region by the polysilicon wiring, the weight Wnet105 of the net105 is Wnet105 = WLV109 + WLV110 + WLV111 = -100 + (-100) + 1 = -199. Becomes

The process 103 searches for horizontal wiring and contacts from the lower boundary of the wiring area to the upper boundary, automatically inserts a jog in the horizontal wiring, bends the horizontal wiring, and sets the design rule near the lower boundary of the wiring area. The horizontal wiring and the contact are moved to the protected position to minimize the height of the wiring area as shown in FIG.

In process 104, the height of the wiring region minimized in process 103 is retained, and in order to eliminate the unnecessary bending of the horizontal wiring, horizontal lines and contacts are searched from the upper boundary to the lower boundary of the wiring region. Then, as shown in FIG. 10, the design rule is followed and the position is moved to a position where the unnecessary bending of the horizontal wiring is removed.

For details of processing 103 and processing 104, refer to "Nutcracker: An efficient and intelligent cha.
nnel spacer ”(in Proc. 24th Design Auto-mation Co
nf., 1987, pp.298-304) and "High-speed multifunctional channel spacer with via deletion" (IEICE Transactions A Vol. J72-A No. 2 pp.349-3).
58, February 1989).

The process 105 is performed by the process 102 from net101 to net101.
In consideration of the weights Wnet101 to Wnet105 attached to the net105, horizontal wiring and contacts are searched from the lower boundary of the wiring region to the upper boundary so as to minimize the resistance value of the net101 to net105, and the shaping process is performed.

The shaping process for net101 is net10.
Since the weight of 1 is Wnet101 = -2, it can be seen that the LH101, which is a compaction target of the net101, can minimize the resistance value at the position as close as possible to the lower boundary of the wiring area, and the horizontal wiring LH101 satisfies the design rule and is wasteful. The resistance value of the net 101 is minimized and shaped by moving to a position closest to the lower boundary of the wiring region without causing bending.

The shaping process for net102 is net10.
Since the weight of 2 is Wnet102 = -99, it can be seen that the LH102 and VIA101, which are the compaction targets of the net102, can minimize the resistance value at a position as close as possible to the lower boundary of the wiring area. By moving to a position closest to the lower boundary of the wiring region without causing unnecessary bending, the wiring length of the polysilicon wiring LV103 is minimized and the resistance value of the net102 is minimized to perform shaping.

The shaping process for net103 is net10.
Since the weight of 3 is Wnet103 = -99, it can be seen that the VIA102 which is the compaction target of the net103 can minimize the resistance value at the position as close as possible to the lower boundary of the wiring area, and the VIA102 satisfies the design rule and the lower boundary of the wiring area is satisfied. By moving to a position closest to, the wiring length of the polysilicon wiring LV105 is minimized and the resistance value of the net103 is minimized to perform shaping.

Similarly, the shaping process of net104 is net10.
Since the weight of 4 is Wnet104 = -2, the LH103 satisfies the design rule and no unnecessary bending occurs. By moving to the position closest to the lower boundary of the wiring area, n
Minimize the resistance of et104 and shape.

Similarly, the shaping process for net105 is n
Since the weight Wet105 of et105 = -199, each of the horizontal wirings LH104, VIA103, VIA104 moves to the position closest to the lower boundary of the wiring area, which satisfies the design rule and does not cause unnecessary bending. Where VI
For A103, lower it to the position shown in FIG.
By connecting 103 and LH104 to the aluminum wiring LV112, the wiring length of the polysilicon wirings LV109 and LV110 is minimized, and the resistance value of the net105 is minimized to perform shaping.

FIG. 11 shows the result of the second embodiment, and FIG. 12 shows the result of the conventional method. In the conventional method, net101, net10
2, 2, net103, and net105 cannot minimize the resistance value, but according to the second embodiment, net101, net102,
It can be seen that the resistance values of net103 and net105 can be minimized. The second embodiment is also effective for a layout having two or more wiring layers. Further, the weight added to each net can be changed according to the designer's intention such as VIS, or only the net of a specific wiring can be added.

[0043]

As described above, according to the present invention, the LSI
Regarding the layout pattern such as, considering the connection state of each net in the wiring area, the wiring length can be minimized, and the wiring length of a specific wiring layer can be minimized to minimize the resistance value. It becomes easy to satisfy the delay value of a circuit such as an LSI.

[Brief description of drawings]

FIG. 1 is a flowchart of a shaping processing method in layout compaction according to a first embodiment of this invention.

FIG. 2 is a diagram showing a layout result of the detailed wiring system used in the first exemplary embodiment of the present invention.

FIG. 3 is a diagram showing a result of a bottom filling process in the first embodiment of the present invention.

FIG. 4 is a diagram showing a result of top-justification processing according to the first embodiment of this invention.

FIG. 5 is a diagram showing a shaping processing result in the first embodiment of the present invention.

FIG. 6 is a diagram showing a shaping processing result of the layout shown in FIG. 2 according to a conventional method.

FIG. 7 is a flow chart of a shaping processing method in layout compaction according to a second exemplary embodiment of the present invention.

FIG. 8 is a diagram showing a layout result of the detailed wiring system used in the second exemplary embodiment of the present invention.

FIG. 9 is a diagram showing a result of a bottom filling process according to the second embodiment of the present invention.

FIG. 10 is a diagram showing a result of top-up processing in the second embodiment of the present invention.

FIG. 11 is a diagram showing a shaping processing result according to the second embodiment of the present invention.

FIG. 12 is a diagram showing a shaping processing result of the layout shown in FIG. 8 according to a conventional method.

[Explanation of symbols]

11 Data input processing 12 Processing for recognizing the connection status of each net in wiring area data 13 Bottom filling processing 14 Top justification processing 15 Shaping processing considering the connection status of each net in wiring area data 101 Data input processing 102 Wiring area data Processing for recognizing connection state and wiring layer information of each net 103 Bottom filling processing 104 Top filling processing 105 Shaping processing in consideration of connection state and wiring layer information of each net of wiring area data LH1 to LH4 First layer aluminum wiring LV1, LV2 First layer aluminum wiring LV3, LV4 Second layer aluminum wiring LV5, LV6 First layer aluminum wiring LV7 to LV9 Second layer aluminum wiring LV10 First layer aluminum wiring VIA1 to VIA4 First layer aluminum wiring layer and second layer aluminum Contact with wiring layer LH101 to LH104 Second layer aluminum wiring LV101, LV102 Second layer aluminum wiring LV103 First layer polysilicon wiring LV104 Second layer Lumi wire LV105 First layer polysilicon wire LV106 to LV108 Second layer aluminum wire LV109, LV110 First layer polysilicon wire LV111, LV112 Second layer aluminum wire VIA101 to VIA104 First layer polysilicon wire layer and second layer aluminum wire Layer contact

Claims (2)

[Claims] 1. The detailed wiring system recognizes the connection state of each net in the routed wiring area, minimizes the height of the wiring area, and maintains the height of this wiring area to prevent unnecessary bending of the wiring. A shaping processing method in layout compaction in which the wiring length is minimized and shaped in consideration of the connection state of each net in the wiring area. 2. The detailed wiring system recognizes the connection state and wiring layer information of each net of the wiring in the wired wiring area, minimizes the height of the wiring area, and maintains the height of this wiring area. This is a shaping processing method in layout compaction in which the resistance value of each net is minimized and shaped by further considering the connection state of each net of the wiring in the wiring area and the wiring layer information after eliminating unnecessary bending of the wiring.