JP3014646B2 - Wiring method and compaction method - Google Patents

Description

DETAILED DESCRIPTION OF THE INVENTION

[0001]

The present invention relates to a CMOS LSI
Standard cells or data paths used in integrated circuits such as
The present invention relates to a wiring method and a layout compaction method for leaf cells in an LSI such as a module cell.

[0002]

2. Description of the Related Art Recent advances in automation technology for semiconductor integrated circuit manufacturing systems have given system designers the freedom to select a manufacturing foundry. That is, system designers and design vendors can select a manufacturing foundry that provides the lowest cost and highest performance process technology based on common design data. Due to this tendency, the difference in process technology of each company is directly linked to the competition for LSI orders, and the competition in process technology from an open stand has been intensified.

[0003] The intensification of process technology has led to the acceleration of process technology innovation and the development of high-performance system designs aimed at process technologies to be put into practical use in the near future. .
In addition, design rules are becoming more and more complex in the deep submicron era.
Although the number of rules is limited to about one, currently more than 100 rules are required, and each of them affects the manufacturing cost and the yield, so that it is difficult to determine the rules early. These facts have the following effects on the development of leaf cells in LSI such as standard cells or cells for data path modules.

[0004] 1) The frequency of designing a cell library has been greatly increased due to intensified changes in process technology. Five years ago, it was only necessary to develop one series of libraries every two years. Recently, however, development has been carried out at a frequency of about one year to develop one series of libraries.
The number of cells included in each library is about twice as large as five years ago.

2) A cell cannot be developed and provided in a short period of time unless the cell design is started before the design rules are finalized and the final layout is modified when the rules are finally finalized. .

3) Since the degree of abstraction of the design is shifting from the mask layout and circuit design to the system design, the number of engineers who perform the mask design and circuit design is drastically reduced.

[0007] From the foregoing, the importance of cell synthesis or cell compaction technology is becoming increasingly recognized.
In addition, since the area of the leaf cell directly affects the chip area, and hence the chip cost, the cell area is required to be as high as that of a person or more.

Conventional compaction methods can be classified into one-dimensional compaction and two-dimensional compaction. 1
The dimensional compaction considers only one direction at a time, either parallel or perpendicular to one side of the placement area where the compaction target is placed. In particular,
In the one-dimensional compaction, there is a method of expressing the arrangement and wiring using a lattice, searching for a band-shaped empty region perpendicular or parallel to the arrangement region, and reducing the area by repeatedly removing the empty region. In addition, a method of expressing the left and right or up and down position constraints in a graph, giving the actual distance and the minimum distance between the arrangement elements as information to a branch of the graph, and moving each arrangement element so as to shorten the longest path of the graph. There is.

In any of the methods, only movement in one direction is considered at the same time. Therefore, it is not possible to cope with a case in which the entire compaction can be further performed by moving a part of the arrangement element in another direction even a little. Had a problem. Subsequently, a method of simultaneously moving in two directions to cope with such a problem was proposed as two-dimensional compaction.

A typical example of two-dimensional compaction is “Hyun
chul Shin, Alberto L. Sangiovanni-Vincentelli, Car
lo H. Sequin, "Two-Dimensional Compaction by 'Zone
As described in 'Refining'', when starting from the lowest group of elements to be moved among the arrangement elements inside the cell, and shifting them further down, The optimum arrangement in the horizontal direction is obtained, and the movement is performed to the two-dimensional optimum position. The group to be moved is sequentially shifted to the upper arrangement element, and the operation of moving each group to the lower optimal position is similarly repeated. If such a method is used, items that are problematic in one-dimensional compaction are solved, and better compaction results are obtained.

[0011]

However, the conventional two-dimensional compaction method has a problem that there is no optimum index for the arrangement position. Further, since the movement is simultaneously performed in both directions parallel and perpendicular to the placement area, the placement can be optimized, but the change in the placement causes a large amount of bending of the wiring, which impairs the optimality of the wiring. As a result, there is a problem that the area is increased. Furthermore, there is a problem that it is difficult to effectively handle wirings having different thicknesses.

SUMMARY OF THE INVENTION The present invention has been made in view of the above points, and is a two-dimensional compaction that solves the above-mentioned conventional problems at a glance and achieves a more practical compaction result without impairing the optimality of wiring. The purpose is to be able to generate.

[0013]

SUMMARY OF THE INVENTION In order to achieve the above object, the present invention has a configuration in which all the original wirings are erased once, and compaction is performed simultaneously while new wirings are newly formed.

More specifically, the wiring method according to the present invention abstracts a component into a square having terminals, and abstracts the terminals and the wiring connecting the terminals into wiring connection points and wiring elements. 1 and a net target, which is a set of wiring connection points to be connected to the same potential, in a placement area where a plurality of squares are placed, and a neighboring relationship between the net targets. And a wiring step of connecting the rectangles with each other by the net target and the adjacent relationship. The wiring step scans the scan line toward the net target, and scans the scan line. The path of the front drawn by moving the front on the scan line so as to approach the net target is defined as a wiring path.

According to the wiring method of the present invention, the components are abstracted into squares having terminals, the terminals and the wires connecting the terminals are abstracted into wiring connection points and wiring elements, and a plurality of squares are arranged. In order to abstract the general wiring path connecting the components in the set placement area into a net target, which is a set of wiring connection points to be set to the same potential, and an adjacent relationship between the net targets, a schematic connecting the components is performed. The wiring path is deleted once. Subsequently, in a wiring process, a scan line for scanning the placement area is scanned toward the net target, and a front path drawn by moving the front on the scan line on the scan line so as to approach the net target. This is a wiring route. As a result, a new wiring path connecting the rectangles is generated, so that unnecessary wiring bending can be reduced.

In the compaction method according to the present invention, a first abstraction in which a component is abstracted into a rectangle having terminals, and the terminals and wiring connecting the terminals are abstracted into wiring connection points and wiring elements. In a process and an arrangement area where a plurality of squares are arranged, a general wiring path connecting components is abstracted into a net target which is a set of wiring connection points to be connected to the same potential and an adjacent relationship between the net targets. A second abstraction step, and a wiring and compaction step of connecting and compacting the squares according to the net target and the adjacency relationship. The wiring and compaction step scans a scan line toward the net target and performs scanning. Draw the front on the line by moving it on the scan line closer to the net target. It is comprising a step of the front of the trajectory the routing, when the scanning line is located on the scanning start side of the edge of the square, and a step of compaction of the square to the scanning start direction.

According to the compaction method of the present invention, the components are abstracted into a square having terminals, the terminals and the wiring connecting the terminals are abstracted into wiring connection points and wiring elements, and a plurality of squares are arranged. In order to abstract the general wiring path connecting the components in the set placement area into a net target, which is a set of wiring connection points to be set to the same potential, and an adjacent relationship between the net targets, a schematic connecting the components is performed. The wiring path is deleted once. Subsequently, in the wiring and compaction process, a scan line for scanning the placement area is scanned toward the net target, and the front of the scan line is moved by moving the front on the scan line closer to the net target. The trajectory is used as a wiring path, and when the scan line is located on the side on the scanning start side of the rectangle, the rectangle is compacted in the scanning start direction.
As a result, a wiring path connecting the rectangles is newly generated, so that the rectangle made of the abstracted parts can be compacted reliably while reducing unnecessary wiring bending.

In the compaction method according to the present invention, the wiring and compaction steps are performed by sequentially arranging the position of the wiring connection point and the position of one side parallel to the scan line in the rectangle and the position of the other side opposite to the one side in the net target. A first step of creating a scanning point list that determines the order in which the lines are scanned; and moving the scan line in a direction perpendicular to the scan line according to the scanning point list and moving the front on the scan line closer to the net target. Move on the scan line and compact the straight line connecting the wiring connection point to the destination front in the scan start direction, which is the position where the scan line first started scanning,
A second step of adding a compacted straight line as a wiring element, and, when two fronts on a scan line are in the same direction, merging the two fronts and connecting the fronts to each other. A third step of compacting the obtained straight line in the scanning start direction and adding the compacted straight line as a wiring element; and, when the scan line is located at a wiring connection point,
A fourth step of newly arranging a front at the wiring connection point, adding a wiring element toward the net target targeted by the front, and then erasing the front that no longer needs to extend the wiring element; It is preferable to include a fifth step of setting the square to the wiring prohibited area when the square is positioned on the side opposite to the scanning start side.

As described above, in the first step of the wiring and compaction step, the position of the wiring connection point and the scan line in the rectangle are set in the net target, which is a set of wiring connection points in which the terminals in the square having the terminals are abstracted. A scanning point list in which the positions of the one side and the other side parallel to are sequentially arranged, and in the second step, the wiring connection points are moved while moving the front on the scan line on the scan line so as to approach the net target. Then, a straight line connecting the front and the destination is compacted in the scanning start direction, and the compacted straight line is added as a wiring element. In the third step, when two fronts facing the same direction are generated on the scan line, two fronts are generated on the scan line to connect the fronts so as to be merged. In such a case, a wiring element can be generated. Furthermore, in the fourth step, the generation and disappearance of the front can be reliably performed, and in the fifth step, when the scan line reaches the side on the non-scanning start side of the rectangle, the rectangle is defined as a wiring prohibited area. I do. By these five steps, wiring and compaction between a plurality of net targets can be reliably performed.

In the compaction method of the present invention, when the wiring and compaction steps include the first to fifth steps, the scan line is located on the side on the scanning start side of the rectangle, and the rectangle defines the diffusion region of the transistor. Included in the diffusion island shown, and when the side on the scanning start side that is more square than the other components of the diffusion island is located closest to the scanning start side, the inside of the diffusion island that generates a layout pattern inside the diffusion island It is preferable to include a layout generation step and a diffusion island inside compaction step of compacting the layout pattern inside the diffusion island in the search start direction.

As described above, since the impurity diffusion region of the transistor is defined as a diffusion island, the layout generation processing inside the diffusion island and the entire compaction processing can be handled hierarchically, so that the transistor gate It is possible to cope with complicated layouts such as bending and optimizing the position of the diffusion contact.

In the compaction method according to the present invention, the diffusion island has a plurality of squares composed of a gate, a diffusion region, or a diffusion island contact provided in the diffusion region in its constituent element, A step of sequentially performing compaction in the scanning start direction so as to satisfy the design rule from a rectangle located closest to the scanning start side of a plurality of rectangles, and a rectangle in which scan lines are located in a diffusion island square and the scan line is located In the case where a design rule error occurs between the wiring and the wiring around the diffusion island, a rectangle where the scan line is located and another in the diffusion island located on the anti-scanning start side of the rectangle so as to eliminate the design rule error. It is preferable to include a step of moving the rectangle by the same distance in the anti-scanning start direction.

In this way, when the scan line is located in the square of the diffusion island and a design rule error occurs between the square where the scan line is located and the wiring around the diffusion island, the scan line is located. In order to eliminate the design rule error by moving the rectangle and the other rectangle in the diffusion island located on the anti-scanning start side of the rectangle by the same distance in the anti-scanning start direction, compaction inside the diffusion island can be surely performed. You.

In the compaction method of the present invention, the diffusion island has, as its constituent elements, a plurality of squares each composed of a gate, a diffusion region, or a diffusion island contact provided in the diffusion region. And a storage step of storing the processing of each step and the processing result for each step, so that the compaction step inside the diffusion island satisfies the design rule from the square located closest to the scanning start side among the plurality of squares. In the step of sequentially compacting in the scanning start direction, and when the scan line is located in the square of the diffusion island and a design rule error occurs between the square where the scan line is located and the wiring around the diffusion island,
Based on the processing saved in the storage step and the processing result, the storage step is traced back to the point in time at which the design rule error is eliminated by enlarging the square area formed by the diffusion region connected to the power supply wiring, and Preferably, the method further includes a step of moving the same square in which the scan line is scanned and the other square in the diffusion island located on the opposite side to the scanning start side by the same distance in the opposite scanning start direction.

As described above, when a design rule error occurs between the rectangle inside the diffusion island where the scan line is located and the wiring around the diffusion island, the processing stored in the storage step and the processing result are used. Then, the storage step is traced back to the point in time at which the design rule error is eliminated by enlarging the area of the square formed by the diffusion region connected to the power supply wiring. Further, by moving the rectangle on which the scan line scanned at the retrospective point is located and the other rectangle on the diffusion island located on the anti-scan start side with respect to the rectangle by the same distance in the anti-scan start direction, the design rule error is reduced. To eliminate. At this time, the square is defined as the anti-scan start direction,
That is, when moving in the direction opposite to the compaction direction, the area of the square formed by the diffusion region connected to the power supply wiring is enlarged, so that the delay time of the transistor is not affected.

[0026]

DETAILED DESCRIPTION OF THE PREFERRED EMBODIMENTS First Embodiment An outline of a first embodiment of the present invention will be described below with reference to the drawings. FIG. 1 is a diagram comparing a compaction result according to the present invention with a compaction result according to a conventional method, wherein (a) is a diagram before compaction processing,
(B) is a diagram of a typical cell layout using a conventional compaction method, and (c) is a diagram of a cell layout using a compaction method according to the present invention. FIG.
In each of the squares 1A to 1D in which transistors, contacts, and the like are abstracted, each has a terminal 2 in the periphery of each square, and is connected by a wiring element 3 in which wiring is abstracted.

As shown in FIG. 1 (c), according to the compaction method according to the present invention, unnecessary bending of the wiring element 3 has been removed, and compared with the conventional compaction result shown in FIG. 1 (b). The compaction results in a smaller area. This is because unnecessary rerouting (= jog) of the wiring is prevented by simultaneously executing local rewiring at the time of compaction.

A feature of the present invention is that compaction is performed while local wiring is performed.

FIG. 2 is a diagram showing an outline of a compaction method according to the present invention, showing a state in which wiring connection and compaction are performed simultaneously. FIG. 2 (a)
As shown in the figure, in a region where the rectangles 1A and 1B are arranged, a spit which is a virtual line perpendicular to one side of the region (one side in the horizontal direction with respect to the drawing in the present embodiment; the same applies hereinafter). (= Skewers) 4A and 4B are introduced, and net targets 5A and 5B are set at the positions where the wires from the square 1A intersect on the spits 4A and 4B, respectively. The net target is a set of objects connected to the same potential, and the position of the net target is a target to which the front described below should proceed. The definition of the spit introduced here will be described later.

First, in FIG.
A scan line 6 that scans in the right direction from the left end of the area and that is parallel to A and 4B is set, and when the scan line 6 is moved to a position corresponding to the terminal 2A on the right side of the square 1A, it is the leading end point of the wiring. A front 7 is generated on the scan line 6. The basis of the present invention is that the front 7 on the scan line 6
Is advanced with the net target 5A as the target, and then advanced with the net target 5B as the next target. Note that the comprehensive line 8 is a boundary line indicating that the compaction processing has been completed in an area on the left side of the comprehensive line 8.

Next, as shown in FIG. 2B, the scan line 6 is scanned rightward, and the net target 5A targeted by the front 7 is above the terminal 2A. It is moved to the same vertical position as the target 5A. The locus drawn by the front 7 becomes the new wiring element 3a, and the comprehensive line 8 is updated so as to be adjacent to the right side of the wiring element 3a.

Next, as shown in FIG. 2C, when the scan line 6 scans to the left side of the rectangle 1B,
Is moved to the left until it touches the comprehensive line 8 to perform compaction. At this time, an area where the scan line 6 and the moved rectangle 1B overlap is referred to as a wiring prohibited area 9.

Next, as shown in FIG. 2D, when the scan line 6 scans to the right side of the rectangle 1B or when the front 7 starts to move perpendicularly to the scanning direction, the comprehensive line 8 is changed to a rectangle. The comprehensive line 8 is updated so as to be adjacent to the right side of 1B.

Next, as shown in FIG. 2E, the scan line 6 is scanned rightward, and the front target 7B of the next net target 5B is located below the upper side of the square 1B. Front 7 to Net Target 5
Move to the same horizontal position as B. The locus drawn by the front 7 becomes the new wiring element 3b, and the comprehensive line 8 is updated so as to be adjacent to the right side of the wiring element 3b.

It should be noted that the wiring method according to the present invention does not
The configuration is such that only the wiring is performed without the compaction process shown in FIG.

Hereinafter, a first embodiment of the present invention will be described in detail with reference to the drawings.

FIG. 3 is a block diagram showing an LSI design apparatus centered on a compaction apparatus for realizing the compaction method according to the first embodiment of the present invention. As shown in FIG. 3, the LSI design device includes a symbolic layout unit 11 that expresses a transistor, a contact, a wiring, or the like by a symbol or a line, and an input unit such as a design rule unit 12 for determining the pattern size and arrangement of the LSI. And a storage device 14 as a storage unit having a built-in output unit such as a graphic data unit 13 which is a compaction result.
4, a compaction device 15 as a cell compaction unit for generating a compaction result of the cell based on the stored information and outputting the compaction result to the graphic data unit 13, a computer 16 for performing data transfer or arithmetic processing, etc .; And a display device 17 for displaying the same. The compaction device according to the present invention includes a storage device 14 and a compaction device 15.

Hereinafter, a data structure used in the compaction method or the wiring method will be described.

(Data Structure) 1) Placement Target FIG. 4A is an example of a layout diagram which is an input of a compaction method or a wiring method, and FIG.
It is the figure which abstracted the layout figure shown to (a). FIG.
As shown in (a), the objects to be arranged are CMOS
Transistor 31A, transistor 31B, transistor 31C and transistor 31D, and contacts 32 including pins. The transistor 31A and the transistor 31B share an impurity diffusion region,
The transistor 31C and the transistor 31D share an impurity diffusion region. The pins indicate the positions of the contacts in another wiring layer connected to the contacts 32.

In FIG. 4B, the transistor 31
A, 31A representing the squares 33a, 33B
b, 33c, which are abstracted and similarly represent the transistors 31C, 31D.
33e and 33f are abstracted. Square 33C
Is an abstraction of the contact 32. The terminal 34 for connecting the wiring is located at the periphery of the square in the case of the square 33a representing a transistor, and is located at the center of the square in the case of the square 33C representing a contact. A rectangle 33a representing a transistor and a rectangle 33 representing a contact
C are connected to each other by a wiring element 3 representing a straight line portion.
5 and a wiring connection point 36 connecting the wiring elements 35 to each other. Note that the terminal 34 is also abstracted into a wiring connection point 36.

2) Zone Expression As shown in FIG. 5, the zone expression is a data expression indicating a division of an area in which a set of squares 33 is arranged. The region in which the set of the squares 33 is arranged is divided horizontally and vertically with respect to one side of the region, and H1, H2,
H3 and H4 are horizontal zones, and V1, V2, V3 and V4 are vertical zones. Each zone includes as a member a rectangle that occupies at least some of its place within the zone. For example, the horizontal zone H3 includes a square C, a square D, a square F, and a square J, and the horizontal zone H4 includes a square C, a square D, a square G, and a square K. The boundaries between the horizontal and vertical zones are provided at coordinates where the number of members is minimized. Taking the boundary between H3 and H4 of the horizontal zone as an example, when scanning in the direction from the horizontal zone H1 to the horizontal zone H4, the number of members of the horizontal zone H3 is four.
Since (C, D, F, J) is maximized and reduced to 2 (C, D) and again increased to 3 (C, D, K), the distance between the square 33 of J and the square 33 of K It can be seen that a boundary occurs.

3) Vertical Constraint Graph FIG. 6 is a graph showing the upper and lower adjacent relationship of the square 33 shown in FIG. Each vertex 51 of the graph corresponds to each square 33, and each branch 52 expresses a constraint that it is necessary to separate each square 33 by a minimum distance. The minimum interval is given as the weight of the branch 52.

4) Spits As shown in FIG. 7, one spit 61 is arranged in each horizontal zone. Spit 61 is square 3 in the horizontal zone
Reference numeral 3 denotes an imaginary line placed horizontally with respect to the boundary 63 of the horizontal zone at a position where the number of vertically penetrated parts is maximized. Further, a net target 62 defined below is provided at the intersection of the spit 61 and the wiring element 35 crossing the horizontal zone.

5) Net Target List As shown in FIG. 8, the net target 62 is a target for extending the wiring to the next horizontal zone during the wiring and compaction processing. The net targets 62 are generated at the following three types of positions.

(A) Terminal 33 of square 33 to be a wiring connection point
2A (b) Wiring branch point 62B serving as a wiring connection point (c) Intersection 62C between wiring element and spit The net target list is a set of net targets 62A, 62B, and 62C for each horizontal zone.

6) Scan Line As shown in FIG. 9, the scan line 81 is an imaginary line perpendicular to the scanning direction for scanning from the left end to the right end of the area where the square 33 is arranged. Scan line 8
A front 82 or a wiring prohibition area 83 is arranged on 1.

The fronts 82A and 82B have a data structure indicating the leading end of the wiring, and the front 82A in the horizontal direction is a wiring corresponding to the front 82A in a direction indicating the scanning start position side, that is, in the left direction in the present embodiment. Connection point 3
6 is generated on the scan line 81 at the position where the 6 exists. Also, a front 82B perpendicular to the scanning direction
Is generated on the terminal 34 or the wiring connection point 36 which is the wiring connection point. The wiring prohibited area 83 where the wiring element 35 cannot be laid is defined at a position where the scan line 81 and the square 33 intersect. The comprehensive line 84 is an imaginary line indicating a boundary between an area where wiring and compaction processing has been completed and an area where wiring and compaction processing have not been completed, and is defined for each wiring layer.

7) Scanning Point List As shown in FIG. 10, the scanning point 85 indicates a position to which a scan line moves when a scan line is moved in the horizontal direction. The scanning point list is a list in which the scanning points 85 are sorted in ascending order in the scanning direction, and includes the terminals 34 as the wiring connection points, the wiring connection points 36 as the wiring branch points, the left side of the rectangle 33 and the right side of the rectangle 33. . When the terminal 34, the left side of the square 33 and the right side of the square 33 are at the same coordinates, if the scanning is performed from the left end to the right end in FIG.
4. Right side of square 33, left side of square 33, and rightward terminal 3
Sort in the order of 4.

(Processing Flow) The processing flow of the compaction method will be described below with reference to the drawings. FIGS. 11 and 12 are flowcharts showing the processing procedure of the compaction method according to the first embodiment of the present invention.

First, the details of the initialization processing in step ST1 shown in FIG. 11 will be described with reference to FIG.

As shown in FIG. 12, first, at step ST
In 1a, an abstraction is performed in which a component including a transistor, a resistor, a capacitor, or a contact to be arranged is rectangular.

Next, in step ST1b, a net target is set at a wiring connection point serving as a terminal, a wiring connection point serving as a branch point of a wiring element, or an intersection of a wiring element and a spit located at the peripheral portion or the central portion of the square. After that, in step ST1c, adjacent relations between the net targets are obtained, and their connection information is obtained.

Next, after all the existing wirings are deleted in step ST1d, in step ST1e, the square to be arranged is positioned in the vertical direction.

Next, in step ST1f, the terminal 3
4. A scanning point where the wiring connection point 35 and the left end and the right end of the rectangle are arranged in the scanning order is obtained, and a scanning point list is created. Then, in step ST1g, the position of the scan line is initialized. For example, the scan line is moved to the leftmost end of the area where the rectangle is arranged, and the comprehensive line is initialized.

Next, as shown in FIG.
In step 2, each front on the scan line is moved in a direction to approach the net target.

Next, in step ST3, the fronts that can be connected to each other are merged, and a wiring process is performed by adding the corresponding wiring elements. Thereafter, in step ST4, when the scan line moves to the scanning point corresponding to the terminal, a new front is generated from this terminal in the direction in which the wiring is connected.

Next, in step ST5, when the scan line moves on the scanning point corresponding to the left side of the rectangle, the rectangle is left-justified. Further, in step ST6, when the scan line moves on the scanning point corresponding to the right side of the rectangle, the comprehensive line is updated so as to surround the rectangle.

Next, in step ST7, it is determined whether or not the scan line has moved to the right end of the entire area, and in step ST8, the scan line is moved to the next scanning point.

In the present embodiment, a method has been described in which all the rectangles are left-justified while moving the scan line to the right in accordance with the scanning point in order from the left end of the area. It goes without saying that it can be done.

Hereinafter, the processing contents of each step of the processing flow will be described in detail.

(ST1a) Abstraction of Placement Target (1) As described with reference to FIG. 4, for a component such as a transistor, a contact including a pin, a resistor and a capacitor, a rectangle 33, a terminal 34, a wiring element 35 Alternatively, it is abstracted by the wiring connection point 36.

(2) As described with reference to FIG. 5, a zone expression is obtained for a set of squares 33.

(3) As described with reference to FIG. 7, the spit 61 is provided at the representative coordinate point which is the coordinate including the maximum point of the rectangular set of each horizontal zone. The group of squares 33 to be arranged included in the horizontal zone is arranged on the spit 61 located at the center of the horizontal zone.

(4) As described with reference to FIG. 6, a vertical graph which is an upper and lower constraint graph is created.

(4-1) Initialize the vertical graph.

(4-2) The vertices 51 corresponding to each square are added to the vertical graph. Each vertex 51 of the vertical graph corresponds to a rectangle, and the weight of each vertex 51 is the vertical size of each rectangle.

(4-3) Each spit is searched, and among the squares located on the spit, a branch which is effective between the vertices corresponding to each of the vertices corresponding to each of the vertices adjacent to each other in the vertical direction. 52 is added.

(4-4) As shown in FIG. 13A, it is assumed that a power supply line is arranged above a transistor arrangement region and a ground line is arranged below the arrangement region. FIG. 13B shows a case where p-type transistors Ap, Bp, and Cp are arranged above the center of the region and n-type transistors An, Bn, and Cn are arranged below the center of the region. As shown, vertices corresponding to the upper end Sp of the region, the lower end Dn of the region, and the center separation parts Sn and Dp of the region are respectively added. Of the vertices of all graphs,
The branches 52 and the weights of the branches 52 are given to the vertices corresponding to the transistors in order to express the design rules of the upper end Sp serving as the source of the transistor, the lower end Dn serving as the drain of the transistor, and the center separating portions Sn and Dp. I do.

(4-5) Branch 5 coming from source Sp
Source S for each vertex Ap, Bp, Sn without
The branch 52 is provided from p, and the branch 52 is provided to the drain Dn from each of the vertices An, Bn, Cn, and Dp having no branch 52 that goes out of any of them.

(ST1b) Installation of Net Target As described with reference to FIG. 8, (1) a net target 6 serving as a wiring connection point at the position of a peripheral terminal on each square 33 in which transistors and the like are abstracted
Install 2A.

(2) A net target 62B serving as a wiring connection point is installed at the position of the wiring branch point.

(3) The net target 62C is set at the intersection of the horizontal wiring element 35 and the spit 61.

(ST1c) Extraction of Adjacency Relationship of Net Targets In each net target, an adjacency relationship between the net targets is obtained by searching for an existing wiring, and wiring connection information is created.

(ST1d) Deletion of Wiring All wirings connected before compaction are deleted.

(ST1e) Vertical arrangement of objects to be arranged (1) The minimum width between rectangles according to the number of wirings passing between the rectangles depending on the condition of the spits (interval between wirings in each wiring layer, wiring width , And the sum of the intervals between the wirings is obtained, and the maximum value thereof is obtained.) Is given as the weight of the branch between the vertices corresponding to each rectangle.

As described with reference to FIG. 13, the weights of the branches from the vertices corresponding to the source Sp and the drain Dn are given in the same manner as between the vertices corresponding to the square.

(2) The longest path length of the vertical graph is calculated to obtain the initial arrangement of the arrangement object. In the case of a rectangular transistor, p-type transistors are packed so as to be as close to the power supply line as possible, and n-type transistors are packed so as to be as close to the ground line as possible. A square consisting of pins or contacts is placed in the center of the placement area.

(ST1f) Installation of Scanning Points As described with reference to FIG. 10, a list of scanning points in which all terminals, wiring branch points, left sides of a rectangle or right sides of a rectangle are sorted in ascending order of horizontal coordinates is created. .

(ST1g) Initialization of Scan Line and Comprehensive Line A scan line comprehensive line is initialized at the left end of the arrangement area for each wiring layer.

(ST2) Movement toward the front net target Each movable rightward front on the scan line is moved in a direction approaching the target.

More specifically, for each right-facing front on a scan line, (1) If the net target aimed at by the front is a terminal on a square or an intersection on a spit, the vertical coordinate value yt is used as the target y Coordinates.

(2) A position yy at which the right front can be brought close to the target y coordinate is determined in consideration of the wiring prohibited area on the scan line, the wiring width, the design rule, and the like, and the movement candidate (front and destination yy values and To the list).

(3) If there is a possibility that the wires in the same layer may intersect due to the movement among the movement candidates, an error is notified.

(4) Among the remaining moving candidates, the candidates moving up the placement area are sorted so that the vertical coordinates are in descending order, and the candidates moving down the placement area are sorted in ascending vertical coordinate. Sort.

(5) According to the order of the sorted movement candidate list, front movement and associated wiring processing are performed by using the process movefrontr for the movement candidates.

Hereinafter, the operation of the process movefrontr will be described with reference to FIG.

<Process movefrontr (front, vertical coordinate y
y)> MF1) As shown in FIG. 14A, the wiring connection point which is the leading end of the wiring corresponding to the front 82 is defined as wjold.

MF2) As shown in FIG. 14B, a new wiring connection point wjnew is created at the y coordinate of the front 82 after the movement.

MF4) From wiring connection point wjold to wiring connection point w
Generate a vertical wiring element ws in jnew.

MF5) The wiring element ws is left-justified along the comprehensive line 84, and the comprehensive line 84 is updated.

(ST3) Merging of fronts As shown in FIG. 15, the processing connectiveflicted to a pair of adjacent right-facing fronts fr1 and fr2 in the same net
Use ronts to generate vertical wires that connect them. Note that a net refers to a set of objects to be connected to the same potential.

<Processing vertical fronts (front fr1, front fr2)> CV1) The wiring connection point corresponding to the front fr1 is defined as wj1,
The wiring connection point corresponding to the front fr2 is defined as wj2.

CV2) From the wiring connection point wj1 to the wiring connection point wj2
Is generated in the vertical direction.

CV3) The wiring element ws is left-justified along the comprehensive line 84, and the comprehensive line 84 is updated.

(ST4) If the scan line is located on a rectangular terminal, a front is generated in the direction of wiring from the terminal.

That is, the following processing is performed for all wiring directions connected to the terminal T.

(1) When the terminal T has a leftward wiring, (1-1) As shown in FIG. 16, a rightward front fr1 having the terminal T of the square 33 as a net target already exists on the scan line 81. When the above mentioned movefrontr
Is used to wire from the wiring connection point wj corresponding to the front fr1 to the terminal T which is a net target.

(1-2) As shown in FIG. 17 (a), if there is no rightward front facing the terminal T of the square 33 on the scan line, and the net target on the terminal T is N1, The wiring connection point wj0 is generated so as to be on the left of the terminal T and to have the same vertical coordinate as that of the terminal T.

A wiring element ws2 connecting the wiring connection point wj0 and the terminal T is generated.

A net target adjacent to the net target N1 in the right direction is N2.

As shown in FIG. 17B, after a new wiring connection point wj1 is generated at the same vertical coordinates as the net target N2 and at the same horizontal coordinates as the wiring connection point wj0,
Wiring element ws1 connecting wiring connection point wj0 and wiring connection point wj1
Generate

A right front fr2 is newly provided starting from the wiring connection point wj1, and the target of the front fr2 is a net target N2.

(2) When the right wiring is provided at the terminal T: As shown in FIG. 18, a right front fr1 is generated on the scan line. The wiring connection point where the front fr1 is located is the terminal T of the square 33.

The target next to the front fr1 is changed to the net target N2 adjacent to the terminal T in the right direction.

(3) If there is a wiring in the terminal T in a vertical direction, for example, a direction in which the vertical coordinate becomes smaller (= downward), a downward front fr1 is newly provided on the scan line. The target of the front fr1 is moved from the net target corresponding to the terminal T to the net target N1 adjacent below.

(3-1) As shown in FIG. 19A, the wiring connection point w which is the net target N1 on the square 33C
Wiring for connecting j1 and the terminal T of the square 33D is required, and the wiring connection point wj1 of the square 33C is connected to the square 33D.
If there is a front fr2 toward the net target on the terminal T, a wiring element ws1 connecting the terminal T and the wiring connection point wj1 is generated.

Update the comprehensive line 84.

The front fr1 and the front fr2 are deleted.

(3-2) As shown in FIG. 19B, the wiring connection point w which is the net target N1 on the square 33C
Wiring for connecting j1 and the terminal T of the square 33D is required, and the wiring connection point wj1 of the square 33C is connected to the square 33D.
If there is a front fr2 toward the net target on the terminal T, and a wiring connection point wj0, which is a wiring branch point, between the terminal T of the square 33D and the wiring connection point wj1 of the square 33C. A wiring element ws1 connecting T and the wiring connection point wj1 is generated.

Update the comprehensive line 84.

The front fr1 and the front fr2 are deleted.

The front fr3 is newly provided on the wiring connection point wj0.

(3-3) As shown in FIG. 20, the net target N1 is located on the right side of the terminal T of the square 33 and above the wiring connection point wj0, and there is no wiring penetrating the wiring connection point wj0 upward. If the net target N1 exists in the horizontal wiring element ws, a new wiring connection point wj2 is generated at the same horizontal coordinate as the terminal T and at the same vertical coordinate as the net target N1.

After generating an upward front fr2 toward the terminal T at the position of the wiring connection point wj2, a wiring element ws1 connecting the front fr1 and the front fr2 is generated. After the wiring element ws1 is left-justified along the comprehensive line 84, the comprehensive line 84 is updated.

The front fr1 and the front fr2 are deleted.

The right front fr3 is newly provided on the wiring connection point wj2.

(3-4) As shown in FIG.
When the net target does not exist on the right side of the terminal T and is at the end, a front fr2 toward the terminal T exists on the scan line, has the same vertical coordinates as the front fr2, and New wiring connection point w at the position of the same horizontal coordinate
Generate j2.

Generate a horizontal wiring element ws1 connecting the wiring connection point wj2 and the wiring connection point wj2 on the left horizontal extension of the front fr2.

A vertical wiring element ws2 connecting the terminal T and the wiring connection point wj2 is generated, left-justified along the comprehensive line 84, and the comprehensive line 84 is updated.

The front fr1 and the front fr2 are deleted.

(ST5) When the scan line has moved to the left end of the rectangle, the rectangle is left-justified in accordance with the comprehensive line 84, and a region where the left-justified rectangle intersects the scan line is set as a wiring prohibited region.

(ST6) When the scan line moves to the right end of the rectangle, the comprehensive line 84 is updated so that the rectangle is included on the left side of the comprehensive line 84. Next, the wiring prohibited area occupied by the rectangle on the scan line is deleted.

As described above, the compaction method according to the present embodiment has the following features. As shown in FIG. 22A, three MOS transistors 9
Let us consider a case where 1, 92, 93 and one contact 94 are placed in an arrangement area. Impurity diffusion region 91a
MOS transistor 91 comprising a gate and a gate electrode 91b
And MOS transistor 92 formed of impurity diffusion region 92a and gate electrode 92b share a part of impurity diffusion regions 91a and 92a adjacent to each other, and MOS transistor 93 formed of impurity diffusion region 93a and gate electrode 93b. It is assumed that the transistor 92 shares part of the impurity diffusion regions 93a and 92a adjacent to each other. As shown in FIG. 22 (b), in the compaction method according to the present invention, an uneven figure (= rectlinear) formed by sharing a part of a square is abstracted by a plurality of squares, and the abstraction is performed. Since the adjacent relation between the rectangles is held as connection information, the compaction can be performed in the vertical direction by sliding the impurity diffusion region 92a of the MOS transistor 92 and the impurity diffusion region 93a of the MOS transistor 93.

The compaction apparatus using the compaction method according to the present embodiment is the same as the compaction apparatus described in ST1.
To ST8.

Further, in the wiring method of the present invention, only the steps described in the above ST5 are omitted, and the wiring apparatus of the present invention includes means for realizing all the steps other than the steps described in the above ST5 from the compaction apparatus. .

(Second Embodiment) Hereinafter, a second embodiment of the present invention will be described with reference to the drawings.

The compaction method used in the present invention is different from the conventional compaction method in a strict sense as described above, and is a method of simultaneously executing the movement of the placement object and the detailed wiring. That is, in the compaction method, while moving a virtual line (scan line) perpendicular to one side of the placement area from one end of the placement area to the other end, the leading end point (front) of the wiring is extended, This is a method of packing the arrangement objects in the scan start direction.

The placement objects include wiring contacts,
A pin, a transistor diffusion region, or a metal line extraction contact on the transistor diffusion region is included. Each layout object is provided with terminals for wiring connection in a peripheral portion or inside of the layout object.

A set of a series of diffusion regions formed by a single transistor or a plurality of transistors sharing a diffusion region and objects arranged on the diffusion region is called a diffusion island. When considering the optimization of gate bending in which the middle of the gate electrode of the transistor is bent, left-justified movement and layout generation are performed so that the positional relationship between the placement objects included in the diffusion island can be considered at the same time. While taking into account the wiring of the wiring layer that passes above and is different from the diffusion island,
It is preferable to carry out all at once. For this reason, in the present embodiment, when the scan line reaches the right end of the arrangement object corresponding to the diffusion island, after performing the layout generation processing inside the diffusion island, the entire diffusion island is left-justified.

Hereinafter, the entire processing of compaction and layout generation and a layout generation method inside a diffusion island will be described.

(2.1) Overall Processing The outline of the present embodiment will be described with reference to FIGS. 2A to 2C, in which the left-justified movement of a rectangular placement object and the generation of wiring proceed simultaneously.
This will be described with reference to FIG.

First, as shown in FIG. 2 (a), the schematic wiring path is divided into net targets 5A and 5
B and an adjacent list of the net targets 5A and 5B. The net targets 5A and 5B are arranged at locations where the vertical positional relationship with the placement objects in the wiring connection points, wiring branching points, and wiring areas formed of terminals is to be shown. The leftmost boundary where the figure can be placed is called a comprehensive line 8.

The basic concept is that when the scan line 6 scans a new terminal, a new front 7 is provided on the scan line 6 so that the front 7 tracks the net target adjacent to the right. The movement of the front 7 has to be a wiring path.

The positions scanned by the scan line 6 are the right end and left end of the rectangle, the wiring connection points, and the wiring branch points.
The order of scanning these is determined by the positional relationship before compaction. The front 7 is provided on the scan line when the scan line 6 passes through the terminal.

Next, as shown in FIG. 2B, the scan line 6 is moved rightward, and at the same time, the front 7 is moved along the scan line 6 toward the net target 5A. As the front 7 moves, a vertical wiring is formed, and the covering line 8 is updated so as to cover the vertical wiring.

Next, as shown in FIG. 2C, when the scan line 6 scans the left end of the rectangle 1B, the rectangle 1B is moved to the left toward the comprehensive line 8. At this time,
When the rectangle 1B represents a part of the diffusion island, since the rectangle 1B is linked to another plurality of rectangles, the plurality of rectangles and the information on the wiring passing over the plurality of rectangles are transmitted to the diffusion island. After notifying the internal layout generating means and generating the layout inside the diffusion island first, all figures related to the diffusion island are left-justified. The left-justified rectangle is treated as an obstacle (wiring-prohibited area 9) for the wiring of the specified layer. That is, the front 7 of the layer designated as the wiring prohibited area 9 on the scan line 6 is
Can not jump and move.

Next, as shown in FIG. 2D, when the scan line 6 passes through the rectangle 1B, the covering line 8 is updated so as to cover the rectangle 1B. Then, FIG.
, The front 7 disappears when it reaches the net target 5B.

FIG. 23 shows an example of graphic information notified to the diffusion island internal layout generating means. In FIG. 23, 84 is a comprehensive line, 6 is a scan line, and fr1 is a front. 94 is a first MOS transistor having net targets N4, N5 and N6, and 92 is a second MOS transistor having net targets N8, N9 and N11. Reference numeral 101 denotes a diffusion island in which the first MOS transistor 94 and the second MOS transistor 95 share a diffusion region. N7, N10 and N12
Are net targets which are wiring connection points.

In this embodiment, a layout model is used in which a general wiring path can pass above the diffusion island 101 so that different wiring layers can pass above the transistor. For example, if it is assumed that a metal wiring is provided in a certain wiring layer, a metal wire lead-out contact from the diffusion region can be an obstacle to wiring, but a wiring layer of a different layer from the metal wire lead-out contact, for example, polysilicon Since the metal wiring and the diffusion region do not become obstacles, the rough wiring path of the metal wiring is determined by recognizing only the contact drawn from the diffusion region as an obstacle.

N1, N2, and N3, which are intersections on the boundary between the schematic wiring path and the placement object, are newly defined as net targets, and the diffusion island inside layout generation means for performing a detailed layout inside the diffusion island is used to generate the diffusion island 101. Notify graphic information.

The diffusion island internal layout generating means does not perform the actual wiring processing, but generates a wiring by moving the front in the compaction processing later so that the metal wiring and the polysilicon wiring can become obstacles. Return the list to the notification source that notified the graphic information.

Since the generated rectangular set has a fixed relative position, no subsequent movement is performed, but the front is moved and the comprehensive line is updated in accordance with the scanning order determined before compaction. Thus, the wiring can be laid at the position specified by the schematic wiring.

(Processing Flow) FIG. 24 is a flowchart showing a compaction method according to the second embodiment of the present invention. As compared with the processing flow of the first embodiment shown in FIG. 11, steps ST1 to ST8 are common, and steps ST101 to ST104 are provided in place of step ST5 for shifting the square to the left.

That is, when the left end of the square is found, (1) when the square is included in the diffusion island, and when the square is located at the left end of the diffusion island, (2) the square is included in the diffusion island In the case other than the above (1), and (3) when the square is not included in the diffusion island and is a single arrangement object that can perform a process such as movement, the process to be performed is switched depending on any of the cases. .

In the case of (1), a diffusion island generation step ST10
In step 4, a wiring area passing through the upper layer of the diffusion island is secured and a layout pattern inside the diffusion island is generated.

In the case of (2), no processing is performed.

In the case of (3), the rectangle is packed to the left as much as possible.

(2.2) Diffusion Island Inside Layout Generation Diffusion island inside layout generation is a compaction subsystem that is executed when a scan line moves to the right end of a square consisting of diffusion islands. Hereinafter, the function and processing procedure of the diffusion island internal layout generation means will be described.

FIGS. 25A to 25C show a layout method in a diffusion island internal layout generation step. In FIG. 25A, reference numeral 111 denotes a bent gate having a bent portion 140 of the MOS transistor, reference numeral 112 denotes a source of the MOS transistor, reference numeral 113 denotes a drain of the MOS transistor, and reference numeral 160 denotes a diffusion contact provided in a diffusion region of the MOS transistor.

(Function) (1) Generation of bent gate As shown in FIG. 25 (a), the inside of the diffusion island can move the placement object independently of the outside of the diffusion island, so that the gate of the MOS transistor can be moved. The bent gate 111 having a bent shape can be generated. Therefore, the capacitance of the drain 113 can be reduced by moving the bent portion 140.

(2) Control of Diffusion Area Graphic As shown in FIG. 25 (b), the inside of the diffusion island can change the placement object independently of the outside of the diffusion island. The width of the non-arranged diffusion region 104 in the gate length direction 151 can be shorter than that of the portion where the diffusion contact 160 is arranged. The size in the gate width direction is controlled so that the series resistance 130 does not exceed the upper limit. Thus, the area occupied by the transistor and the drain capacitance can be reduced.

(3) Securing Space for Overlying Diffusion Island Passing Wiring As shown in FIG. 25C, after passing through the upper layer of the diffusion island, an upper layer passing wiring 102 is provided after the internal layout is generated. Here, the space 103 for the upper layer passing wiring in the direction of the gate length 151 can be secured in advance.

(Data Structure) (1) Graphic Elements FIG. 26 shows graphic elements constituting a diffusion island in a table format. FIG. 27 shows an example of a diffusion island and a graphic element belonging to it. Reference numeral 160 denotes a diffusion contact as number 5 in FIG. 26, 161 denotes a diffusion left end as number 1 in FIG.
26 represents the right end of the diffusion as the number 2 in FIG. 26, 163 represents the left end of the gate as the number 3 in FIG. 26, and 164 represents the right end of the gate as the number 4 in FIG. The deformable gate and the diffusion region are regions in the gate length direction at the left end 163 of the gate and regions in the gate length direction at the right end 164 of the gate. The fixed-shaped diffusion contact 160 is represented as a square, and the net target, which is a wiring passing through the upper layer of the diffusion island, is represented by a rectangle 165 as a virtual graphic element.

(2) Design Rule As shown in FIG. 27, of the design rules, the design rule 109 considered in the present embodiment includes a minimum spacing 107, a minimum overlap 108, and a diffusion region in the bent gate. This is the minimum overlap 108 in the transistor width direction from the end to the bent portion.

(3) Placement Prohibited Area As shown in FIGS. 28A to 28C, the placement prohibited area 12
Reference numeral 1 denotes a graphic which is enlarged in the direction outside the graphic element 120 by the minimum space or the minimum design rule 109 for the purpose of preventing other graphic elements from entering. All design rules 1 for graphic element 120
09, the placement prohibited area 121 of the corresponding layer is created.

(4) Wall As shown in FIG. 29, a wall represents a boundary where graphic elements can be moved to the left. A wall 122 is created for each layer. The wall 122 is a concept common to the entire compaction process.

The processing procedure of the diffusion island internal layout generating means will be described below.

The following processing is repeated for a graphic element composed of transistors constituting a diffusion island, starting from the graphic element located at the left end of the arrangement area.

(STEP 1) Creation of a Graphic Element A graphic element shown in FIG. 26 is created for a figure constituting a transistor and a passing wiring. If there is a diffusion contact 160 on the diffusion region, the diffusion contact 16
A graphic element relating to 0 is created, and no graphic element is created for the left end and the right end of the diffusion area. The processing of (STEP2) to (STEP5) is repeated in order from the graphic element located at the left end of the arrangement area.

(STEP 2) Initialization of Wall First, the direction in which the graphic element is scanned is defined as the X-axis direction, and the direction perpendicular to the X-axis is defined as the Y-axis direction. When the diffusion region is shared with another transistor on the left side of the diffusion region, information of a portion having a common range in the Y-axis direction is inherited from the information of the wall 122 of the sharing partner transistor. In the case where the diffusion region is not shared between the non-common range and the left side, X located at the leftmost of the transistor graphic elements 120 is used.
Create an initial wall 122 with coordinates.

(STEP 3) Left-justify the graphic element 120 (Case 1) If the graphic element 120 has a fixed shape,
The distance between the graphic element 120 and the graphic element 120 is calculated, and the graphic element 120 is shifted to the left by that distance. For the graphic element 120 composed of a plurality of layers, a distance is obtained for each layer, and the graphic element is moved to the left by the smallest distance.

(Case 2) When the graphic element is at the left end or right end of the gate, for example, when generating a bent gate as shown in FIG. 29, (STEP 3.1) the bent portion 14 of the wall 122
By correcting 0, the bent portion shape of the gate is determined.

(STEP 3.2) From the minimum overlap at the left end or right end of the gate and the presence / absence and position of the diffusion contact 160 on the right side of the gate, an arrangement possible range 141 in the vertical direction in which the bent portion 140 can be arranged is determined.

(STEP 3.3) Source 1 for Gate 111
12. From the positional relationship between the left and right of the drain 113, the bent portion 140 is arranged at the position where the area on the drain 113 side is smallest within the range 141 where the bent portion can be arranged, and the shape of the left end of the gate is determined.

(STEP 3.4) The right end of the gate is a figure obtained by moving the left end of the gate to the right by a gate length 151.

(Case 3) In the case where the graphic element 120 is at the left end or the right end of the diffusion area, it will be described in the processing procedure for generating a diffusion graphic below.

(STEP 4) Creation of Placement Prohibited Area 121 The placement prohibited area 121 is created for the left-justified graphic element 120. In order to be able to create a bent gate,
Placement prohibited area 1 created for diffusion contact 160
21 are X in the placement prohibited area of the polysilicon layer.
Allows a 45 degree orientation to the axis.

(STEP 5) Update of the Wall 122 The wall 122 is updated so as to cover the placement prohibited area 121. Update is performed on the wall 122 of all layers.

Hereinafter, a processing procedure for generating a diffusion pattern inside a diffusion island will be described.

As shown in FIG. 30, the diffusion contact 16
The width a in the gate length direction 151 of the diffusion region where 0 is not arranged is reduced.

Here, the series resistance Rs (130) in the region where the diffusion contact 160 is not arranged is approximated as follows.

Rs = r × b / a where r is the sheet resistance of the diffusion region, a is the width of the diffusion region in the gate length direction, and b is the transistor width in the gate width direction of the diffusion region where no contact is arranged. I do.

The width a of the diffusion region and the overlap rule 108 are set so that the series resistance Rs does not exceed a predetermined upper limit.
The placement prohibited area 121 is created by using the large value of and the diffusion figure is generated.

FIGS. 31 (a) to 31 (h) show the entire processing flow of the diffusion island internal layout generation means using a specific example. As shown in FIG. 31A, input data includes a gate 111, a source 112, a drain 113, and a source 11
2 or a diffusion contact 160 provided on the drain 113, and net targets N1, N2, and N3, which are intersections on the boundary between the schematic wiring path and the placement object.

Next, in FIG. 31B, graphic elements are extracted from the input data. As shown in FIG. 31B, the gate left end 163 and the gate right end 164 are extracted from the gate 111, the diffusion left end 161 is extracted from the source 112, and the diffusion right end 161 is extracted from the drain 113.
62 is extracted. Further, a square 165 composed of a wiring passing through the upper layer of the diffusion island is extracted between the right end 164 of the gate and the diffusion contact 160.

Next, as shown in FIG. 31 (c), the wall 122 is initialized, and as shown in FIG. 31 (d), the wall 122 is updated along the placement prohibited area 121. Next, as shown in FIGS. 31 (e) and (f),
After deciding the position of the gate bending to the optimum position where the capacity of the drain can be reduced, as shown in FIG.
An area for the upper layer passing wiring passing through the upper layer of the diffusion island is secured, and the wall 122 is moved and updated from the right end of the upper layer passing wiring area to the right in accordance with the design rule. Thereafter, the diffusion contact 160 adjacent to the right side of the region for the upper-layer passing wiring is left-justified. FIG. 31H shows a state in which layout generation inside the diffusion island has been completed.

As described above, according to the present embodiment, since the diffusion sharing region in which each transistor shares the diffusion region is defined as a diffusion island, the inside of the diffusion island can be laid out independently. Even when the rules and the design rules outside the diffusion island are different, the layout inside the diffusion island can be surely optimized.

In addition, since the upper-layer wiring that passes through the upper layer of the diffusion island is also taken into consideration, more optimal compaction can be realized.

The compaction apparatus using the compaction method according to this embodiment is the same as the compaction apparatus described in ST1 described above.
To ST8 and ST101 to ST104.

Third Embodiment Hereinafter, a third embodiment according to the present invention will be described with reference to the drawings.

In this embodiment, after the generation of the layout in the diffusion island, the layout itself in the diffusion island naturally satisfies the design rule at that point. After that, when a design rule error occurs with the surrounding wiring, an object of the present invention is to correct the layout in the diffusion island and eliminate the design rule error.

FIGS. 32, 33 (a) and (b) and FIGS. 34 (a) and (b) show a compaction method according to the third embodiment. In FIG. 32, squares 33A and 33B are transistors, respectively, and the diffusion regions of the respective transistors are shared to form diffusion islands. N1 to N6 are net targets. The scanning point 85 is a position where the scan lines 6 are sequentially stopped. First diffusion region 114 represents a diffusion region connected to a power supply, and second diffusion region 115 represents a diffusion region not connected to a power supply. Only the covering line 84 of the polysilicon layer is shown for simplicity.

Now, assume that a layout inside the diffusion island is generated. As shown in FIG. 32, the scan line 6 starts scanning the left side of the square 33A. The compaction result is shown in FIG. It can be seen that the width of the entire diffusion island in the scanning direction is smaller than that of the diffusion island shown in FIG. The scan line 6 shown in FIG. 33A scans the net target N1. After generating the front fr1 on the net target N1, the front fr1 is vertically moved on the scan line 6 in a direction approaching the net target N2 to which the net target N1 is linked. The vertical movement of the front 6 is added as a wiring path, and the comprehensive line 84 is updated so as to include the wiring path.

Next, the scan line 6 shown in FIG. 33B scans the right side of the square 33A and the net target N2, and updates the comprehensive line 84 to include the square 33A. Further, the front fr1 is vertically moved on the scan line 6 in a direction approaching the net target N2. After adding the vertical movement of the front 6 as a new wiring route, the comprehensive line 84 is updated.

A scan line 6 shown in FIG. 34A scans the net target N3. A front is generated on the net target N3, and the net target N3 is generated.
3 tries to pull out the front towards the next linked net target N4, but the net target N1
The distance between the wiring route connecting the net target N2 and the net target N3 is too short, and a design rule error has occurred.

In order to eliminate this design rule error, as shown in FIG. 34B, the net target N3 and all the diffusion islands on the right side of the net target N3 are moved to the position where the design rule error is eliminated. The components are moved to the right by the same distance. As a result, it can be seen that the second diffusion region 115 is expanded and the design rule error is eliminated.

FIG. 35 shows another example using the compaction method according to the present embodiment. In FIG. 35, diffusion island 1
Numeral 01 includes net targets N1 to N4 and squares 33C and 33D made of contacts, respectively. The positions of these rectangles 33C and 33D are determined once when the layout inside the diffusion island 101 is generated. The comprehensive line 84 represents a comprehensive line of the metal wiring layer in this example.

In FIG. 35A, scan line 6
Is a state in which the left side of the rectangle 33D is being scanned, and the distance between the wiring path connecting the net target N2 and the net target N3 and the left side of the rectangle 33D is too short to cause a design rule error.

As shown in FIG. 35 (b), the rectangular 33D and the rectangular 3
The components of all the diffusion islands on the right side of 3D are moved to the right by the same distance.

As described above, according to the present embodiment, since the diffusion sharing region in which each transistor shares the diffusion region is defined as a diffusion island, the inside of the diffusion island can be independently laid out. Even when the rules and the design rules outside the diffusion island are different, the layout inside the diffusion island can be surely optimized.

In addition, since the upper layer passing wiring passing through the upper layer of the diffusion island is also taken into consideration, more optimal compaction can be realized.

Further, when a design rule error occurs inside the diffusion island, a step of eliminating the error is provided, so that a good compaction result close to a manual design can be obtained.

The compaction apparatus for realizing the compaction method according to the present embodiment has means for eliminating the above-described design rule error generated inside the diffusion island.

(Fourth Embodiment) Hereinafter, a compaction method according to a fourth embodiment of the present invention will be described with reference to the drawings.

Generally, in a CMOS circuit, the delay time of the circuit increases in proportion to the product of the resistance and the capacitance in the circuit. The parasitic capacitance of the transistor increases in proportion to the area of the diffusion region. Therefore, it is necessary to design the diffusion area of the transistor as small as possible. Exceptionally, the area of the diffusion region connected to the power supply does not affect the delay time.

In this embodiment, when a design rule error is detected during the compaction processing, the processing is traced back to a position where the design rule error is eliminated only by increasing the area of the diffusion region connected to the power supply. The design rule is moved by moving the square or wiring connection point being scanned at that time and all the diffusion island components to the right of the square or the wiring connection point by the same distance in the right direction. Try to meet.

FIGS. 34 (a) and (b) and FIG.
A method for eliminating a design rule error will be described with reference to FIGS. 37 (a) and (b) and FIGS. 37 (a) and 37 (b).

As shown in FIG. 34A, scan line 6 scans net target N3. The front is generated on the net target N3, and the front is drawn from the net target N3 toward the next linked net target N4. As described above, the net target N1 and the net target N
2 and the net target N3 are so short that a design rule error occurs.

In order to eliminate the design rule error, as shown in FIG. 34B, a net rule N3 and all the diffusion island components located on the right side of the net target N3 are subjected to a design rule error. If the second diffusion region 115 that is not connected to the power supply is moved to the right to the position where it disappears, the area of the second diffusion region 115 increases, and the delay time of the circuit increases.

Therefore, the process is traced back to the position where the design rule error is eliminated only by increasing the area of the diffusion region connected to the power supply without using the method shown in FIG. 34B.

In this embodiment, as shown in FIG. 36 (a), it goes back to the time when the scan line 6 scans the net target N1. Next, the net target N1 and the components of all the diffusion islands on the right side of the net target N3 are moved to the right by the same distance. The result is shown in FIG.

It can be seen that the movement makes the area of the first diffusion region 114 connected to the power supply larger than the original. However, this does not adversely affect the delay time.

Next, the scan line 6 shown in FIG. 36B scans the right side of the rectangle 33A and the net target N2, and updates the comprehensive line 84 so as to include the rectangle 33A. Thereafter, the front fr1 is vertically moved along the scan line 6 in a direction approaching the net target N2. After adding the vertical movement of the front 6 as a wiring route, the comprehensive line 84 is further updated.

Next, the scan line 6 shown in FIG. 37A scans the net target N3. After generating the front fr2 on the net target N3, the front fr2 is vertically moved along the scan line 6 in a direction approaching the net target N4 to which the net target N3 is linked. The vertical movement of the front 6 is newly added as a wiring route, and the comprehensive line 84 is updated.
Thereafter, the scan line 6 shown in FIG. 37B scans the net target N4.

As described above, according to the present embodiment, since the diffusion sharing region in which each transistor shares the diffusion region is defined as a diffusion island, the inside of the diffusion island can be independently laid out. Even when the rules and the design rules outside the diffusion island are different, the layout inside the diffusion island can be surely optimized.

Further, since the upper layer wiring which passes through the upper layer of the diffusion island is taken into consideration, more optimal compaction can be realized.

Further, when a design rule error occurs inside the diffusion island, the area of the first diffusion region 114 connected to the power supply is increased by the return process so that the delay time is not adversely affected. Since a design rule error can be eliminated, a good compaction result closer to manual design can be obtained.

The compaction apparatus for realizing the compaction method according to the present embodiment includes means for eliminating the above-described design rule error generated inside the diffusion island.

(Fifth Embodiment) Hereinafter, a schematic wiring method according to a fifth embodiment of the present invention will be described with reference to the drawings. The present embodiment is a schematic wiring method for obtaining a general wiring path abstracted by connecting net targets as shown in FIG.

When the compaction method described in the first or second embodiment is realized, only the arrangement of the transistors is given and there is no existing wiring, or the arrangement of the transistors is changed and the existing wiring is changed. This is effective when it is necessary to find a route again. A method of obtaining a schematic wiring path basically uses a scan line as in the compaction method of the first or second embodiment. In the course of scanning the scan line from the left end to the right end of the arrangement area where the arrangement object is arranged, the wiring that needs to cross the spit to the left and right on the spit, which is a virtual line perpendicular to the scanning direction, Generate a target.

FIGS. 38 and 39 are flowcharts showing a schematic wiring method according to the fifth embodiment of the present invention.

First, an initial state as shown in FIG. 4A is introduced. , Or a square 33 corresponding to the contact 32 and a terminal 34 on the square. Each terminal 34 is provided with a net identifier for identifying a set of terminals to be connected to the same potential. The already-routed wiring is represented by the wiring element 35 or the wiring connection point 36. In the case of obtaining the approximate wiring, all of the already-routed information is deleted and set to the initial state.

Next, in step ST201 shown in FIG. 38, a net target is set at each terminal 34 corresponding to the square terminal 34. The value of the net identifier of each net target is the value of the net identifier of the terminal at the same position.

Next, in step ST202, a scan line 81 as shown in FIG. 9 is provided at the left end of the arrangement area.
A point scanned by the scan line 81, that is, a scanning point list is obtained. The scanning point list is generated by sorting the positions of the terminals 34 and the positions of the spits 61 which are virtual virtual lines shown in FIG. 7 or 8 in order from the left end side of the arrangement area.

Next, in step ST203 and subsequent steps, the following processing is performed while sequentially moving the scan line 81 rightward in accordance with the position indicated by each scanning point in the scanning point list.

That is, in step ST204, when two fronts adjacent to each other on the scan line 81 are in the same direction and are the same layer and the same net, the two fronts are merged so that the two fronts are merged. After providing a pointer for linking the net target corresponding to the front, one of the two fronts is deleted from the scan line 81. The link of the net target is, for example, the net target 62 shown in FIG.
It is represented by a dashed double-headed arrow connecting A to the net target 62C.

Next, in step ST205 shown in FIG. 39, the position scanned by the scan line 81 is the terminal 3
If there is at least one front belonging to the same net as the terminal 34 on the scan line 81 at the position 4, if there is more than one front, it is closest to the terminal 34 among the plurality of fronts. Select Front F. Thereafter, the net target corresponding to the terminal 34 and the net target corresponding to the selected front F are linked.

Next, in step ST206, when the position scanned by the scan line 81 is the position of the terminal 34 and there is no front belonging to the same net as the terminal 34 on the scan line 81, the scan line A new front will be established on 81. Thereafter, the same net identifier as that of the terminal 34 is given to the front, and the front and the net target on the terminal 34 are associated with each other.

In step ST207 or ST208 shown in FIG. 38, if scan line 81 is located at spit 61, the following operation is performed on net target NT on spit 61.

That is, in step ST207, when the net to which the net target belongs is N and there is no front belonging to the net N on the scan line 81, the front of the net N is newly established on the scan line 81. Then, the same net identifier as that of the terminal 34 is given to the front, and the front and the net target on the terminal 34 are associated with each other.

In step ST208, when there is a front belonging to the net N on the scan line 81,
Net target and spit 61 corresponding to the front
An operation of linking the above net target NT is performed.

Next, in step ST209 shown in FIG. 39, when the front of the net N exists on the scan line 81 and the net target belonging to the net N does not exist on the spit 61, the right side of the spit ,
A net target belonging to the net N is searched, and if a net target is found, the front F is moved along the scan line 81 so as to approach a vertical coordinate position indicating a position perpendicular to the scan direction of the net target position. . When the net target is not found, the front target F is newly established with the front target F by moving the net target NT at the same vertical coordinate position as the front F onto the spit 61 without moving the vertical coordinate position of the front F. Correlate with the net target NT.

Next, step S as a cross wiring optimization step
At T210, a wiring intersection position where a plurality of wirings cross each other in the same wiring layer (= the same layer) is optimized. As a specific operation, a switching operation for changing the order of the net targets, or a position where a wiring layer and another wiring layer different from the wiring layer are connected, for example, a position of a layer change point which is a position indicating a contact is moved A moving operation that causes the movement is considered. These operations are optimized by minimizing the value of a certain evaluation function Fc using a repetitive improvement method such as a simulated annealing method or a greedy method. The following evaluation function Fc is used as an optimization evaluation index used in the iterative improvement method.

(Evaluation Function Fc) The spit S has a value obtained by calculating the congestion degree Ds of the arrangement area in the same layer from the number of squares of the same layer and the number of net targets existing in the spit. However, if there is an intersection of wiring in the area adjacent to the right side of the spit, it is necessary to generate a contact to eliminate the intersection of the wiring. Therefore, the increase in the degree of wiring congestion due to the occurrence of the contact is calculated. , And the congestion degree Ds. The following value Fc is used as an evaluation function at the time of improvement by rewiring.

Fc = Max (Ds) (1)

FIGS. 40 (a) and 40 (b) show the procedure of a net target exchange operation in the general wiring method according to the present embodiment. In FIG. 40A, the spits 61
There are net targets 62D and 62E on A, and there are net targets 62F and 62G on Spit 61B,
There are net targets 62H and 62I on the spit 61C. As shown in FIG. 40A, in the left area of the spit 61B, the wiring connecting the net target 62D and the net target 62G and the net target 6
An intersection occurs between the wiring connecting 2E and the net target 62F. On the other hand, as shown in FIG. 40 (b), when the net target 62F and the net target 62G on the spit 61B are exchanged, the wiring connecting the net target 62G and the net target 62I is located in the right area of the spit 61B. An intersection occurs between the wiring connecting the net target 62F and the net target 62H. In this case, which one of (a) and (b) is selected depends on the wiring congestion on the right or left side of the spit 61B. That is, it is preferable to provide a wiring intersection at a place where the congestion degree Ds is as low as possible. It is clear that such an evaluation of optimality can be realized by using equation (1).

FIGS. 41 (a) and 41 (b) show the procedure for moving the layer change point in the general wiring method according to the present embodiment. In FIG. 41A, a net target 62D is located on a spit 61A, a contact 32 serving as a layer change point for changing a wiring layer is located on a spit 61B, and a net target 62E is located on a spit 61C. The metal wiring 201 connected to the net target 62D and the metal wiring connecting the net target 62D and the contact 32 are provided in the left area of the spit 61A. The contact 32 and the net target 62E are connected to the metal wiring 201 by a polysilicon wiring 202 having a different wiring layer. On the other hand, as shown in FIG. 41 (b), by moving the position of the contact 32 on the spit 61B to the left of the spit 61B, the metal wiring 201 connected to the contact 32 in the left area of the spit 61A is changed. Provided. The contact 32 and the net target 62D are connected by a polysilicon wiring 202 having a different wiring layer from that of the metal wiring 201.
2D and net target 62E are also polysilicon wiring 2.
02 will be connected. As a result, the wiring layer is changed between the spits 61A and 61B, so that the congestion degree Ds in the spits 61A and 61B changes. Therefore, it is clear that the evaluation of the optimality can be realized by using the equation (1).

Next, a step ST21 as a wiring bypass step
In 1, in the case where the intersection of the wirings in the same wiring layer remains, a change is made so that a contact is provided in one of the intersecting wiring paths so as to bypass a wiring layer different from the wiring layer.

As described above, according to the present embodiment, a scan line which is arranged in parallel to the spits in the arrangement area and has a front which is a front end point on a line where a wiring element is to be arranged scans a new net target. Then, a new front is provided on the scan line, the front moves so as to trace toward a net target adjacent to the right side, and the locus of the movement of the front becomes a wiring path. Thus, even when the placement object is changed and rewiring is performed, bending of the wiring can be suppressed as much as possible, so that the area of the wiring can be minimized.

The schematic wiring device using the general wiring method according to the present embodiment includes the above described ST201 to ST2.
There are means for realizing each of the eleven steps.

[0231]

According to the wiring method of the present invention, not only are components and wiring abstracted, but also a general wiring path for connecting components to each other in an arrangement area where a plurality of rectangles made of the abstracted components are arranged. Is abstracted into a net target, which is a set of wiring connection points to be set to the same potential, and an adjacent relationship between the net targets, the schematic wiring path connecting the components is once deleted. Then, by scanning the scan line toward the net target and moving the front on the scan line on the scan line so as to approach the net target, the trajectory of the front drawn as a wiring path connects the squares Since a new wiring path is generated, unnecessary bending of the wiring can be reduced, and the area of the wiring can be reduced.

According to the compaction method of the present invention, not only are components and wiring abstracted, but also in a layout area where a plurality of rectangles composed of the abstracted components are arranged, the general wiring paths connecting the components are the same. In order to abstract a net target, which is a set of wiring connection points to be set to a potential, and an adjacent relationship between the net targets, a schematic wiring path connecting the components is temporarily deleted. afterwards,
Wiring that connects squares by using the trajectory of the front drawn by moving the front of the scan line on the scan line so as to approach the net target while scanning the scan line toward the net target, as a wiring path Since the route is newly generated, the square can be compacted reliably while reducing unnecessary wiring bending. Even if the arrangement of components is changed, by performing rewiring, it is possible to suppress bending of the wiring as much as possible, and it is also possible to effectively compact wiring having different thicknesses.

[0233] In the compaction method of the present invention, the wiring and the compaction step are performed by sequentially arranging the position of the wiring connection point, the side parallel to the scan line in the rectangle, and the position of the other side facing the one side in the net target. A first step of creating a scanning point list that determines the order in which the lines are scanned; and moving the scan line in a direction perpendicular to the scan line according to the scanning point list and moving the front on the scan line closer to the net target. Move on the scan line and compact the straight line connecting the wiring connection point to the destination front in the scan start direction, which is the position where the scan line first started scanning,
A second step of adding a compacted straight line as a wiring element, and, when two fronts on a scan line are in the same direction, merging the two fronts and connecting the fronts to each other. A third step of compacting the obtained straight line in the scanning start direction and adding the compacted straight line as a wiring element; and, when the scan line is located at a wiring connection point,
A fourth step of newly arranging a front at the wiring connection point, adding a wiring element toward the net target targeted by the front, and then erasing the front that no longer needs to extend the wiring element; If the fifth step is performed in which the rectangle is located on the side opposite to the scanning start side and the rectangle is a wiring prohibited area, the wiring and compaction processing between a plurality of net targets can be reliably performed.

In the compaction method of the present invention, when the wiring and compaction steps include the first to fifth steps, the scan line is located on the side on the scanning start side of the rectangle, and the rectangle defines the diffusion region of the transistor. Included in the diffusion island shown, and when the side on the scanning start side that is more square than the other components of the diffusion island is located closest to the scanning start side, the inside of the diffusion island that generates a layout pattern inside the diffusion island When the method further includes a layout generation step and a diffusion island internal compaction step of compacting a layout pattern inside the diffusion island in the search start direction, the layout generation processing inside the diffusion island and the entire compaction processing are hierarchically handled. It can handle complicated layouts such as bending the gate of the transistor and optimizing the position of the diffusion contact. It is possible, it is possible to obtain good compaction results close to the manual design.

[0235] In the compaction method of the present invention, the diffusion island has a plurality of squares composed of a gate, a diffusion region, or a diffusion island contact provided in the diffusion region. A step of sequentially performing compaction in the scanning start direction so as to satisfy the design rule from a rectangle located closest to the scanning start side of a plurality of rectangles, and a rectangle in which scan lines are located in a diffusion island square and the scan line is located In the case where a design rule error occurs between the wiring and the wiring around the diffusion island, a rectangle where the scan line is located and another in the diffusion island located on the anti-scanning start side of the rectangle so as to eliminate the design rule error. Moving the same line in the anti-scan start direction by the same distance as When a design rule error occurs between the wiring and the peripheral wiring, a rectangle in which the scan line is located and another rectangle in the diffusion island located on the anti-scanning start side of the rectangle so as to eliminate the design rule error. Are moved in the anti-scanning start direction, so that a design rule error does not occur, so that compaction inside the diffusion island can be reliably performed.

In the compaction method of the present invention, the diffusion island has, as its constituent elements, a plurality of squares each consisting of a gate, a diffusion region, or a diffusion island contact provided in the diffusion region. And a storage step of storing the processing of each step and the processing result for each step, so that the compaction step inside the diffusion island satisfies the design rule from the square located closest to the scanning start side among the plurality of squares. In the step of sequentially compacting in the scanning start direction, and when the scan line is located in the square of the diffusion island and a design rule error occurs between the square where the scan line is located and the wiring around the diffusion island,
Based on the processing saved in the storage step and the processing result, the storage step is traced back to the point in time at which the design rule error is eliminated by enlarging the square area formed by the diffusion region connected to the power supply wiring, and Moving the same line in the anti-scan start direction by the same distance in the anti-scan start direction between the square where the scan line scanned is located and the other square in the diffusion island located on the anti-scan start side with respect to the square. Since the design rule error is eliminated by enlarging the square area formed of the diffusion region to be formed, the delay time of the transistor is not increased, so that the layout can be optimized more reliably.

[Brief description of the drawings]

FIG. 1 is a diagram comparing a compaction result according to the present invention with a compaction result according to a conventional method,
(A) is a diagram before compaction processing, (b) is a diagram of a typical cell layout by a conventional compaction method, and (c) is a diagram of a cell layout by a compaction method according to the present invention.

2A and 2B schematically show a compaction method and a wiring method using scan lines and a front according to the first or second embodiment of the present invention, FIG. 2A is a diagram showing generation of a front, and FIG. ) Is a diagram in which the front moves on the scan line, (c) is a diagram in which the rectangle is compacted, (d) is a diagram in which the comprehensive line is updated, and (e) is a diagram in which the front moves. It is a figure which shows how a wiring is laid.

FIG. 3 is a block diagram showing an LSI design apparatus centered on a compaction apparatus according to the first embodiment of the present invention.

FIG. 4A is a layout diagram that is an input of a compaction method according to the first embodiment of the present invention or a schematic wiring method according to the fifth embodiment; (B) is a diagram which abstracts the layout diagram shown in (a).

FIG. 5 is a diagram showing a zone expression of an abstraction step in the compaction method and the wiring method according to the first embodiment of the present invention.

FIG. 6 is a diagram showing an upper and lower constraint graph of an abstraction step in the compaction method and the wiring method according to the first embodiment of the present invention.

FIG. 7 is a diagram showing virtual lines (= spits) in an abstraction step in the compaction method according to the first embodiment of the present invention or the schematic wiring method according to the fifth embodiment.

FIG. 8 is a diagram illustrating a net target in an abstraction step in the compaction method according to the first embodiment of the present invention or the schematic wiring method according to the fifth embodiment.

FIG. 9 is a diagram showing scan lines in a compaction method according to the first embodiment of the present invention or a schematic wiring method according to a fifth embodiment.

FIG. 10 is a diagram showing a scanning point list in the compaction method or the wiring method according to the first embodiment of the present invention.

FIG. 11 is a flowchart of a compaction method according to the first embodiment of the present invention.

FIG. 12 is a flowchart of an initialization process of the compaction method according to the first embodiment of the present invention.

FIGS. 13A and 13B show a constraint graph including a peripheral portion of an arrangement region in the compaction method or the wiring method according to the first embodiment of the present invention, and FIG. 13A is a diagram showing a transistor and an arrangement region of the transistor; (b) is a diagram showing a vertical constraint graph, and (c) is a diagram showing a left / right constraint graph.

14A and 14B are diagrams illustrating generation of vertical wiring elements in the compaction method or the wiring method according to the first embodiment of the present invention, wherein FIG.
(B) is a diagram after the wiring processing.

FIG. 15 is a diagram illustrating generation of a vertical wiring element by merging fronts in the compaction method or the wiring method according to the first embodiment of the present invention.

FIG. 16 is a diagram illustrating generation of horizontal wiring elements in the compaction method and the wiring method according to the first embodiment of the present invention.

FIGS. 17A and 17B are diagrams showing the generation of horizontal wiring elements when there is no front pointing to a net target on a scan line in the compaction method and the wiring method according to the first embodiment of the present invention, and FIG. FIG. 3B is a diagram before the wiring process, and FIG. 3B is a diagram after the wiring process.

FIG. 18 is a diagram illustrating generation of horizontal wiring elements when wiring extending in the scanning direction is laid on a terminal on a scan line in the compaction method and the wiring method according to the first embodiment of the present invention.

FIG. 19 is a diagram for generating a vertical wiring element when laying a wiring extending perpendicularly to a scanning direction on a terminal on a scan line in the compaction method or the wiring method according to the first embodiment of the present invention. (A) is a diagram showing a connection between terminals, and (b) is a diagram showing a connection in which a wiring connection point is interposed between the terminals.

FIG. 20 is a diagram for generating a vertical wiring element when a net target exists in a scanning direction ahead of a terminal on a scan line in the compaction method or the wiring method according to the first embodiment of the present invention. .

FIG. 21 is a diagram illustrating generation of a vertical wiring element in the case where no net target exists in a scanning direction prior to a terminal on a scan line in the compaction method or the wiring method according to the first embodiment of the present invention. .

FIG. 22 is a diagram in which in a compaction method or a wiring method according to the first embodiment of the present invention, a plurality of MOS transistors abstracts a concavo-convex pattern formed by sharing an impurity diffusion region with a plurality of squares to realize compaction; (A) is a diagram before compaction processing,
(B) is a diagram after compaction processing.

FIG. 23 is a diagram showing input data of a diffusion island internal layout generating means in the compaction method according to the second embodiment of the present invention.

FIG. 24 is a flowchart of a compaction method according to the second embodiment of the present invention.

FIGS. 25A to 25C are diagrams showing a method for generating an internal layout of a diffusion island in a compaction method according to the second embodiment of the present invention.

FIG. 26 is a diagram showing graphic elements of a compaction method according to the second embodiment of the present invention in a table format.

FIG. 27 is a diagram showing the relationship between graphic elements and design rules in a compaction method according to the second embodiment of the present invention.

FIG. 28 is a diagram illustrating an arrangement prohibited area in the compaction method according to the second embodiment of the present invention.

FIG. 29 is a diagram illustrating a method of generating a bent gate in a compaction method according to the second embodiment of the present invention.

FIG. 30 is a diagram showing a method for optimizing a diffusion region in a compaction method according to the second embodiment of the present invention.

FIGS. 31 (a) to (h) are diagrams showing a diffusion figure generation method of a diffusion island internal layout generation means in a compaction method according to a second embodiment of the present invention.

FIG. 32 is a diagram showing a design rule error elimination method in the compaction method according to the third embodiment of the present invention in the order of steps.

FIGS. 33 (a) and (b) are diagrams showing a design rule error elimination method in a compaction method according to a third embodiment of the present invention in the order of steps.

FIGS. 34A and 34B are diagrams showing a design rule error elimination method in the compaction method according to the third or fourth embodiment of the present invention in the order of steps.

FIGS. 35 (a) and (b) are diagrams showing a design rule error elimination method in a compaction method according to a third embodiment of the present invention in the order of steps.

FIGS. 36 (a) and (b) are diagrams showing a design rule error elimination method in a compaction method according to a fourth embodiment of the present invention in the order of steps.

FIGS. 37 (a) and (b) are diagrams showing a design rule error elimination method in a compaction method according to a fourth embodiment of the present invention in the order of steps.

FIG. 38 is a flowchart illustrating a schematic wiring method according to a fifth embodiment of the present invention.

FIG. 39 is a flowchart illustrating a schematic wiring method according to a fifth embodiment of the present invention.

FIG. 40 is a diagram showing a procedure of a net target replacement operation in the schematic wiring method according to the fifth embodiment of the present invention.

FIG. 41 is a view showing a procedure of an operation of moving a layer change point in the schematic wiring method according to the fifth embodiment of the present invention.

[Explanation of symbols]

 Reference Signs List 1A rectangle 1B rectangle 1C rectangle 1D rectangle 2A terminal 3 wiring element 3a wiring element 3b wiring element 4A Spit 4B Spit 5A net target 5B net target 6 scan line 7 front 8 inclusive line 9 wiring prohibited area 11 symbolic layout section 12 design rule section 12 Graphic data part 14 Storage device 15 Compaction device 16 Computer 17 Display device 31A Transistor 31B Transistor 31C Transistor 31D Transistor 32 Contact 33 Square 33A Transistor group 33a Rectangular 33b Transformer 33c Rectangular 33B Transformer 33d Rectangular 33d 33C A square representing a contact 33D A rectangle representing a contact 34 Terminal 35 Wiring element 36 Wiring connection Point 51 Apex 52 Branch 61 Spit 61A Spit 61B Spit 61C Spit 62 Net Target 62A Terminal (Net Target) 62B Wiring Branch (Net Target) 62C Intersection (Net Target) 62D Net Target 62E Net Target 62F Net Target 62G Net Target 63 Horizontal Zone boundary 81 Scan line 82 Front 82A Horizontal front 82B Vertical front 83 Wiring prohibited area 84 Inclusion line 85 Scanning point 91 MOS transistor 91a Impurity diffusion area 91b Gate electrode 92 MOS transistor 92a Impurity diffusion area 92b Gate electrode 93 MOS Transistor 93a Impurity diffusion region 93b Gate electrode 94 First MOS transistor 95 second MOS transistor Sp source Dn drain Sn median separator Dp median separator Ap p-type transistor Bp p-type transistor Cp p-type transistor An n-type transistor Bn n-type transistor Cn n-type transistor wjold Wiring connection point wjnew Wiring connection point wj0 wiring connection point wj1 wiring connection point wj2 wiring connection point ws wiring element ws1 wiring element ws2 wiring element fr front fr1 front fr2 front fr3 front N1 net target N2 net target N3 net target N4 net target N5 net target N6 net target N6 net target N8 Net target N9 Net target N10 Net target N11 Net target N12 Net target T terminal 101 Diffusion island 102 Upper layer wiring 103 Upper layer wiring space 104 Diffusion region 107 Minimum spacing 108 Minimum overlap 109 Design rule 111 Gate (bent gate) 112 Source 113 Drain 114 First diffusion region 115 Second diffusion region 120 Graphic element 121 Placement prohibited area 122 Wall 130 Series resistor 140 Bend 141 Placeable range 150 Transistor width 151 Gate length 160 Diffusion contact 161 Diffusion left end 162 Diffusion right end 163 Gate left end 164 Gate right end 165 Square corresponding to upper layer wiring 201 Metal wiring 202 Polysilicon wiring

──────────────────────────────────────────────────続 き Continuation of the front page (56) References JP-A-8-222636 (JP, A) JP-A-3-108738 (JP, A) JP-A-5-36830 (JP, A) 318642 (JP, A) (58) Fields investigated (Int. Cl. ⁷ , DB name) H01L 21 / 82,21 / 822 H01L 27 / 04,27 / 118

Claims (6)

(57) [Claims] Abstract : A component is abstracted into a rectangle having terminals.
And the terminal and a wiring connecting the terminals to each other
A first abstraction step of abstraction to the connection point and the wire element, in the arrangement region in which the square is plural arranged, said unit
The schematic wiring paths connecting the parts must be connected at the same potential.
A net target that is a set of line connection points and the net target
Second abstraction process for abstracting the adjacent relation between the get
And the squares according to the net target and the adjacent relation
And a wiring step of connecting a scan line to the net target.
While scanning toward the
To move the front panel closer to the net target.
The drawing drawn by moving on the line
A wiring method characterized by using a trajectory of a front as a wiring route.
Law. 2. A method component, the abstract square having a pin, a first abstraction step of abstracting the wiring that connects the terminals and the terminals to each other in the wiring connection point and the wiring element, the in arrangement depositing area of the square is a plurality arranged, the rough wiring path connecting the components to each other, to connect the same potential distribution
A second abstraction step of abstracting a net target, which is a set of line connection points, and an adjacency relationship between the net targets; and a wiring and compaction step of connecting and compacting the rectangles by the net target and the adjacency relation. e Bei the door, the wiring and compaction step, the scanning line while scanning toward the net target, the scan line above so as to approach the full Ronto on the scan lines in the net <br/> preparative target a step of a wiring path trajectory of the front drawn by causing moved, the scan line is located to the side of the scanning start side of the square
The rectangular shape in the scanning start direction.
Compaction method characterized by a step of ® down. 3. The wiring and compaction step, wherein, in the net target, a position of the wiring connection point, a side of the rectangle parallel to the scan line and a position of another side facing the one side are arranged in order. a step of creating a scanning point list scan line to determine the order in which to scan, the scan line is moved to the scan lines and the direction perpendicular accordance with the scanning point list, the front of the front Symbol nets on the scan line Moving on the scan line so as to approach the target, and compacting a straight line connecting the front from the wiring connection point to the destination in the scan start direction, which is the position where the scan line first started scanning; The straight line thus obtained is used as a wiring element. And adding a straight line generated by merging the two fronts and connecting the fronts to each other when the two fronts on the scan line are in the same direction, in the scanning start direction. Compacting and adding the compacted straight line as a wiring element; and when the scan line is located at the wiring connection point, newly providing a front at the wiring connection point and setting the front as a target. After adding the wiring element toward the net target, erasing the front where it is no longer necessary to extend the wiring element, and when the scan line is located on the side of the square on the anti- scan start side, 3. The compaction method according to claim 2, further comprising the step of: setting a square as a wiring prohibited area. Wherein said wiring and compaction step is located before Symbol scan start side edges of the scan line is the square, the square is included in the diffusion islands showing the diffusion regions of the transistors, and, the diffusion Island A diffusion island internal layout generating step of generating a layout pattern inside the diffusion island when the side on the scanning start side of the rectangle is positioned closest to the scanning start side than the other constituent elements; 4. A compaction method according to claim 3 , further comprising the step of compacting the layout pattern inside the diffusion island in the search start direction. Wherein said diffusion island, as its component, the gate has a plurality of square consisting of diffusion island contacts provided to the diffusion region or the diffusion region, the diffusion island internal compaction step, the A step of sequentially compacting in the scanning start direction so as to satisfy a design rule from a rectangle located closest to the scanning start side among a plurality of rectangles, and wherein the scan line is located in a square of the diffusion island and the scan line is When a design rule error occurs between the located square and the wiring around the diffusion island, the scan line is located so that the design rule error is eliminated, and the scanning start side is located on the opposite side of the square. claims, characterized in that the other square of the diffusion island comprises a step of moving the counter-scanning start direction by the same distance which is located Compaction method according to. 6. The diffusion island has, as its constituent elements, a plurality of squares each composed of a gate, a diffusion region, or a diffusion island contact provided in the diffusion region. The method includes a storing step of storing the processing of each step and the processing result for each step, wherein the diffusion island internal compaction step satisfies a design rule from a rectangle located closest to the scanning start side among the plurality of rectangles. The step of sequentially compacting in the scanning start direction, wherein the scan line is located in the square of the diffusion island, and a design rule error occurs between the rectangle in which the scan line is located and the wiring around the diffusion island. Is generated, based on the processing stored in the storing step and the processing result, the diffusion region connected to the power supply wiring. The storage step is traced back to a point in time when the design rule error is eliminated by enlarging the area of the rectangle, and the scan line scanned at the traced point in time is located on the anti-scan start side with respect to the rectangle and the rectangle. wherein the weight of the other square of the diffusion island located in the counter-scanning start direction and degree Engineering moving by the same distance
The compaction method according to claim 4 .