CN111611762A

CN111611762A - Method, system and storage medium for optimizing integrated circuit with hierarchical structure

Info

Publication number: CN111611762A
Application number: CN202010456616.5A
Authority: CN
Inventors: 黄国勇; 张岩
Original assignee: Guowei Group Shenzhen Co ltd
Current assignee: Shenzhen Guomicrochip Technology Co ltd
Priority date: 2020-05-26
Filing date: 2020-05-26
Publication date: 2020-09-01

Abstract

The invention discloses an optimization method, a system and a storage medium for an integrated circuit with a hierarchical structure, wherein the hierarchical structure of the integrated circuit comprises a module positioned at the top layer and a plurality of modules positioned at other layers, except for the module positioned at the lowest layer, each module comprises at least one lower-layer module positioned at the next layer, and the method comprises the following steps: selecting a module to be optimized and a lower module of the modules; and performing time sequence analysis and optimization on boundary paths among the lower-layer modules, so that circuits in the modules meet time sequence constraint conditions of the modules. By adopting the technical scheme of the invention, the calculation efficiency of the whole optimization process can be improved.

Description

Method, system and storage medium for optimizing integrated circuit with hierarchical structure

Technical Field

The present invention relates to the field of integrated circuit design, and in particular, to a method and a system for optimizing an integrated circuit having a hierarchical structure, and a storage medium.

Background

Automatic place and route of integrated circuits involves a number of steps. A typical automated place and route tool first divides the design netlist into a top-level design and a number of module-level designs and outputs the module-level circuits in DEF format. The timing constraint conditions of the module-level circuit are obtained by planning the timing constraint condition budget of the whole chip circuit, and comprise input and output timing constraint conditions of the module and timing constraint conditions inside the module, the timing constraint conditions are described by an SDF (synchronous Design) format, and the input and output timing constraint conditions of the module comprise a maximum input time constraint, a minimum input time constraint, a maximum output time constraint and a minimum output time constraint. And the module-level layout and wiring engine levels the hierarchical structure inside the module and then performs optimal layout and wiring on the hierarchical structure so as to meet the timing constraint condition of the module level. And then, integrating abstract representations of all modules with time sequence information and physical boundary information to obtain a top-level design. If the input or (and) output timing condition of a module is not satisfied in consideration of the timing analysis after the RC extraction of the top-level design, that is, the inter-module timing path including the module cannot satisfy the timing constraint condition, the module is on the critical path, in this case, for all modules on the critical path, the timing constraint condition of the top-level design needs to be re-budgeted and planned to obtain a new timing constraint condition, and the layout and wiring of the modules need to be re-optimized and modified. This process will iterate repeatedly until all modules and timing constraints between modules are satisfied.

From the above analysis, in a typical automatic place and route tool, a circuit is divided into a top level design and a module level design. The timing constraint conditions of the module level design are obtained by artificial budget planning of the timing constraint conditions of the top level design, and after the layout and the wiring which meet the timing constraint conditions are completed at the module level and integrated to the top level design, the timing constraint conditions among the modules may not be met, so that the module level layout and wiring process needs to be iterated repeatedly, and the calculation efficiency of the whole process is reduced.

Disclosure of Invention

Aiming at the problems in the prior art, the invention provides an optimization method of an integrated circuit with a hierarchical structure, which directly optimizes circuits among modules under the condition of chip-level time sequence constraint, thereby effectively improving the efficiency of automatic layout and wiring.

In an embodiment of the present invention, there is provided a method for optimizing an integrated circuit having a hierarchical structure, the hierarchical structure of the integrated circuit including a module located at a top layer and a plurality of modules located at other layers, each module including at least one lower module located at a next layer except a module located at a lowest layer, the method including:

selecting a module to be optimized and a lower module of the modules;

and performing time sequence analysis and optimization on boundary paths among the lower-layer modules, so that circuits in the modules meet time sequence constraint conditions of the modules.

In the embodiment of the invention, the netlist, the wiring information and the resistance-capacitance information of the boundary path between the lower-layer modules are subjected to time sequence analysis and optimization, so that the boundary path between the lower-layer modules is subjected to time sequence analysis and optimization.

In the embodiment of the present invention, the performing timing analysis and optimization on the boundary path between the lower modules includes:

performing time sequence analysis according to netlist data of the current module and the low-level module;

judging whether the result of the time sequence analysis meets the corresponding time sequence constraint condition or not;

if yes, the boundary path time sequence constraint condition among the lower-layer modules is converged;

and if not, performing time sequence optimization on the boundary path between the lower-layer modules.

In the embodiment of the invention, the time delay of the boundary path between the lower-layer modules is adjusted by inserting a buffer or changing the size of a logic gate.

In the embodiment of the present invention, after performing timing analysis and optimization on the boundary path between the lower modules, the method further includes:

judging whether the internal path of the low-layer module meets a time sequence constraint condition or not, if so, taking the optimized boundary path data as the time sequence convergence data of the current module;

otherwise, performing time sequence optimization on the internal path of the low-layer module to enable the internal path of the low-layer module to meet the time sequence constraint condition.

In the embodiment of the present invention, the internal path of the lower layer module is subjected to timing optimization, so that after the internal path of the lower layer module satisfies the timing constraint condition, the boundary path between the lower layer modules is subjected to timing analysis and optimization again, so that the circuit in the module satisfies the timing constraint condition of the module.

In the embodiment of the present invention, performing timing analysis and optimization on a boundary path between the lower modules, so that a circuit in the module satisfies a timing constraint condition of the module, includes:

acquiring hierarchical RC information of the module;

combining the RC information of the boundary paths between the lower-layer modules, and expanding the RC information to the whole boundary path of the modules to generate the RC information of the whole boundary path of the modules;

performing RC analysis on RC information of the whole boundary path of the module to judge whether a time sequence constraint condition conflict exists in the module at the lower layer;

and if the time sequence constraint condition conflict exists in the low-layer module, optimizing and modifying the internal path of the low-layer module, so that the time sequence constraint condition of the boundary path between the low-layer modules is met while the internal path of the low-layer module meets the corresponding time sequence constraint condition.

In the embodiment of the invention, the internal paths of the low-layer modules are subjected to time sequence optimization, so that after the internal paths of the low-layer modules meet the corresponding time sequence constraint conditions, the boundary paths between the low-layer modules are subjected to time sequence analysis and optimization again, so that the circuits in the modules meet the time sequence constraint conditions of the modules.

In the embodiment of the present invention, an optimization system of an integrated circuit with a hierarchical structure is further provided, and when the integrated circuit with the hierarchical structure is optimized, the optimization method of the integrated circuit with the hierarchical structure is adopted.

In an embodiment of the present invention, a storage medium is further provided, where computer program instructions are stored in the storage medium, and when the computer program instructions are executed by a computer, the method for optimizing an integrated circuit with a hierarchical structure is performed.

Compared with the prior art, in the hierarchical circuit optimization method of the embodiment of the invention, firstly, the timing constraint condition between the modules is directly obtained from the timing constraint condition of the top layer design, the timing analysis and optimization are carried out aiming at the circuit between the modules, the circuit layout and wiring realization meeting the timing constraint condition between the modules is obtained, then the timing analysis and optimization modification between the modules are taken as input, namely, the circuit layout and wiring realization inside the modules is carried out under the influence of the timing optimization and modification between the modules is considered, the timing analysis and optimization and modification of the circuit inside the modules are simultaneously carried out, the influence of the automatic layout and wiring of the circuit inside the modules on the timing analysis of the circuit between the modules is considered according to the result of the timing analysis and optimization and modification of the circuit inside the modules, and the iteration times of the layout and wiring of the module level and the top layer design can be reduced because the automatic layout and wiring of the circuit inside the modules is, thereby greatly improving the calculation efficiency of the whole optimization process.

Drawings

FIG. 1A is a schematic diagram of a hierarchical design of an integrated circuit according to an embodiment of the present invention;

FIG. 1B is a flowchart of a method for optimizing an integrated circuit having a hierarchical structure according to an embodiment of the present invention;

FIG. 2 is a flowchart illustrating an exemplary method for optimizing an integrated circuit having a hierarchical structure to achieve timing closure among modules;

FIGS. 3A-3B are exemplary diagrams illustrating timing analysis and optimization of a boundary path of a module according to an embodiment of the present invention;

FIG. 4 is a flowchart illustrating timing analysis and optimization of a boundary path of a module using RC analysis according to an embodiment of the present invention;

FIGS. 5A-5B are exemplary diagrams illustrating timing analysis and optimization of the boundary paths of a module according to embodiments of the present invention;

FIG. 6 is a flowchart illustrating a method for optimizing an integrated circuit having a hierarchical structure to perform timing closure within a module according to an embodiment of the present invention.

Detailed Description

Methods and processes for timing analysis and optimization for integrated circuits having a hierarchical structure to satisfy timing constraints are disclosed. The hierarchy of the integrated circuit comprises a module at the top level and a plurality of modules at other levels, each module comprising at least one module at a lower level, except for the module at the lowest level. In some embodiments, the invention first performs timing analysis and optimization on the selected circuits, for example, selecting the top level circuit and the next level module circuit, in order to satisfy the timing constraints. In some embodiments, the selected circuit includes a sequential circuit path between modules. The method of the invention analyzes and optimizes the time sequence of the circuit in the module on the basis of considering the optimization of the time sequence path among the modules so as to meet the time sequence constraint condition in the module.

FIG. 1A illustrates an example of a design during a place and route process. In this example, 100 is a hierarchical design of an integrated circuit. The memory 152 stores therein a top layer design unit and a next layer module design unit. Each element in the hierarchy can be viewed as a container that stores information for the next hierarchical element. For example, container 102 stores graphics chip top level assembly data, which includes

sub-containers

104 and 110, which store input/output, DSP, etc. data in sub-modules corresponding to the containers. The format of input and output design data adopts a uniform project file format, thereby achieving a consistent design environment.

In some embodiments, the circuit design includes circuit element netlist and routing information. The RC information (i.e., parasitic resistance and capacitance information) can be extracted from the wiring information. During the placement and routing process, a hierarchical data structure is maintained. In other words, in this example, the top level processing maintains the structure of the top level container and the next level module sub-containers, although the circuitry in the next level module container may be leveled and analyzed and optimized for timing. Because the hierarchy and boundary information is maintained at all times, optimizations performed on the module data at the top and next levels can be placed back into the corresponding containers during the top-level processing. In the embodiment of the invention, the time sequence analysis and optimization are directly carried out on the top layer design and the module level design in the top layer processing, so that the time sequence constraint condition of the whole chip is met.

FIG. 1B is a flow chart illustrating a method for optimizing an integrated circuit having a hierarchical structure in accordance with the present invention. Process 180 may be performed by a computer system or corresponding device.

In step 182, hierarchical circuit data is accessed through the hierarchical circuit design. FIG. 1A is an example of a hierarchical design, where the accessed hierarchical data includes the next level of module data (e.g., 104-110) and the top level data (e.g., 120). Netlist, routing, and/or RC data may be accessed. In some embodiments, the data is stored on the media in an item file and the memory may be read back from the media. This maintains the hierarchical data structure at all times.

In the prior art, a typical place and route process includes these main steps: layout planning, module level design, and chip top level assembly. Timing constraints within the individual modules are typically satisfied prior to top level assembly. However, for the module level designer, the parts outside the module he is responsible for are not visible and cannot be optimized for timing analysis. Therefore, the delay of the timing path between the modules often results in the timing constraints of the entire chip not being satisfied. The timing paths between the modules (usually referred to as boundary paths) are timing paths at the boundaries of the respective modules (for example, as shown by path 122 in fig. 1A); intra-module paths refer to paths that are entirely internal to the respective module (as shown by path 124 in fig. 1A).

Step 184 of fig. 1B, performs timing analysis and optimization on the inter-module timing path selected in the hierarchical structure circuit, so that the timing constraint condition of the inter-module path is satisfied. In some embodiments, the netlist, the routing information, and the rc information of the paths between the modules are subjected to timing analysis and optimization, so as to satisfy the timing constraint condition between the modules, and in some specific cases, the timing between the modules is also converged after iteration loop, which is described in detail below.

In some embodiments, the step of laying out and routing at the module level is the same as that of the top-level design, and data of the next layer of sub-modules does not need to be repeatedly accessed in the process of timing analysis and optimization. Since this method is to directly optimize the timing path between modules in the top layer, there is no need to do eco (engineering changeorder) for the design engineer at the module level, so the iteration cycle of the design flow will be greatly shortened.

Fig. 2 is a block diagram illustrating how timing closure between modules is achieved in the method for optimizing an integrated circuit having a hierarchical structure according to an embodiment of the present invention. Process 200 may be performed on a computer or any other suitable device. Step 184 of process 180 may be implemented by process 200 shown in fig. 2.

Assume that in step 204, the data of the hierarchy circuit is already accessible and a portion of the data is selected for timing analysis.

In some embodiments, the selected data includes the top module and all modules in the hierarchy. The time sequence constraint condition of each sub-module can be obtained by the time sequence constraint condition of the whole circuit through a certain budget planning method. The goal of timing analysis optimization is to modify the circuit so that the overall circuit meets the overall timing constraints. In a typical design flow of the prior art, timing constraints of each module are first satisfied in a design stage at a module level before a final assembly process of place and route. For module level engineers, it is generally difficult for them to plan timing constraints for the circuit portions not under their responsibility, so that the boundary paths between modules may cause the timing constraints of the whole chip to be not satisfied due to unreasonable budget planning. Therefore, in the embodiment of the present invention, path data between modules may be selected first, put into a container for top-level processing, and perform timing analysis and optimization on the part of data first, instead of performing timing analysis and optimization on the whole chip at the beginning, which has the advantage of greatly improving the computational efficiency.

Fig. 3A-3B illustrate in detail how to select paths between modules for timing analysis and optimization, as an example.

In some embodiments, selected data is stored in an internal memory (e.g., RAM) with a small processor access latency, which is relatively fast to process, while other data is stored in an external memory with a large processor access latency, such as a virtual memory and a hard disk, which is backed up and transferred to the internal memory when needed for processing.

In step 206, selected data is subjected to timing analysis, i.e., selected netlist data is subjected to timing analysis, including Static Timing Analysis (STA), RC analysis, and other suitable timing analysis methods.

In step 208, it is determined whether the timing analysis result of the selected netlist data satisfies the corresponding timing constraint, i.e. the timing constraint of the current top layer. If yes, the current timing constraint condition among the modules is converged. If not, go to step 210 to optimize the selected inter-module path as the current top-level optimization process. The optimization method comprises a plurality of standard optimization methods, selected circuit data and corresponding time sequence constraint conditions are used as input of the optimization process, and optimized circuits meeting the time sequence constraint conditions are used as output of the optimization process. In optimization, some logic modifications are made to the circuit in order to adjust the timing of the circuit, for example, buffers (buffers) may be inserted and the gate size (gate size) may be changed to optimize the timing. After the current time sequence analysis and optimization of the paths among the modules are processed, corresponding physical modification is realized on the premise of meeting design rules aiming at the layouts in the related modules caused by the optimization modification.

After the optimization of the selected portion is completed, flow control passes to step 206 to re-perform timing analysis on the optimized and modified circuit. Step 208 is re-executed, i.e. whether the analysis result meets the timing constraint, and step 210 is re-executed if necessary, i.e. further optimization modification is performed. The iterative process of step 206 and step 210 is repeated to finally make the timing constraint condition between the modules converge.

Block structure fig. 3A-3B present an example of a circuit for placement and routing processing corresponding to process 200 in fig. 2. In this example, it is assumed that the internal timing constraints of

blocks

302 and 304 have converged, and timing constraints between the blocks need to be converged through timing analysis and optimization.

As shown in the example of fig. 3A, the boundary path between sequential elements a and D is an inter-module timing path, and the timing analysis results for this timing path indicate that the timing constraint is not satisfied. Thus, the current top-level timing optimization is performed for this timing path, and the result of the timing optimization modification for this path is given in fig. 3B. Specific optimization modifications include the gate 306 being enlarged in size and the insertion of

buffers

308 and 310.

The above optimization modification changes the wiring manner and the RC tree of the circuit, thereby changing the time delay of the timing path. For example, in fig. 3B, the routing of the paths in the circuit, the topology of the RC tree, and the wire time delays are changed due to the insertion of

buffers

308 and 310. Therefore, for the wiring manner change of the optimization modification circuit, RC analysis is applied for evaluation to ensure that the timing constraint condition after the wiring manner change is still satisfied.

Fig. 4 shows a flow of instantiation of the RC analysis process. In some embodiments, process 400 is used to make timing constraints converge as part of the timing analysis. For example, the process 400 may be incorporated at step 206 of the process 200 described above, as well as step 210, or at step 608 of the process 600 described below, as well as step 610.

Assuming that the hierarchical data has been accessed at step 404, the hierarchical RC information is obtained and the hierarchical structure of the hierarchical data is maintained. In other words, the module boundaries are maintained and the hierarchical RC data corresponding to the top and bottom modules is stored in the containers corresponding to each module. In some embodiments, RC information on the boundary may be obtained, which is derived from RC trees between modules on the boundary path and from RC trees inside the modules on the boundary path. Referring to the example of FIG. 3A, paths B-C connect

modules

302 and 304, and the RC tree based on this path is obtained by the container of the top module 305; accordingly, the RC tree based on paths A-B and C-D is obtained by the containers of the

underlying modules

302 and 304.

At step 406, the inter-module and intra-module RC information on the boundary path are combined together to generate boundary RC information. In the example of FIG. 3A, the RC trees between paths B-C, and between paths A-B and C-D are combined to produce the RC information for the boundary paths A-D.

At step 408, an RC analysis is performed using the boundary path RC information.

At step 410, the timing delay resulting from the RC analysis is compared to an expected delay. If the calculated delay is less than the expected delay, the global RC delay is not degraded by the previous optimization modifications to satisfy the inter-module timing. The timing constraints of the RC analysis are thus converged. Conversely, if the calculated delay exceeds the desired delay, further optimization and adjustment of the circuit should be performed at step 414. In some embodiments, repeating process 400 may further optimize and modify the netlist until timing constraints and RC delays from the timing budget are both satisfied.

In this case, an RC tree that is completely inside the module and does not cross the module boundary is not used. Since in most cases such data amounts account for 80% of the total RC data, ignoring this RC information entirely within the module when performing the analysis can greatly reduce the need for inventory during the analysis. In some embodiments, after modifying the netlist, only those boundary paths that cause changes in the RC tree are selected for timing analysis and optimization, further reducing the amount of data that needs to be calculated.

Modifications to the boundary path for inter-module timing constraint convergence may also affect the timing of other paths within the module, resulting in the need for additional processing. FIGS. 5A-5B are schematic diagrams illustrating an example circuit design in which block internal timing is affected by timing modifications on boundary paths. FIG. 5A is similar to FIG. 3A, except that in addition to the boundary paths, there are affected module internal paths, such as the E-F internal path of module 302 and the G-H internal path of module 304 in FIG. 5A. Although the inter-module paths and intra-module paths are not directly electrically connected, modifications to the inter-module boundary paths may change adjacent intra-module paths through coupling capacitance, thereby changing the timing of these paths. For example, as shown in FIG. 5B, when additional buffers 310 are added, the intra-module paths E-F are affected; the module internal path G-H is also affected after the logic gate 306 is resized.

If the internal timing constraints of a block conflict, intra-block repairs can be made so that the modified intra-block paths satisfy the timing constraints and so that inter-block paths adjacent to the block do not violate the timing constraints. For example, logic gates 314 on paths E-F are sized so that timing constraints internal to module 302 are satisfied, and accordingly additional buffers 316 are inserted in paths G-H so that timing constraints internal to module 304 are satisfied. In some embodiments, iterative iterations of timing analysis and optimization may be required to achieve timing convergence.

FIG. 6 is a flow chart of circuit optimization of timing impact within a block according to boundary paths in an embodiment of the present invention, and FIG. 6 describes a process of timing closure within a block. Process 600 may be performed after inter-module timing constraints are satisfied.

Step 602 is to perform timing analysis on a module. In the process of analyzing the timing of the module, the results of the boundary path and inter-module path timing analysis are used as the conditions, and the influence of the boundary path and the inter-module path timing analysis on the timing of the internal path of the module is considered. Referring to the example of FIG. 5A, when performing timing analysis on the block 302, the results of the boundary path A-D timing analysis are used as inputs to account for its effect on the block internal path E-F timing. Similarly, when the block 304 is analyzed in timing, the results of the boundary path A-D timing analysis are taken as input, thereby taking into account its effect on the intra-block path G-H.

Returning to step 604 of fig. 6, after the module is subjected to timing analysis and optimization, it is checked whether timing constraints inside the module are satisfied. If the module internal timing constraint condition is satisfied, in other words, the module internal timing constraint condition is satisfied while the module inter-module timing constraint condition is satisfied, that is, no further optimization modification is required to be performed on the module, that is, the existing optimization modification of the module is submitted in effect. In different implementations, the module internal timing constraints may come from data at the module level and/or from the top level timing constraint file. If the module is in the process of serial processing and there is a next module to process, control transfers to step 602. If the modules are processed in parallel, or if all other modules have been processed, the process ends.

If, however, the internal timing constraints are not satisfied, then proceeding to step 606, an internal module optimization modification is made such that the internal timing constraints are satisfied. The time sequence analysis result of the boundary path is still used as input at this time, and the fact that the time sequence constraint condition conflict on the boundary path cannot be caused by module internal optimization modification is guaranteed. In other words, when performing intra-module optimization modification, it is necessary to ensure that the timing of the boundary path is not compromised. In some embodiments, step 608 performs an inter-module timing analysis. And when the time sequence between the modules is analyzed, the optimization modification inside the modules and the influence of the optimization modification on the time sequence of the boundary path are considered at the same time. Both intra-module optimization modifications and boundary paths are input variables to the inter-module timing analysis function. At step 610, the results of the inter-module timing analysis are checked for satisfaction of the inter-module timing constraints. If the inter-module timing constraints are satisfied, then the intra-module potential optimization modification does not compromise the inter-module timing, and thus this optimization modification is accepted at step 612. This process is complete or the process proceeds to the next module. If, however, the timing constraints between the modules are not satisfied, the potential optimization modification is rejected and control transfers to step 606 where another intra-module optimization is performed to find a potential optimization modification solution. Step 606-.

To sum up, in the hierarchical circuit optimization method according to the embodiment of the present invention, the timing constraint condition between the modules is directly obtained from the timing constraint condition of the top layer design, the timing analysis and optimization are performed on the circuits between the modules, so as to obtain the circuit layout and wiring implementation meeting the timing constraint condition between the modules, then the timing analysis and optimization modification between the modules are used as input, that is, the circuit layout and wiring implementation inside the modules is performed under the influence of the timing optimization and modification between the modules is considered, the timing analysis and optimization and modification of the circuits inside the modules are performed at the same time, and the influence of the timing analysis and optimization and modification on the circuits between the modules is considered according to the result of the timing analysis and optimization and modification of the circuits inside the modules, because the automatic layout and wiring of the circuits inside the modules is performed under the premise of considering the timing analysis and optimization and modification between the modules, the iteration number of the module-level and, thereby greatly improving the calculation efficiency of the whole process.

The above examples are intended only to illustrate specific embodiments of the present invention. It should be noted that, for a person skilled in the art, several modifications and variations can be made without departing from the inventive concept, and these modifications and variations shall fall within the protective scope of the present invention.

Claims

1. A method for optimizing an integrated circuit having a hierarchical structure including a module at a top level and a plurality of modules at other levels, each module including at least one module at a lower level except for a module at a lowest level, the method comprising:

selecting a module to be optimized and a lower module of the modules;

2. The method of optimizing an integrated circuit having a hierarchical structure according to claim 1, wherein the timing analysis and optimization of the boundary paths between the lower modules are performed by performing the timing analysis and optimization of netlist, routing information, and resistance-capacitance information of the boundary paths between the lower modules.

3. The method of claim 1, wherein the analyzing and optimizing the timing of the boundary paths between the lower modules comprises:

performing time sequence analysis according to the netlist data of the current module and the low-level module;

4. The method of optimizing an integrated circuit having a hierarchical structure according to claim 3, wherein the delay of the boundary path between the lower modules is adjusted by inserting a buffer or changing the size of a logic gate.

5. The method of claim 1, wherein the step of performing timing analysis and optimization on the boundary path between the lower modules further comprises:

6. The method of claim 5, wherein the internal paths of the lower modules are time-sequence optimized such that the internal paths of the lower modules satisfy the time-sequence constraints, and then the boundary paths between the lower modules are time-sequence analyzed and optimized again such that the circuits in the modules satisfy the time-sequence constraints of the modules.

7. A method for optimizing an integrated circuit having a hierarchical structure according to claim 1, wherein the timing analysis and optimization of the boundary paths between the lower modules such that the circuits in the modules satisfy the timing constraints of the modules comprises:

acquiring hierarchical RC information of the module;

8. The method of claim 7, wherein the internal paths of the lower modules are time-sequence optimized such that the internal paths of the lower modules satisfy their respective timing constraints, and then the boundary paths between the lower modules are time-sequence analyzed and optimized again such that the circuits in the modules satisfy the timing constraints of the modules.

9. A system for optimizing an integrated circuit having a hierarchical structure, wherein the method for optimizing an integrated circuit having a hierarchical structure according to any one of claims 1 to 8 is used for optimizing an integrated circuit having a hierarchical structure.

10. A storage medium having stored therein computer program instructions which, when executed by a computer, perform a method of optimizing an integrated circuit having a hierarchical structure according to any one of claims 1 to 8.