JPH0536295A - Semiconductor memory - Google Patents

Abstract

PURPOSE:To enhance the defect relief rate of a device and to improve the yield of a product by dividing a regular memory cell into first and second column areas, providing a redundant row decoding circuit at respective column areas, synthesizing a decoding signal and selecting one redundant row. CONSTITUTION:A Yi is one of row addresses, and the Yi is 0 and 1, and then, respective left half and right half of a regular memory cell array 1 are designated. A YiB is the negative signal of the Yi. In order to decode a defective row to redundant row decoding circuits 31 and 32, a row address and column signals Yi and YiB are respectively inputted. When decoding signals 131 and 132 are generated, the selection of the array 1 is inhibited, in order to select a redundant row 2, the OR of the signals 131 and 132 is obtained, and a redundant row selecting signal 141 and a selecting inhibited signal 142 of a regular memory cell are generated. The row address from an external part is coincident to the address of A, the Yi is 0, and then, a signal 131 becomes valid, the signal 141 is generated, and the A' is replaced to the redundant row 2. On the other hand, when the row address is equal to A and the Yi is 1, the 131 become invalid and the row of the regular memory cell is selected.

Description

Detailed Description of the Invention

[0001]

BACKGROUND OF THE INVENTION 1. Field of the Invention The present invention relates to a semiconductor memory device having a redundant function.

[0002]

2. Description of the Related Art In order to improve the product yield of a semiconductor memory device such as a random access memory (RAM), a repairing method has been adopted in which defective memory cells are replaced with redundant memory cells to operate as good products. A block diagram of a conventional RAM including a redundancy function is shown in FIG. The memory cell array 1 is arranged in a matrix of rows and columns,
A memory cell is selected by a row decoder designating a row line and a column decoder designating a column line from an externally applied row address and column address. Reference numeral 2 is a redundant row in which spare memory cells are arranged in the row direction. When the defective memory cell A exists in the memory cell array 1, switching to the redundant memory cell is performed in row units. That is, the entire row A ′ including A is switched to the redundant row 2. Reference numeral 3 denotes a redundant row decoding circuit which outputs a redundant row selection signal 141 when the row address of the row A ′ including the defective memory cell is designated.

[0003]

Since the conventional semiconductor memory device is configured as described above, if there is even one defective memory cell in one row, other memory cells in the same row are also switched to redundant memory cells. Redundant memory cells cannot be used effectively. In particular, as the memory capacity increases with technological development, the number of memory cells per row tends to increase, and the usage efficiency of redundant memory cells decreases.
If there is a second defective memory cell in a different row, the circuit of FIG. 3 cannot repair it. For the relief, another redundant row is provided and it is necessary to switch the row unit.

The present invention has been made to solve such a problem, and an object of the present invention is to improve the yield of products by efficiently performing defect relief without increasing the number of redundant memory cells. ..

[0005]

A semiconductor memory device according to the present invention is provided with a redundant row in which normal memory cells arranged in a matrix of rows and columns and spare memory cells are arranged in a row direction. In the first of the regular memory cells
A first redundant row decoding circuit for generating a first decode signal based on a first column signal designating a column area and a row address, and a second column area different from the first column area. A second decode circuit for generating a second decode signal based on a second column signal and a row address, and the normal memory cell when the first decode signal or the second decode signal is applied. It is characterized in that a circuit for prohibiting the selection of the redundant row and selecting the redundant row is provided.

[0006]

Since the present invention has the above-mentioned configuration, it is possible to divide a normal memory cell and one redundant row into a plurality of column regions and independently set a row address for switching in each column region. The relief rate for the memory cell is increased.

[0007]

Embodiments of the present invention will be described below with reference to the drawings.

FIG. 1 is a block diagram of a RAM showing an embodiment of the present invention. Where Yi is one of the column addresses and Y
When i is 0, the left half area of the normal memory cell array 1 is designated, and when Yi is 1, the right half area is designated. YiB is a negative signal of Yi. There are two redundant row decoding circuits 31, 32, and 31 has Yi of 0 (Yi
It is valid when B is 1) and 32 is valid when Yi is 1. Therefore, the row address and the column signals Yi and YiB are input to decode the defective row. 31 and 3
2 can set an independent row address for switching to the redundant row. When the decode signal of either 131 or 132 is generated, the decode of 4 is performed in order to prohibit the selection of the normal memory cell array 1 and select the redundant row 2.
Redundant row selection signal 1
41 and the selection prohibition signal 142 of the regular memory cell are generated. Here, the defective memory cell A exists in the area of Yi = 0 and its row address is set to 31, and at the same time, the defective memory cell B exists in the row different from A in the area of Yi = 1 and the row address is set to 32. It is assumed that When the row address from the outside matches the address of A and Yi is 0, the decode signal 131 becomes valid, the redundant row selection signal 141 is generated, and A'is replaced by the redundant row 2. On the other hand, when the row address is equal to A and Yi is 1, 131 is invalid, redundant row 2 is not selected, and a row of normal memory cells is selected.
Similarly for B, when Yi is 0, the normal memory cell is selected, but when Yi is 1, redundant row 2 is selected for B ′. Thus, although only one redundant row is provided, different row addresses can be relieved in the left half region and the right half region in the column direction of the memory cell array. When the same row address is set to 31 and 32, one row including the normal memory cell is directly switched to the redundant row. When the number of defective memory cells is only A, the left half A'of the memory cell array is switched to the redundant row, but the right half normally uses the memory cells.

FIG. 2 is a circuit diagram of a redundant row decoding circuit according to the present invention. Program elements 31 and 32 for setting row addresses are S10 to S1n and S20 independently.
~ S2n are included. S1 and S2 are program elements for setting the use of the redundant circuit. 31
Includes a NAND 51 for synthesizing a row address given by the program element, and also receives a column signal YiB at the same time. YiB must be at H level, that is, Yi must be 0, for the output of 51 at which switching to redundancy becomes effective to be at L level. Therefore, this decoding circuit is valid when Yi is 0. On the other hand, since the column signal Yi is input to the NAND 52 at 32, Yi is 1
It becomes effective when.

In this embodiment, one column address Yi is used to describe the column region divided into two, but this division increases the column address to two or three and the redundant row decoding circuit to four.
By increasing the number to 8, the column regions can be divided more finely and repaired.

Although the embodiments of the present invention have been described above, the present invention is not limited to RAM, but ROM, PROM, and EEPROM.
It can be used for various storage devices as long as it has a redundant function. The devices to be used include MOSFETs, bipolar transistors, MESFETs, etc., and the program elements for storing redundant address information and replacement address information in a nonvolatile manner are fuses, MNOS, FAMOS
Etc.

[0012]

As described above, according to the present invention, the repair rate of defective memory cells can be increased, so that the product yield can be improved. Further, it is not necessary to increase the number of redundant memory cells for repairing a plurality of defective memory cells, and the chip area can be saved.

[Brief description of drawings]

FIG. 1 is a block diagram showing an embodiment of a semiconductor memory device according to the present invention.

FIG. 2 is a circuit diagram showing an embodiment of a redundant row decoding circuit of a semiconductor memory device according to the present invention.

FIG. 3 is a block diagram of a conventional semiconductor memory device having a redundancy function.

[Explanation of symbols]

 1 Normal Memory Cell Array 2 Redundant Row 3 Redundant Row Decode Circuit 31 Redundant Row Decode Circuit 32 Redundant Row Decode Circuit 131 Redundant Row Decode Signal 132 Redundant Row Decode Signal 141 Redundant Row Select Signal 142 Selection Disable Signal

Claims (1)

Claim: What is claimed is: 1. A semiconductor memory device having a redundant row in which normal memory cells arranged in a matrix of rows and columns and spare memory cells are arranged in a row direction. A first redundant row decode circuit for generating a first decode signal based on a first column signal designating a first column area and a row address, and a second column different from the first column area. A second decode circuit for generating a second decode signal based on a second column signal designating a region and a row address; and a second decode circuit when the first decode signal or the second decode signal is given. A semiconductor memory device comprising a circuit for prohibiting selection of normal memory cells and selecting the redundant row.