JPH0393097A - Semiconductor memory device - Google Patents

Abstract

PURPOSE:To relief a defective memory cell by adding a means switching an output line from a memory cell and an output line from a redundancy memory cell, and providing only an extremely small redundancy memory cell string. CONSTITUTION:Data outputted from the memory cell string selected at a column decoder 7 is supplied to a data switching circuit 3. On the other hand, the output data of the memory cell block 1 and the output data of the redundancy memory cell block 2 are inputted to the switching circuit 3. The switching circuit 3, the can switch an optional data line among the data line among the data lines for transmitting the output data of the block 1 and the data line for transmitting the output data of the block 2. When the data line is switched, the output data of the block 2 is supllied from the switching circuit 3 to a sensing amplifier 4 instead of the output data of the block 1 to be transmitted through the shifted data line. In such a manner, the optional data in the output of the block 1 is replaced by the output data of the block 2.

Description

DETAILED DESCRIPTION OF THE INVENTION <<Industrial Application Field> The present invention relates to a semiconductor memory device, and particularly relates to an improvement in a structure for relieving a defective memory cell in a semiconductor memory device.

(Prior Art) In semiconductor memory devices, it is not easy to avoid the occurrence of a small number of defective memory cells during manufacturing.

For this reason, semiconductor memory devices are usually equipped with a redundant circuit that includes redundant memory cells to replace defective memory cells, means for determining whether an input address is an address for which a redundant memory cell should be used, etc. It will be done.

FIG. 3 schematically shows an example of a conventional semiconductor memory device having a redundant circuit. There are two types of semiconductor memory devices: one that outputs one bit of data and one that outputs multiple pieces of data simultaneously. The semiconductor memory device illustrated in FIG. 3 is of the latter type.

In the semiconductor memory device of FIG. 3, a redundant memory cell block 102 is provided in addition to a regular memory cell block 101 having a plurality of memory cell columns. Redundant memory cell block 102 has a plurality of redundant memory cell columns.

Column decoder 10 for memory cell block 101
7 is provided. Column decoder 107 selects n memory cell columns in memory cell block 101 according to an input address (not shown). The n-bit data output from the memory cell column selected by the column decoder 107 is simultaneously output to the outside via the sense amplifier 104 and the output circuit 105.

A redundant memory cell column decoder 106 is provided for the redundant memory cell block 102 . The redundant memory cell column decoder 106 calculates the number (n) of memory cell columns simultaneously selected by the column decoder 107 in the redundant memory cell block 102 when an address for which a redundant memory cell column is to be used is given. Select the same number of redundant memory cell columns. These redundant memory cell columns replace n memory cell columns including a memory cell column having a defective memory cell. The n-bit data output from the selected redundant memory cell column is also input to the sense amplifier 104.

As shown in FIG. 3, data lines from the memory cell block 10l to the sense amplifier 104 [- share a part with the data line from the redundant memory cell block 102 to the sense amplifier 104, so there is a defective memory cell. When an address specifying a plurality of memory cell columns including a memory cell column is given to the semiconductor memory device, the output data of the plurality of memory cell columns is not input to the sense amplifier 104. This is a method in which a fuse is provided on the output side of each memory cell column and the fuses corresponding to the plurality of memory cell columns are cut in advance, and a gate controlled by a column decoder 107 is provided on the output side of each memory cell column. This is achieved by setting the column decoder 107 so that the gates corresponding to the plurality of memory cell columns are always in the off state.

(Problem to be Solved by the Invention) As described above, in a conventional semiconductor memory device that outputs multiple pieces of data at the same time, even if there is only one memory cell column containing a defective memory cell, if only that memory cell column contains a defective memory cell, First, the memory cell columns selected at the same time as that memory cell column are replaced by the redundant memory cell column at once. Therefore, the redundant memory cell block 102 needed to include at least the same number of redundant memory cell columns as the number of memory cell columns simultaneously selected by the column decoder 107.

Therefore, a problem arises in that the redundant circuit including the redundant memory cell block 102 occupies a large area on the chip, increasing the chip area of the entire semiconductor memory device.

The present invention has been made in view of the current situation, and its purpose is to reduce the number of redundant memory cells, which are significantly fewer than conventional methods, despite adopting a method of outputting multiple pieces of data at the same time. An object of the present invention is to provide a semiconductor memory device that can repair defective memory cells simply by providing a column and requires a smaller chip area than conventional devices. A semiconductor memory device includes a memory cell block having a plurality of memory cell columns, a redundant memory cell block having at least one redundant memory cell column, and selecting a plurality of memory cell columns from the memory cell columns. a column decoder for transmitting data output from the redundant memory cell block; and any data line among the data lines for transmitting data output from the memory cell column selected by the column decoder, and for transmitting data output from the redundant memory cell block. and a data switching means capable of switching between the data lines and the data line, thereby achieving the above object.

(Example) FIG. 1 shows a block diagram of an embodiment of the present invention.

In this embodiment, a memory cell block 1 having a plurality of memory cell columns and a redundant memory cell block 2 having at least one redundant memory cell column are provided. A column decoder 7 is connected to the memory cell block 1, and the column decoder 7 selects n memories among the memory cell columns in the memory cell block 1 according to an input address (not shown). Select a cell column. n output from the memory cell column selected by the column decoder 7
The bit data is given to the data switching circuit 3.

A column decoder 6 for redundant memory cells is connected to the redundant memory cell block 2 . memory cell block l
When an address specifying a memory cell column including a defective memory cell in the redundant memory cell column decoder 2 is given to the redundant memory cell column decoder 2, one redundant memory cell column is selected to replace the memory cell column. Settings are made in advance for the column decoder 6 for redundant memory cells.

The n-bit output data of memory cell block 1 and the output data of redundant memory cell block 2 are transferred to data switching circuit 3.
is input. The data switching circuit 3 switches between an arbitrary data line among the data lines for transmitting n-bit output data of the memory cell block l and a data line for transmitting the output data of the redundant memory cell block 2. I can do it. When the data line is switched, the output data of the redundant memory cell block 2 is transferred from the data switching circuit 3 to the sense amplifier 4 instead of the output data of the memory cell block l that should be transmitted via the switched data line. given to. As a result, any data in the output data of memory cell block 1 is replaced by the output data of redundant memory cell block 2. The output data of the memory cell block l transmitted through the data lines that are not subject to data line switching is applied to the sense amplifier 4 as is.

When replacing the output data of a memory cell column having a defective memory cell with the output data of a redundant memory cell column, blocking (blocking) of the output data of the memory cell column is as follows:
A fuse is provided on the output side of each memory cell column of the memory cell block l, and the fuse corresponding to the memory cell column including the defective memory cell is cut in advance so that data is not output from the memory cell column. It is carried out by However, the blocking of the output data of the defective memory cell column can also be performed in other ways.

For example, within the data switching circuit 3, output data of a memory cell column having a defective memory cell may be blocked. Alternatively, among the gate elements provided on the output side of each memory cell column and controlled by the column decoder 7 when selecting a memory cell column, the gate element corresponding to the memory cell column having a defective memory cell is always in an off state. The column decoder 7 may be configured so that

In this embodiment, when an address for selecting a memory cell column including a defective memory cell in memory cell block l and n-1 memory cell columns in a memory cell block l is input, the defective memory cell is selected. The defective memory cell is relieved by replacing only the output data of the included memory cell column with the output data of the redundant memory cell column. Conventionally, the redundant memory cell block 2 was required to have at least the same number of redundant memory cell columns as the number (n) of memory cell columns simultaneously selected in the memory cell block l, but in this embodiment, the redundant memory cell The memory cell block 2 only needs to be provided with a number of redundant memory cell columns commensurate with the number of defective memory cell columns to be relieved, and the minimum required number of redundant memory cell columns is one.

FIG. 2 schematically shows a second embodiment of the present invention.

In the embodiment shown in FIG. 2, the configuration of the data switching circuit 3 is shown in detail. This embodiment is a semiconductor memory device that simultaneously outputs 4-bit data.

Memory cell block 1 has four data blocks 11~
It is equipped with 14. Each data block has the same number of memory cell columns. One memory cell column is selected from each data block by column decoder 7, and output data of the selected memory cell column is input to data switching circuit 3 via data lines 15-18. In this embodiment, a cuttable hole (not shown) is provided on the output side of each memory cell column of the memory cell block 1. If a defective memory cell is found in a certain memory cell column by a test after the wafer process, the fuse corresponding to the memory cell column is cut in an appropriate manner.

The data line 4 is connected from the data switching circuit 3 to the sense amplifier 4.
Data is transmitted via 1-44.

The data switching circuit 3 includes a transistor 311 interposed between the data line 15 and the data line 4l. The gate of the transistor 311 is connected via an inverter 310 to a control line 31 connected to a data switching control circuit 30 provided in the data switching circuit 3.

A transistor 321, a transistor 33l, and a transistor 341 are interposed between the data line 16 and the data line 42, between the data line 17 and the data line 43, and between the data line l8 and the data line 44, respectively. ing. The gate of the transistor 321, the gate of the transistor 331, and the gate of the transistor 341 are connected to control lines 32, 33, and 34, respectively, which are connected to the data switching control circuit 30.

Transistors 323, 333 and 343 are interposed between data R15 and data lines 42, 43 and 44, respectively. In addition, the data line 41 and the data line l6
, l7 and l8, transistors 322, 33
2 and 342 are interposed, respectively. The gates of transistors 322 and 323 are connected to control line 32 via inverter 320. The gates of transistors 332 and 333 are connected to control line 33 via inverter 330. Further, the gates of the transistors 342 and 343- are connected to the control line 34 via an inverter 340.

The redundant memory cell column decoder 6 has a function of selecting one redundant memory cell column within the redundant memory cell block 2. The output data of the redundant memory cell column selected by the redundant memory cell column decoder 6 is input to the data switching circuit 3 via the data line 2l. The data line 21 is connected to the data line 41 by a transistor 301 whose gate is connected to the control line 3l.

The 4-bit data output from the sense amplifier 4 is given to the output circuit 5.

The operation of the data switching circuit 3 will be described assuming that a certain memory cell column in the data block 13 includes a defective memory cell. During normal operation, that is, when a memory cell column including a defective memory cell is not selected, a low level data block switching signal is output from the data switching control circuit 30 to the control 1913x. This turns on the transistor 311 and connects the data line 15 and the data line 41. At this time, the transistor 301 connected to the data line 2l to which data from the redundant memory cell block 2 is output is turned off, and the data line 21 is not connected to any data line. A high level data block switching signal is output to the control lines 32, 33 and 34. As a result, the transistors 321, 331, and 341 are turned on, and the data lines 16 and 42, the data lines 17 and 43, and the data lines 18 and 44 are turned on.
are connected to each other. In addition, transistors 322, 3
23, 332, 333, 342 and 343 are off. As a result of the above, data blocks 11, 12, l
The data output from 3 and 14 is transmitted through data lines 41 and 4.
2, 43 and 44, respectively, to the sense amplifier 4.

When a memory cell column including a defective memory cell in the data block 13 is selected, the data switching control circuit 30 sets the signal on the control line 3l to a high level, and controls the control line 1ij3.
3. Set the upper signal to low level.

As a result, the transistor 331 is turned off, and the data line 17 corresponding to the data block l3 is separated from the data $943. Also, the transistor 311 is turned off,
Data line 15 corresponding to data block 11 is data!
141.

Further, transistors 332 and 333 are turned on, data line 17 and data Ili41 are connected, and data line l5
and data 1143 are connected. The data line 2l connected to the redundant memory cell block 2 is connected to the transistor 30.
1 is turned on, so it is connected to the data line 4l. By switching the data lines in this manner, data output from the data block 1l is input to the sense amplifier 4 via the data line 15 and the data line 43.

Since the fuse corresponding to the memory cell column including the defective memory cell is blown as described above, no data is output to the data line 17. Instead, the data output from the selected redundant memory cell column in the redundant memory cell block 2 is transferred to the data 1i121 and the data line 41.
The signal is input to the sense amplifier 4 via. In this way, the data line 17 and the data line 2l are switched, and the output data of the memory cell column including the defective memory cell is replaced by the output data of the redundant memory cell column in the redundant memory cell block 2. Data blocks l2 and 14
The output data is sent to data lines l6 and 4 as in normal times.
2 and data lines 18 and 44, respectively, to the sense amplifier 4.

The operation of the data switching circuit 3 when a defective memory cell is included in a data block will be clear from the above description.

In this embodiment, when using the redundant memory cell block 2, the bit arrangement of the output data is different from normal, but by appropriately changing the bit arrangement when writing to the redundant memory cell block 2, it is possible to From this point of view, it can be made to look similar to a conventional semiconductor memory device.

It should be noted that the configuration of the data switching circuit 3 is not limited to that shown in FIG. 2, and it will be obvious to those skilled in the art that various configurations are possible within the scope of the present invention.

(Effects of the Invention) According to the present invention, although a method is adopted in which multiple pieces of data are output simultaneously, defective memory cells can be reduced by providing a much smaller number of redundant memory cell rows than in the past. A semiconductor memory device that can be repaired and requires a small chip area is provided. In particular, when there is one memory cell column including a defective memory cell to be relieved, the number of redundant memory cell columns may also be l.

4. No! H FIG. 1 is a block diagram schematically showing an embodiment of the present invention,
FIG. 2 is a diagram schematically showing a second embodiment of the present invention, and FIG.
The figure is a block diagram of an example of a conventional semiconductor memory device that outputs a plurality of data simultaneously.

DESCRIPTION OF SYMBOLS 1... Memory cell block, 11-14... Data block, 15-18... Data line, 2... Redundant memory cell block, 21... Data line for redundant memory cell block, 3...・Data switching circuit, 30...Data switching control circuit, 31-34...Control line, 301, 3
11, 321-323, 331-333, 341-34
3...Transistor, 310, 320, 330, 34
0...Inverter, 4...Sense amplifier, 5...
Output circuit, 6... Column decoder for redundant memory cells,
7...Column decoder.

that's all

Claims (1)

[Claims] 1. A memory cell block having a plurality of memory cell columns; a redundant memory cell block having at least one redundant memory cell column; and a plurality of memory cell columns among the memory cell columns. a column decoder to select; an arbitrary data line among the data lines for transmitting data output from the memory cell column selected by the column decoder; and a data line for transmitting data output from the redundant memory cell block. 1. A semiconductor memory device comprising: data switching means capable of switching between a data line and a data line;