JP3083923B2 - Device for relieving standby current failure of memory element - Google Patents

Description

DETAILED DESCRIPTION OF THE INVENTION

[0001]

BACKGROUND OF THE INVENTION 1. Field of the Invention The present invention relates to a device for relieving a standby current defect of a memory element, and more particularly, to a memory device having a NAND type cell array structure without changing the standby condition during and after a manufacturing process. The present invention relates to a standby current defect remedy device for a memory element, which suppresses an increase in standby current when a standby current defect due to stress occurs and enables a device to be completely relieved by means for correcting other data.

[0002]

2. Description of the Related Art In a memory device of a NAND type, when a voltage applied to a word line is a selected cell, the voltage is lower than the threshold voltage of an enhancement cell (logic "L"), and the voltage of a non-selected cell is reduced. In the case of a memory device having a decoding condition that is equal to or higher than the threshold voltage of the enhancement cell (logic "H"), all word lines are in a logic "H" state during standby, and are selected by an address input to the chip. Only a part of the word lines are in the state of logic "L".

Therefore, in a memory product having a normal NAND cell structure in which a word line is formed by a poly gate, most cells are stressed by a logic "H" voltage applied to the word line during operation. Such stress destroys the gate oxide film of the transistor connected to the word line, making it impossible to determine the state of the cell (data read). Such a problem can be corrected by using data correction means such as redundancy and ECC (Error Correction Code). However, in the standby state of the chip, the voltage of the word line is maintained at a high level. , A DC current path is formed, and a standby current defect is caused.

FIG. 3 shows a conventional NAND cell array circuit having such a problem, and shows a circuit having N string selectors. That is, the first to N-th strings ST1 to STn are provided, and each string has a bit line B / L1 to B / L.
n and word lines W / L1 to W / Ln, respectively, and only one of the first and second string select signals SS1 and SS2 is set to a high level according to an address input to the chip in a normal NAND cell state determination. , Only one selected word line among the word lines W / L1 to W / Ln becomes low level.

In FIG. 3, a transistor m1 is an N-channel enhancement MOS transistor having a normal positive threshold, and a transistor m2
Is a depletion transistor having a negative threshold. Also, transistors m3, m4, m
5 and m6 have an enhancement threshold voltage or a depletion threshold voltage depending on the contents of the program.

For example, when the first string select signal SS1 and the word line W / L2 are selected according to the decoding result of the address input to the chip, the voltage of the first string select signal SS1 becomes logic "H", The voltage of the second string selector signal SS2 becomes logic "L". At this time, the word lines W / L1 to W /
The voltage state of Ln is logic "L" only for the selected word line W / L2, and all other word lines are logic state "H". Therefore, the transistors m1 and m2 are turned on and the transistor m7 is turned off according to the decoding condition. Thereby, the bit line B /
L1 is electrically connected to the node A, while the node B is connected to the bit line B / L1 by the transistor m7,
It is cut off and floated. The transistors m3, m5, and m6 are turned on regardless of the contents of the program, and the presence or absence of the electrical connection to the ground node C 'is determined by the threshold voltage of the transistor m4 having the word line W / L2 as a gate input.

When the transistor m4 is in a depletion state, the bit line B is turned on even when the voltage of the word line W / L2 is logic "L".
An electric path is formed between / L1 and ground node C '. On the other hand, when the transistor m4 is an enhancement transistor, the transistor m4 is turned off, so that no electrical path is formed between the bit line B / L1 and the node C '.

The state of the cell selected by such decoding is determined by a sense amplifier (not shown) connected to the bit line B / L1.

[0009]

In the circuit of FIG. 3, when the chip is in the standby mode, the first and second string select signals SS1 and SS2 are at the logic "L" state and the word line W / The voltage states of L1 to W / Ln are logic "H". When the insulating film (for example, a silicon oxide film) that insulates the gate, source, and drain of the transistor m4 is broken due to the stress due to the applied voltage or a defect in the manufacturing process, the transistor m5 is switched from the word line W / L2. A current path is formed via m6. In this case, the transistor m4 is
Although relief can be achieved by data correction means such as redundancy or ECC, current consumption in the standby state of the chip increases. That is, the chip will not be completely rescued.

SUMMARY OF THE INVENTION It is an object of the present invention to prevent unnecessary current from flowing to the ground when a NAND cell array undergoes an irregular breakdown due to a stress during a manufacturing process or after a manufacturing process. An object of the present invention is to provide a standby current defect remedy device for a memory element which can prevent an increase in current at the time of standby and can completely rescue a chip by data correction means.

[0011]

According to the present invention, there are provided a plurality of (N) devices for preventing a standby current failure of a memory device.
, A first block and a second block, and a block decoding means for selectively activating one of the first and second blocks, each of the string means, Commonly connected to each of a corresponding plurality of (N) bit lines,
NAN of memory cell including MOS transistor
A plurality of word lines commonly connected to the respective NAND cell arrays of the plurality of string means, and one of the word lines. And a switching means connected between the NAND cell array and the ground of the string means, and the word line decoding of the selected block is performed. Means is enabled, the switching means of the selected block is turned on, the switching means of the unselected block is turned off, and the current path to the ground of the unselected block is cut off. I do.

[0012]

An embodiment of the NAND cell array circuit according to the present invention will be described in detail with reference to the accompanying drawings.

FIGS. 1 and 2 show a NAND cell array circuit diagram according to the present invention. Upon receiving signals from two string selectors, bit lines B / L1 and B / L2 are provided for each of strings ST1 and STn. The transistors m1 to m6 are provided with respective word lines W / L1 to W / L1.
This is a NAND cell array circuit in which W / Ln exists, and additionally includes a transistor m7 for ground string selection in series. The transistor m7 is constituted by an enhancement MOS transistor, and selectively turns on a current path between the transistors m5 and m6 and the node c.
It acts as a switching means for turning off, is provided for each of the strings ST1 to STn, and is turned on and off by a ground string select signal GSS.

In such a circuit configuration, the word lines W / L1 to W / Ln and the bit lines B / L1 to B / Ln
Ln and the first and second string select signals SS1, S
Even if a current path to the ground is formed when the transistor selected by S2 is in standby, the transistor m7 can be set by the ground string select signal GSS.
Is turned on and off, and the transistor m7 is in standby mode.
Is turned off, and is turned on if necessary in the read mode, thereby preventing an increase in current due to dielectric breakdown during standby of the chip. That is, the current path to the ground is cut off by the transistor m7.

FIG. 2 shows one embodiment of FIG. 1, in which a NAND cell array circuit section 1 commonly uses bit lines.
10, 210, NOR gates N1 and N2 whose levels are selected by decode signals for driving word lines and respective selectors, and NOR gates N1 and N2
And the first and second blocks 100 and 200 driven by.

First block 100 and second block 200
Are N string means ST1 to STn each composed of a NAND cell array using each bit line in common.
And decoding circuit units 120 and 220 for outputting decoding signals so that the N string means ST1 to STn perform ground string selection.
It is composed of In addition, the first block 100 and the second block 200 include the decoding circuit units 120 and 22.
The operation is divided by the logic signal output from the NOR gates N1 and N2 in "0".

With this configuration, an operating block is selected by an address decoding signal applied to the input terminals of the decoding circuit units 120 and 220, and N strings are selected by string select signals SS1 and SS2. One of the string units ST1 to STn is selected, and one word line is selected and driven by the word line decoding signals S1 to Sn. Further, the logic levels of the ground string select signals GSS1 and GSS2 are determined by the logic signals output from the NOR gates N1 and N2, and the current path to the ground is cut off or turned off by turning on / off the transistors M5 and M10. Decide whether to form a current path.

Here, the decoding circuit unit 120
At the time of chip standby, the two-stage inverters In1 and In2 are turned off so that the transistor M10 of the NAND cell array unit 110 is turned off by the output of the NOR gate N1.
And the transistors SSM3 and SSD3 and the transistor SSM which are turned on / off by the string select signals SS1 and SS2 which are the address decoding signals.
4 and SSD4 are connected to transistors M6 and M7 via inverters In3 and In4, respectively, to perform string selection. Also, word lines W / L11 to W / L
nn is a word line decoding signal S1 of the address.
One word line W / L11 is driven by the transistors WM3 and WMD3 and the inverters IW3 and IW4, which are turned off and on by Sn, and the other word line W / Lnn is driven by the transistors WM4 and WMD4 and the inverters IW1 and IW2. . The second block 200 also has the same configuration as the decoding circuit unit 220, which is composed of the transistors WM1 and WM.
2, transistor WMD1, WMD2 and transistor S
It is composed of SM1, SSM2, SSD1, SSD2 and inverters In5 to In8, IW5 to IW8, and is driven by a NOR gate N2 whose output level is determined by an address decoding signal. In FIG. 2, transistors that perform ground string selection are transistors M5 and M10.

As described above, according to the present invention, since the bit lines B / L1 to B / Ln are connected together with the respective strings ST1 to STn of the first block 100 and the second block 200, the address decoding signal is provided. Is selected, and one of the word lines of the block selected by the address word line decoding signals S1 to Sn is selected and driven.

For example, the inputs P0, Q of the NOR gate N1
0 and R0 are all logic "H", the NOR gate N
1 becomes a logic "L" and enters a standby state, the transistor M is connected via the inverters In1 and In2.
The ten gates go to logic "L" and are turned off.
Therefore, even if the bit line B / L1 is selected, the current path in the path from the transistors M6 to M10 to the ground c 'is cut off. Similarly, inputs P1, Q0,
Even when all of R0 are logic “H”, the current path is cut off in the second block 200. Thus, the ground string select signal becomes logic "L" and the transistor M5 is turned off, so that the bit line B / L1
Is selected, no current path is formed between the transistors M1 to M5 and the ground node C '. When one of the NOR gates N1 and N2 is selected and driven, the ground string select signal of the corresponding block becomes logic "H", and a current path is formed.

On the other hand, the inputs P0, P0 of the NOR gates N1, N2
When Q0 and R0 are logic "L" and the input P1 of the NOR gate N2 is logic "H", the logic "L" is output from the NOR gate N2 to the second block 2 as in the standby mode.
00 is not selected, the output of the NOR gate N1 becomes logic "H", and the transistor M10 of the first block 100 is turned on and selected. At this time, it is assumed that SS1 which is a string selector signal is logic "L" and SS2 is logic "H", S1 which is an address decoding signal for selecting a word line is logic "L", and Sn is logic "H". Then, the current supplied from the transistor SSD4 is supplied to the string selector signal S via the transistor SSM4.
When the current flows to the S1 side, the output of the inverter In4 becomes logic "H", and the bit line B / L1 is connected to the transistor M
6, and electrically connected to the node E via M7. At this time, the address word line decoding signal S1
Is a logical "L", the word line W / L1 changes to a logical "L" state when the supply current of the transistor WMD3 is completely synchronized via the transistor WM3. At this time, the ground string selector GSS
Is a threshold voltage state of the transistor M8 when a logic "H" voltage is applied to the transistor M10.
In other words, the one that forms an electrical path between the bit line B / L1 and the ground node C ′ according to the enhancement and depletion states is connected.

On the other hand, when a gate and a drain of a programmed cell are subjected to insulation breakdown and error correction is performed by ECC or the like, when a current path to the ground is formed by a cell which has been subjected to insulation breakdown during standby of a chip, the above-described grounding is performed. String selector transistor M10
Is turned off, a current path to the ground is not formed, and no standby current failure occurs. Of course, the same effect is obtained when the second block 200 is operated. In this case, the transistor M5 performs a ground string select and the transistors M1 to M
4, the standby current failure is prevented even when one of the transistors is broken down.

When the transistors M5 and M10 for ground selection are connected in series between the ground nodes C and C 'of the string and the transistors, respectively, to perform the read mode, these transistors M5 and M10 are used.
The effect due to is completely eliminated.

The decoding circuit 12
Needless to say, 0 and 220 can be replaced with other circuit configurations, and the configuration shown in FIG. 2 shows an embodiment.

[0025]

As described above, according to the standby current defect remedy device for a memory element according to the present invention, a transistor for ground selection operation is mounted in series with a transistor in a string, and a transistor connected to each word line is provided. An electric path between the gate and the ground node is selectively formed, so that even if a dielectric breakdown occurs in the NAND cell array, the current path is selectively turned on / off by the address decoding signal and flows into the ground at the time of standby. There is no current, and standby current failure can be prevented.

Therefore, the NAND cell array whose insulation has been broken is completely relieved by the data correction means or the like.
There is an effect that the defect rate of the semiconductor memory element is greatly reduced and the productivity is improved. Further, a great advantage of the present invention is that it can be easily applied to an existing NAND cell array without greatly changing the configuration of the existing NAND cell array.

[Brief description of the drawings]

FIG. 1 is a circuit diagram of a NAND cell array according to an embodiment of the present invention.

FIG. 2 is a diagram showing a detailed embodiment of FIG. 1;

FIG. 3 is a circuit diagram of a conventional NAND cell array.

[Explanation of symbols]

 ST1 to STn String B / L1 to B / Ln Bit line W / L1 to W / Ln Word line m1 to m7 Transistor

Continuation of the front page (56) References JP-A-2-177199 (JP, A) JP-A-58-141496 (JP, A)

Claims (4)

(57) [Claims] 1. A plurality of (N) string means, a first block and a second block, and a block decoding means for selectively activating one of the first and second blocks. Wherein each of the string means comprises a NAND cell array of memory cells each including a MOS transistor, which is commonly connected to a corresponding one of the plurality of (N) bit lines, and wherein the first block and the second block A plurality of word lines commonly connected to the NAND cell array of each of the plurality of string means; a word line decoding means for selectively activating one of the word lines; A switch connected between the NAND cell array of each of the plurality of string means and ground; The word line decoding means of the selected block is enabled, the switching means of the selected block is turned on, the switching means of the unselected block is turned off, A device that prevents the standby current failure of a memory device by blocking the current path to the ground of an unselected block. 2. The block decoding means comprises: a first NOR gate (N1) connected to the word line decoding means of the first block and the switching means; and a word line decoding means of the second block. Apparatus according to claim 1, comprising a decoding means and a second NOR gate (N2) connected to the switching means. 3. The first NOR gate (N1) includes a plurality of input terminals for receiving a plurality of input control signals, and the second NOR gate includes a plurality of inputs for receiving a plurality of input control signals. 3. The device of claim 2, including a terminal. 4. The switching means of the first block includes a first ground terminal and a plurality of transistors connected between the NAND cell array of each of the plurality of string means. 2. The apparatus of claim 1, wherein said switching means of said second block comprises a second ground terminal and a plurality of transistors connected between said NAND cell arrays of each of said plurality of string means. .