KR940009246B1 - Stand-by current fault repair - Google Patents

Abstract

The device for relieving a current-inferiority in a stand-by mode of a memory circuit having a NAND cell array includes a respective string selecting signal line, bit line and word line, and connecting by n number of strings, which can reduce an increasing current consumption due to an insulating break down by non-programming the NAND cell array, sequentially coupling a transistor for selecting a ground to the n number of string's grounds and thus cutting down or forming a current pass to ground in case of stand-by mode or read mode of a chip in accordance with a ground coupling signal.

Description

Standby Current Failure Remedy for Memory Devices

1 is a circuit diagram showing an embodiment of a NAND cell array according to the prior art.

2 is a circuit diagram showing an embodiment of a NAND cell array according to the present invention.

Figure 3 is a circuit diagram showing an embodiment of the standby current failure relief device of the memory device according to the present invention.

The present invention relates to a standby current failure remedy device for a memory device, and more particularly, in a memory device having an array structure of NAND type in a semiconductor memory device without changing the standby conditions in the manufacturing process and manufacturing process. The present invention relates to a standby current failure relief apparatus for a memory device which suppresses an increase in standby current consumption caused by post-stress current failure and enables complete recovery of the device by other data correction means.

In the NAND type memory device, the voltage applied to the word line is less than the threshold hold voltage of the cell (Enhancemnet) for the selected cell (logic “L”), and for the non-selected cell, Memory devices with decoding conditions above the hold-hold voltage (logic “H”) will cause the entire word line to be in a logic “H” state during standby, and only a portion of the word lines selected by the address entered into the chip will be logic “L”. Is in a state of “.

Therefore, memory products having a conventional NAND cell structure using a word line as a poly gate are stressed by a logic “H” voltage in which most cells are applied to the word line during operation.

This stress destroys the drain or source of the word line transistor and the gate oxide layer, which is an insulating layer, making it impossible to read the state of the cell. This problem can be solved by using data correction means such as redundancy and error correct cord (ECC) .However, since the word line voltage is maintained at the high level in the standby state of the chip, Forming a direct current voltage path causes a standby current failure.

FIG. 1 shows an embodiment of a conventional NAND cell array circuit having such a problem, and shows a circuit having N string selectors. That is, the first to Nth strings ST1 to STn are provided, and each string includes bit lines B / L1 to B / Ln and word lines W / L1 to W / Ln, respectively. In the case of reading the NAND cell state, only one of the first and second string select signals SS1 and SS2 becomes high level according to the address input to the chip, and one selected from the word lines W / L1 to W / Ln is selected. Only the word line goes low.

In FIG. 1, the transistor m1 is an N-channel dueance transistor with a conventional positive threshold, the transistor m2 is a deflection transistor with a negative threshold, and the transistors m3, m4, m5, m6) has a segment threshold voltage or a deflection threshold voltage depending on the program content. For example, when the address input to the chip is selected as a result of decoding, the first string select signal SS1 and the word line W / L2 are selected, the voltage of the first string select signal SS1 is logic “H” and the second string select signal. (SS2) This voltage is the logic "L". At this time, the voltage state of the word lines W / L1 to W / Ln is only the selected word line W / L2 and the logic “L”, and all other word lines are in the logic “H” state.

Therefore, the transistors m1 and m3 are turned on and the transistor m2 is turned off by the above decoding conditions. Accordingly, the bit line B / L1 is electrically connected to the node A, but the node B is cut off from the bit line B / L1 by the transistor m7 as described above. It is.

In addition, the transistors m3, m5, and m6 are turned on regardless of the program contents, and the presence or absence of electrical connection with the ground node c 'is applied to the transistor m4 using the word line W / L2 as a gate. Determined by the threshold hold voltage. If the transistor m4 is deflected, even if the voltage of the word line W / L2 is logic “L”, the electrical path between the bit line B / L1 and the ground node c ′ is turned on because the transistor is turned on. Is formed. In the case where the transistor m4 is a segment transistor, an electric path is not formed between the bit line B / L1 and the node c 'because the transistor m4 is turned off.

The state of the cell selected by this decoding is read by a sense amplifier (not shown) to be connected to the bit line B / L1.

In the circuit of FIG. 1, the first and second string select signals SS1 and SS2 are in a logic "L" state and the voltage states of the word lines W / L1 to W / Ln are logic "H". Word line W when the insulating film (for example, silicon oxide) that insulates the gate, the source, and the drain of the transistor m4 is destroyed due to stress or defects in the manufacturing process due to the applied voltage. / L2) forms a current path through the transistors m5 and m6.

As described above, the transistor m4 can be repaired by data correction means by redundancy or ECC. However, current consumption of the chip increases, making it difficult to completely repair the chip.

The present invention has been made to solve such a problem, and an object of the present invention is to prevent unnecessary current from being passed to the ground when the NAND cell breakdown occurs irregularly due to stress during or after the manufacturing process in the NAND cell array. The present invention provides a standby current failure relief device for a memory device capable of performing a complete rescue of a chip by data correction means while preventing a current increase during standby.

A feature of the standby current failure remedy device for a memory device according to the present invention for achieving the above object is a NAND cell array having a plurality of string selection signal lines, bit lines, and word lines, respectively, connected by N strings. In a memory device having a; The NAND cell array is not programmed, and a transistor for ground select is connected to the ground of the N strings in series so as to cut off a current path to ground during standby and read mode of the chip according to a ground selection signal. It is possible to reduce the increase of current consumption due to insulation breakdown.

Further features of the standby current failure relief device of the memory device according to the present invention include: N string means connected to share N bit lines and having two ground paths for at least one or more ground selects; At least one transistor connected to the ground selection signal line and the word line and the select line of the N string means, respectively, for selectively driving the N string means in accordance with an address word line decoding signal and a string select signal; Noah gates having three input terminals for applying a gate supply signal for selectively driving the transistors and inverters in block units; And decoding means for performing ground string select by decoding in units of blocks according to a supply level of a predetermined level of the noah gates.

Hereinafter, a standby current failure relief apparatus for a memory device according to the present invention will be described in detail with reference to the accompanying drawings.

2 is a schematic view of a NAND cell array circuit according to the present invention, in which signals of two string selectors are applied, and bit lines B / L1 to B / L2 are provided for each string ST1 to STn, and a transistor ( Do not program the NAND cell array in the NAND cell array circuit as shown in FIG. 1 in which word lines (W / L1 to W / Ln) are present in m1 to m6), and a transistor (m7) for ground string selection is added as a series. It is equipped with.

The transistor m7 is composed of a consequent shunt transistor, which acts as a switching means for selectively turning on / off a current path between the transistors m5 and m6 and the node c, and is provided in each string ST1 to STn. On / off is made by the ground string select signal GSS.

The circuit configuration is such that the transistors selected by the word lines W / L1 to W / Ln and the bit lines B / L1 to B / Ln and the first and second string select signals SS1 and SS2 are standby. Even when a current path is formed to ground, the transistor m7 is turned on / off by the ground string select signal GSS so that the standby transistor m7 is turned off and in the read mode, when turned on as necessary, This reduces the increase in rectification due to insulation breakdown during standby. In other words, the current path to ground is interrupted by the transistor m7.

3 illustrates an embodiment of FIG. 2, in which the first block 100 and the second block 200 each include N string means ST1 to STn configured of an NAND cell array using a bit line in common. And decoding circuits 120 and 220 for outputting a decoding signal so that the N string means ST1 to STn perform ground string select. In addition, the first block 100 and the second block 200 are divided and operated according to logic signals output from the NOA gates N1 and N2 in the decoding circuits 120 and 220.

As such, the block to be operated is selected according to the address decoding signal applied to the input terminals of the standby decoding circuitry 120 and 220 of the chip, and the N string means ST1 are selected by the string select signals SS1 and SS2. Any string means of ˜STn is selected, and one word line is selected and driven by the word line decoding signals S1 to Sn. In addition, the logic level of the ground string select signals GSS1 and GSS2 is determined according to the logic signals output from the NOR gates N1 and N2 so that the current path is blocked to ground by the on / off operation of the transistors M5 and M10. Or decide whether to form a current path to ground.

Meanwhile, each of the blocks 100 and 200 performs a string select by the decoding circuits 120 and 220, so that ground string select is performed.

Here, the decoding circuit unit 120 connects the inverters In1 and In2 of the second stage to turn off the transistor M10 of the NAND cell array unit by the output of the standby NOA gate N1 of the chip, which is an address decoding signal. Transistors SSM3 and SSD3 and transistors SSM4 and SSD4, which are turned on and off by the string select signals SS1 and SS2, are connected to the transistors M7 and M6 through inverters In3 and In4, respectively. Do it.

Further, the word lines W / L11 to W / Lnn are word lines formed by the transistors WM3 and WMD3 and the inverters IW3 and IW4 which are turned off and turned on by the word line decoding signals S1 to Sn of the address. The W / L11 is driven, and another word line W / Lnn is driven by the transistors WM4 and WMD4 and the inverters IW1 and IW2.

The second block 200 also constitutes the decoding circuit unit 220 by the same configuration, which includes the transistors WM1 and WM2, the transistors WMD1 and WMD2, the transistors SSM1 and SSM2, SSD1 and SSD2, and the inverter. It is driven by the NOR gate N2 composed of (In5 to In8) and (IW5 to IW8) whose output level is determined by the address decoding signal. Performing the ground string select in FIG. 3 is transistors M5 and M10.

As described above, according to the present invention, since the bit lines B / L1 to B / Ln are connected to the respective strings ST1 to STn of the first block 100 and the second block 200 together, A block to operate is selected, and one word line is selected and driven from the word lines of the block selected by the address word line decoding signals S1 to Sn.

For example, when the input terminals Po, Qo, and Po of the NOR gate N1 are all logic “H”, when the output of the NOR gate N1 becomes the logic “L” and is in a standby state, the inverters In1 and In2 are turned off. The gate of transistor M10 is turned to logic "L" and is therefore turned off.

Therefore, even when the bit line B / L1 is selected, the current path from the transistors M6 to M10 to the ground c 'is blocked.

In addition, even when the input terminals Po, Qo, and Ro of the NOR gate N2 are all logic “H”, the current path is blocked in the second block 200 in the same manner as described above.

As described above, since the ground string select signal becomes logic “L” and transistor M5 is turned off, the current path from transistors M1 to M5 to ground node c is blocked even when bit line B / L1 is selected. If one of the NOR gates N1 and N2 is selected and driven, the ground string select signal of the corresponding block becomes a logic “H” to form a current path.

On the other hand, when the input terminals Po, Qo, and Ro of the NOR gate N1 are logic “L”, and the input terminal P1 of the NOR gate N2 is the logic “H”, the NOR gate N2 is in standby mode. Similarly, the output of the logic “L” does not select the second block 100, and the NOA gate N1 selects the output of the logic “H” by turning on the transistor M10 of the first block 100. .

At this time, suppose that the string select signal SS1 is logic “L”, SS2 is logic “H”, and the address decoding signal S1, which selects a word line, is logic “L” and Sn is logic “H”. When the current supplied from the current flows through the transistor SSM4 to the string selector signal SS1, the output 54 of the inverter In4 becomes the logic “H” and the bit lines B / L1 drive the transistors M6 and M7. Electrically connected to node E

At this time, since the word line decoding signal S1 of the address is logic "L", when the supply current of the transistor WMD3 is completely synchronized through the transistor WM3, the word line W / L11 is converted into a logic "L" state. At this time, the state of the ground string selector GSS is applied to the transistor M10 due to the voltage of logic “H” applied to the threshold voltage state of the transistor M8, that is, the bit line B according to the resultant deflection and deflection state. It is determined that the electrical path between / L1) and the ground node c 'is formed.

On the other hand, when the gate and the drain of the programmed cell are insulated and corrected by ECC, the transistor M10 of the ground string selector is turned on when a current path to ground is formed by the insulated-breaked cell during standby of the chip. Since it is in the off state, no current path to ground is formed, and no standby current failure occurs.

Of course, the operation of the second block 200 has the same effect. In this case, the ground string select is performed by the transistor M5 to prevent the standby current failure even when one of the transistors M1 to M4 is insulated and destroyed. . In addition, when the transistors M5 and M10 for ground select are connected in series between the ground nodes c and c 'of each string and the transistors, the transistors M5 and M10 are not affected by these transistors M5 and M10. There will be no. Here, the decoding circuits 120 and 200 may be replaced with other circuit configurations, and the configuration shown in FIG. 3 shows one embodiment.

As described above, according to the standby current failure control device of the memory device according to the present invention, a transistor for ground select is provided in series in a string transistor so that an electrical path between a transistor connected to each word line and a ground node is established. Since it is formed selectively, even if an insulation breakdown occurs in the NAND cell array, the standby current failure is prevented because there is no current passing to the standby ground by selectively turning on / off the current path by the address decoding signal.

Therefore, since the NAND cell array insulated and destroyed by data correction means or the like is completely repaired, the defective rate of the semiconductor memory device is greatly reduced, and the productivity is also improved.

In addition, a great advantage of the present invention is that it can be easily applied to a conventional NAND cell array since it is configured in the same transistor series without greatly modifying the structure of the existing NAND cell array.

Claims (2)

A memory device including a string select signal line SS1 and SS2, a bit line B / L1 to B / Ln, a word line W / L1 to W / Ln, and a NAND cell array connected by N strings. In; The NAND cell array is not programmed, and the transistors for ground select are connected to the ground of the N strings in series so as to connect the current path to the ground in the standby mode and the read mode of the chip according to the ground selection signal GSS. The standby current failure relief device of a memory device, characterized in that to reduce or increase the current consumption due to breakdown by blocking or forming. N string means connected to share N bit lines B / L1 to B / Ln and having two ground paths for at least one or more ground selects; Ground word signal lines GSS1 and GSS2, word lines W / L1 to W / Ln, W / L11 to W / L1n and select lines S1 to S4 of the N string means, respectively, At least one transistor (In1 to In8, Iw1 to Iw8) for selectively driving the N string means in accordance with the decoding signals S1 to Sn and the string select signals SS1 and SS2; NOR gates (N1 to N2) having three input terminals for applying a gate supply signal for selectively driving the transistors and inverters in block units; And decoding means (120, 220) for performing ground string select by decoding the block units (100, 200) according to a supply level of a predetermined level of the noah gates. Standby current fault relief device.