JP3176038B2 - Semiconductor storage device - Google Patents

Description

DETAILED DESCRIPTION OF THE INVENTION

[0001]

BACKGROUND OF THE INVENTION 1. Field of the Invention The present invention relates to a semiconductor memory device, and more particularly to an address generation circuit in a semiconductor memory device having a boot block configuration in which divided blocks of a memory cell array are not uniform. For example, the present invention relates to a NOR type flash EEPROM. It is used for such a batch erasing type electrically erasable / rewritable semiconductor memory.

[0002]

2. Description of the Related Art Flash EEP, which is currently receiving attention
Many ROM products have a rewritable cell array area divided into blocks. further,
Data writing and erasing processes are automatically executed inside the memory chip, and the quality of the processing results (pass or fail)
The use of auto-writing and auto-erasing, which output a signal indicating that the user is informed to the user, has become mainstream.

A conventional product of such a flash EEPROM having a storage capacity of 1 Mbyte or 4 Mbyte has an equal block configuration in which the size of a divided block of a cell array is the same, and a power supply voltage for reading. V
A dual power supply system using a normal external power supply for supplying cc and an external power supply dedicated for writing / erasing for supplying a power supply voltage Vpp (for example, 12 V) for writing / erasing is adopted. By providing the external power supply dedicated for writing / erasing with a current supply capability necessary for erasing all the memory cells at the same time, a plurality of blocks in a region to be erased can be erased collectively.

By the way, recent flash EEPROMs
Therefore, there is an increasing demand for a product having a boot block configuration in which the size of the divided blocks of the cell array is not uniform, and further employing a single-source system that does not use an external power supply dedicated to writing / erasing.

In such a product, a read power supply voltage Vcc is used when data is rewritten by a booster circuit built in the memory.
It is necessary to generate the above high voltage, and if it is attempted to provide the booster circuit with a current supply capability necessary for erasing all the memory cells at the same time, the power consumption of the booster circuit becomes extremely large. This is disadvantageous for products that require power consumption.

Therefore, in order to suppress the power consumption of the booster circuit, the cell array area to be erased is set in units of blocks, and a plurality of blocks to be erased are automatically and automatically erased (auto-erase) for each block. I just need.

However, when an automatic erase mode is introduced into a flash EEPROM having a boot block structure, a plurality of blocks to be erased may include blocks of non-uniform sizes. It is necessary to devise an address circuit system so as to generate a selection address of a memory cell inside a block according to the size of the block.

[0008]

SUMMARY OF THE INVENTION The present invention has been made in view of the above circumstances, and when an automatic erase mode is introduced into a semiconductor memory device having a boot block structure, each block to be erased at the time of automatic erase is provided. It is an object of the present invention to provide a semiconductor memory device having an address circuit system capable of generating a block address corresponding to a block size and generating a block internal cell address for selecting a memory cell inside the block.

[0009]

According to the present invention, there is provided a semiconductor memory device comprising: a memory cell array having a plurality of divided blocks divided so as to have a non-uniform size; At the time of auto-erasing in which a plurality of blocks in the cell array area are serially designated in units of blocks and automatically erased, a block address corresponding to a block size is generated for each block to be erased and a memory inside the block is generated. An address generation circuit for generating a block internal cell address for selecting a cell.

[0010]

Embodiments of the present invention will be described below in detail with reference to the drawings. FIG. 1 shows a boot block (unevenly divided block) according to the first embodiment of the present invention.
4MB NOR Flash EEPRO with Configuration
An example of an M pattern layout is shown.

Note that the flash EEPROM of this embodiment is
A single-source system with a built-in booster circuit that boosts the read operation voltage supplied from an external power supply to generate write / erase voltages, and blocks multiple blocks in the cell array area from which data is erased An auto-erase mode is adopted in which data is specified serially for each block and automatically erased.

According to the present invention, at the time of automatic erasure, an address generation for generating a block address corresponding to a block size for each block to be erased and generating a block internal cell address for selecting a memory cell inside the block. Has functions.

In FIG. 1, a memory cell array 10 includes
7 blocks BK0-BK6 of 64K bytes each
And one block BK of 32 Kbytes
7 and one block BK10 of 16K bytes, and two blocks BK8 and BK9 of 8K bytes each.

In this case, the blocks BK0 to BK3 are arranged in the row direction to form a first area 101, and the remaining blocks BK4 to BK10 are arranged in the row direction to form a second area 102.

Each block BK0 in the first area 101
To BK3 in the row direction, a first main row decoder 111 is arranged at one end of the first area 101 in the row direction, and the blocks BK0 to BK3 are arranged in the row direction. A first sub-row decoder 121 is arranged at one end.

Similarly, as a configuration for performing row selection of each of the blocks BK4 to BK10 of the second area 102 by the double word line method, a second main area is provided at one end side in the row direction of the second area 102. A row decoder 112 is provided, and a second sub-row decoder 122 is provided at one end of each of the blocks BK4 to BK10 in the row direction.

Each block BK of the first area 101
0 to BK3 and each block BK4 to BK of the second area 102
K10 are arranged in the column direction, and between the two regions, the first region 101 has a first end on one end side in the column direction.
Of the second area 102 are arranged.
A second column selector 132 is provided at one end in the column direction.
Are arranged, and a column decoder 14 is arranged between the two column selectors.

FIG. 2 shows a part of a NOR-connected cell group in the memory cell array 10 in FIG. The drains of MOS transistors Q having a stacked gate structure for a plurality of EEPROM cells are commonly connected to one bit line BL, and a plurality of word lines WL correspond to each control gate of the plurality of transistors Q. The respective sources of the plurality of transistors Q are connected to a common source line SL.

FIG. 3 shows an example of allocation of block addresses in the flash EEPROM of FIG. In FIG. 3, 18-bit address signals A17 to A17 are used as block addresses for selecting seven blocks BK0 to BK6 each of 64 Kbytes.
0, the combination of the upper three bits A17 to A15 is used, and the remaining 15 bits A14 to A14 are used as block internal cell addresses for selecting these cells in the block.
0 is used.

The upper 4 bits A are used as a block address for selecting one block BK7 of 32 Kbytes.
A combination of 17 to A14 (A17 to A15 are all "1", A14
Is used, and the remaining 14 bits A13 to A0 are used as a block internal cell address for selecting a cell in the block.

As a block address for selecting one 16-Kbyte block BK10, a combination of upper five bits A17 to A13 (A17 to A13 are all "1") is used to select a cell in the block. 13 bits A12 to A12 as the block internal cell address for
0 is used.

Two blocks BK each of 8 Kbytes
8, a combination of upper six bits A17 to A12 as block addresses for selecting BK9 (A17 to A14 are all "1", A13 is "0", A12 is "0" or "1")
Are used, and the remaining 12 bits A are used as a block internal cell address for selecting these cells in the block.
11 to A0 are used.

FIG. 4 is a flow chart showing an example of a sequence in the auto erase mode of the flash EEPROM of FIG. First, for a block to be erased, write processing and write verify processing in units of one word in the block are repeated so as to be executed for all addresses. This write / verify processing is performed by a NOR type flash EE having a NOR connection as shown in FIG.
This is a process for preventing over-erasure of cells when erasing the PROM.

Next, the cell array area to be erased is set as a block unit, and the erasing process and the erase verifying process are performed in units of one word for each block to be erased so as to be repeated for all the addresses, thereby performing the erasing. Automatically serially erase desired blocks serially for each block.

At this time, the address circuit system in the flash EEPROM shown in FIG. 1 generates a block address corresponding to the block size for each block to be erased, and outputs a block internal cell address for selecting a memory cell inside the block. It has a function to generate automatically.

FIG. 5 is a block diagram showing an address circuit system in the flash EEPROM of FIG. An external address signal externally input to the address input terminal (pad) 41 is input to the address buffer circuit 42.

The address generation circuit 43 performs serial erasure by automatically designating a plurality of blocks in the cell array area of the memory cell array to be erased in units of blocks and automatically erasing them. A block address corresponding to the block size is generated for each block to be erased, and a block internal cell address for selecting a memory cell inside the block is generated. In this example, an address counter 51, a logic circuit 52, It is composed of an address synthesis circuit 53.

An address signal output from the address buffer circuit 42 and an address signal output from the address generation circuit 43 are input to a selection circuit 44. During a normal operation, the address signal output from the address buffer circuit 42 is selected, and an automatic erase operation is performed. During operation, the address generation circuit 43
Is selected, and the selected address signal is input to an address decoder (each of the row decoder and the column decoder).

FIG. 6 is a circuit diagram showing an example of the address generation circuit 43 in FIG. FIG. 7 shows a part of the output signal of the address counter 51, a part of the internal logic signal of the logic circuit 52, the logical level of a part of the output signal of the address synthesizing circuit 53, and the block designated to be erased. It is a figure showing an example of correspondence.

The address counter 51 comprises 19 stages of flip-flop circuits FF0 to FF18, and the output signals AC18 to AC0 change from all "0" to all "1" with the counting operation.

The logic circuit 52 outputs a predetermined high-order bit signal AC18 to
AC12 is processed, and a fixed block address is output in accordance with the block size of the block to be erased.

The address synthesizing circuit 53 sets the fixed block address signal output from the logic circuit 52 as an upper bit, and the block internal cell address comprising a variable predetermined lower bit signal of the output signal of the address counter 51. Signal DD as the lower bit
17 to ADD0.

Next, the configuration and operation of the logic circuit 52 in FIG. 6 will be described in detail. The address signals AC17 and AC18 are input to a two-input NOR gate 61. The output of the NOR gate 61 is inverted by an inverter 62 to become a logic signal AL17. After the logic signal AL17 is shaped by two-stage inverters 63 and 64, Used as an address signal ADD17.

The address signals AC16 and AC18 are input to a two-input NOR gate 65, and the output of the NOR gate 65 is inverted by an inverter 66 to become a logic signal AL16. The logic signal AL16 is converted into a two-stage inverter 67,6.
8 is used as the address signal ADD16 after waveform shaping.

The address signals AC15 and AC18 are input to a two-input NOR gate 69, and the output of the NOR gate 69 is inverted by an inverter 70 to become a logic signal AL15, and the logic signal AL15 is converted into two-stage inverters 71, 7
2 is used as an address signal ADD15 after waveform shaping.

The first address switching circuit 91 receives, as a control signal, a logic signal BL14 generated as will be described later in accordance with the block designated to be erased, and outputs the address signal AC14 and a logic generated as described later. Signal AL14
Select one of

In this case, the logic level of the logic signal AL14 is "0" when the block designated to be erased is BK7, and when the block designated to be erased is any of BK8 to BK10. Becomes “1”.

When the block designated to be erased is any of BK0 to BK6, the logic level of the logic signal BL14 becomes "1" and the variable address signal AC1 is changed to "1".
4 is selected and blocks designated for erasure are BK7 to BK1.
If it is any one of 0, the logic level becomes "0" and the logic signal AL14 is selected, and the selected output is used as the address signal ADD14.

The circuit for generating the logic signal AL14 includes two-stage inverters 73 and 74 for shaping the waveform of the address signal AC18, and a two-stage inverter 75 for further shaping the output of the two-stage inverter. 76.

The circuit for generating the logic signal BL14 includes a three-input NAND gate 77 to which the logic signals AL17, AL16, and AL15 are input, and two-stage inverters 78 and 79 for shaping the output of the NAND gate 77. Have.

The second address switching circuit 92 receives as a control signal a logic signal BL13 generated as will be described later in accordance with the block designated to be erased, and outputs the address signal AC13 and a logic generated as described later. Signal AL13
Select one of

In this case, the logic signal AL13 has a logic level "0" when the block designated to be erased is any of BK8 to BK9, and a logic level when the block designated to be erased is BK10. Becomes “1”.

When the block designated to be erased is any one of BK0 to BK7, the logic level of the logic signal BL13 becomes "1" and the variable address signal AC1 becomes variable.
3 is selected and blocks designated for erasure are BK8 to BK1.
If it is any of 0, the logic level becomes "0" and the logic signal AL13 is selected, and the selected output is used as the address signal ADD13.

The circuit for generating the logic signal AL13 includes a two-input NAND gate 80 to which the address signals AC16 and AC18 are input, an inverter 81 for inverting the output of the NAND gate 80, and a second input for shaping the output of the inverter 81. And inverters 82 and 83 in stages.

The circuit for generating the logic signal BL13 comprises an inverter 84 to which the outputs of the two-stage inverters 73 and 74 for shaping the waveform of the address signal AC18 are inputted.
The inverter 78 to which the output of the three-input NAND gate 77 to which the logic signals AL17, AL16, and AL15 are input; the two-input NAND gate 85 to which the respective outputs of the two inverters 84 and 78 are input; And a two-input NOR gate 86 to which the logic signal AL14 is inputted.

The third address switching circuit 93 receives, as a control signal, a logic signal BL12 generated as described later in accordance with the block designated to be erased, and outputs the address signal AC12 and a logic generated as described later. Signal AL12
Select one of

In this case, the logic level of the logic signal AL12 is "0" when the block designated for erasing is BK8, and "1" when the block designated for erasing is BK9. Become.

When the block designated to be erased is any one of BK0 to BK7 and BK10, the logic level of the logic signal BL12 is set to "1" to select a variable address signal AC12 and to designate the erase designated. Block is BK
In the case of any one of 8 and BK9, the logic level becomes "0" to select the logic signal AL12, and the selected output is used as the address signal ADD12.

The circuit for generating the logic signal AL12 includes the two-input NAND gate 87 to which the address signals AC15 and AC18 are input, an inverter 88 for inverting the output of the NAND gate 87, and a waveform shaping of the output of the inverter 88. It has two-stage inverters 89 and 90.

The circuit for generating the logic signal BL12 includes the three-input NAND gate 77 to which the logic signals AL17, AL16, and AL15 are input, the inverter 78 to which the output of the NAND gate 77 is input, and the address signal AC16. And AC18, the two-input NAND gate 80, the inverter 81 to which the output of the NAND gate 80 is input, the inverter 94 to which the output of the inverter 81 is input, and the two-stage NAND gate for shaping the waveform of the address signal AC18. It has a three-input NAND gate 95 to which the outputs of the inverters 73 and 74 and the outputs of the two inverters 78 and 94 are input.

Next, the operation of the address generation circuit 43 in FIG. 5 will be described with reference to FIGS.
While the output signals AC17 to AC0 of the address counter 51 are changing, the blocks BK0 to BK6 are sequentially designated in accordance with the combination of the block addresses ADD17 to ADD15.
The lower bit signals AC14 to AC0 of the output signal of the address counter 51 are output as DD0.

Next, while the output signals AC17 to AC0 of the address counter 51 change after the output signal AC18 of the address counter 51 changes from "0" to "1", the combination of the block addresses AD17 to ADD12 is changed. Blocks BK7 to BK10 are sequentially designated in accordance with the above, and the lower bit signal A of the output signal of the address counter 51 is designated as the block internal cell address ADD13 to ADD0 or ADD12 to ADD0 or ADD11 to ADD0 at this time.
C13 to AC0 or AC12 to AC0 or AC11 to AC
Is output.

FIG. 8 shows an example of one stage of the address counter circuit shown in FIG. 5 taken out, and since this circuit itself is well known, a detailed description thereof will be omitted. FIG.
Shows an example of one of the address switching circuits shown in FIG. 5, which is well known and will not be described in detail.

[0054]

As described above, according to the present invention, when the automatic erase mode is introduced into a semiconductor memory device having a boot block configuration, a block address corresponding to the block size is assigned to each block to be erased at the time of automatic erase. It is possible to provide a semiconductor memory device having an address circuit system capable of generating a block internal cell address for generating and selecting a memory cell inside a block.

[Brief description of the drawings]

FIG. 1 is a 4 Mbyte NOR type flash EEPROM having a boot block configuration according to a first embodiment of the present invention;
FIG. 2 is a block diagram showing an example of an OM pattern layout.

FIG. 2 is a circuit diagram showing a part of a NOR-connected cell group in the memory cell array in FIG. 1;

FIG. 3 is a diagram showing an example of allocation of block addresses in the flash EEPROM of FIG. 1;

FIG. 4 is a flowchart showing an example of a sequence in an auto erase mode of the flash EEPROM of FIG. 1;

FIG. 5 is a block diagram showing an address circuit system in the flash EEPROM of FIG. 1;

FIG. 6 is a circuit diagram showing an example of an address generation circuit in FIG. 5;

FIG. 7 is a diagram showing an example of a correspondence relationship between an output signal of an address counter in FIG. 6, a logic level of an internal signal of a logic circuit, and a block designated to be erased;

FIG. 8 is a circuit diagram showing an example of one stage of the address counter circuit shown in FIG. 5;

FIG. 9 is a circuit diagram showing an example of one of the address switching circuits shown in FIG. 5;

[Explanation of Reference Codes] 10: memory cell array, 101: first area, 102: second area, 111: first main row decoder, 112: second main row decoder, 121: first sub row decoder, Reference numeral 122: second sub-row decoder, 131: first column selector, 132: second column selector, 14: column decoder, BK0 to BK10: divided block, 41: address input terminal (pad), 42: address buffer circuit 43, an address generation circuit, 44, a selection circuit, 51, an address counter, 52, a logic circuit, 53, an address synthesis circuit, 91 to 93, an address switching circuit.

──────────────────────────────────────────────────続 き Continuation of front page (56) References JP-A-8-22404 (JP, A) JP-A-58-105489 (JP, A) JP-A-4-351794 (JP, A) JP-A-7-107 176196 (JP, A) (58) Fields investigated (Int. Cl. ⁷ , DB name) G11C 16/00-16/34

Claims (4)

(57) [Claims] 1. A memory cell array having a plurality of divided blocks divided so as to include a non-uniform block size, and a plurality of blocks in a cell array area to be erased in the memory cell array in block units. At the time of automatic erasing in which data is automatically erased by serially designating each block, a block address corresponding to a floc size is generated for each block to be erased, and a block internal cell address for selecting a memory cell inside the block. And an address generating circuit for generating
And the address generation circuit generates a plurality of bits of an address signal.
An address counter for generating, and a predetermined upper bit of an output signal of the address counter.
Block signal for the block to be erased.
Logic circuit that outputs block address according to noise
And a fixed block address output from the logic circuit
Signal as the upper bit, the output signal of the address counter
Said block comprising a variable predetermined lower bit signal of
Lock internal cell address as lower bit
A semiconductor memory device comprising a dress synthesizing circuit . 2. An address input buffer circuit to which an external address signal input from the outside is input to an address input terminal, and an address signal output from the address input buffer circuit and an address signal output from the address generation circuit are input. A selection circuit that selects an address signal output from the address input buffer circuit during a normal operation, selects an address signal output from an address generation circuit during an auto-erase operation, and receives an address signal selected by the selection circuit. 2. The semiconductor memory device according to claim 1, further comprising an address decoder. 3. The non-uniformity among a logic signal set to a predetermined logic level or a multi-bit address signal output from the address counter according to a block size of a block to be erased. 3. The semiconductor memory device according to claim 1 , further comprising a switching circuit for selecting a bit signal related to a different block size. 4. The semiconductor device according to claim 1, wherein said semiconductor memory device is a flash EEP.
The memory cell array, wherein the memory cell array has a first region in which some of the plurality of divided blocks are arranged in the row direction and the remaining divided blocks of the plurality of divided blocks are arranged in the row direction. And the first area is divided into a second area arranged side by side in the column direction, and a plurality of areas arranged corresponding to one end of each block in the row direction in the first area. A plurality of first sub-row decoders, a first main row decoder arranged at one end of the first region in the row direction, and a first sub-row decoder corresponding to one end of each block in the second region in the row direction. A plurality of second sub-row decoders arranged, a second main row decoder arranged at one end of the second region in the row direction, and a gap between the first region and the second region. A first column selector disposed at one end in the column direction of the first region and a second column selector disposed at one end in the column direction of the second region; A sense amplifier disposed between the second column selectors; and a booster circuit that boosts a read operation voltage supplied from an external power supply and generates a write / erase voltage. Contract
4. The semiconductor memory device according to claim 1.