JPH053481A - Serial multiplex communication system - Google Patents

Abstract

PURPOSE:To improve the data communication efficiency and to simplify the system in the communication between plural computers within a narrow range such as an automobile body. CONSTITUTION:This system consists of a bus communication line B, an interface C and a communication controller sending a data frame. Each interface C is provided with a synchronizing signal generating circuit E to generate a synchronizing signal being a reference signal for reading a data, a output shift register F and an input shift register H outputting and inputting a serial data, and a control means K which controls writing of a data comprising the synchronizing signal and an output data from the output shift register to the prescribed location of a data frame and of reading of an input data from the input shift register by using the synchronizing signal located in the just preceding position of the data at a prescribed location of the data frame. The data write/read control is implemented based on the data location on the data frame.

Description

Detailed Description of the Invention

[0001]

BACKGROUND OF THE INVENTION 1. Field of the Invention The present invention relates to a communication system for efficiently performing data communication between a plurality of computers through a communication path having a communication distance short enough to ignore communication delay with respect to communication speed.

[0002]

2. Description of the Related Art In recent years, electronic control by a computer has been developed and adopted for controlling various devices in an automobile. And to realize the electronic control, engine ignition timing control, fuel injection control, automatic shift control, brake control,
It covers various areas such as steering control, suspension control, air conditioning control, and self-diagnosis. For this reason, since the processing capacity of one computer is insufficient, one computer is used for each controlled object and dedicated.

[0003]

However, a plurality of computers often use common data such as engine speed, vehicle speed, temperature, steering angle and brake. Therefore, in such a case, if independent computer systems are configured, there are drawbacks in that the sensors are redundantly wasted and that the load distribution of the computer is not properly performed.

Further, control of automobiles tends to require precision and high speed. In such a case, it becomes necessary to organically connect a plurality of computers to carry out. Therefore, if the plurality of computers respectively perform one-to-many communication with each other and perform control while exchanging data, the above-mentioned drawbacks can be solved and the above-mentioned request can be dealt with.

However, a LAN in the general communication field
It is unsuitable to apply the method of (1) as it is to a communication system of an automobile because the system becomes large-scale. Therefore, some communication systems for automobiles have been proposed in consideration of the peculiarities of automobiles. Among these proposals, relatively high-speed communication (1
CA as a serial communication method realizing Mbits / sec)
There is N (CONTROLLER AREA NETWORK).

However, according to the conventional proposals such as CAN, with one exception, one node occupies one data frame. In this method, when a large amount of data is sent out simultaneously at each node, the data address and other control signals are smaller than the actual data, but in the case of an automobile, the number of data sent out simultaneously at each node is 1 In many cases, the number of data on each data frame is about 2, because LATENCY (the delay time from the data transmission request to the end of actual data transmission) is desired to be as small as possible. At this time, the data communication efficiency (actual data communication amount / total communication amount) becomes low.

On the other hand, as in Japanese Patent Application No. 61-101583, a method of increasing data communication efficiency by carrying out communication by placing data of a plurality of nodes on one data frame, a so-called time slot method has been proposed. , This method was only applicable to ring-shaped networks.

The present invention has been made from such a viewpoint, and an object thereof is to enable a plurality of computers to communicate with each other, have high data communication efficiency, and have a narrow range in an automobile or the like. It is to realize a convenient communication system applicable to a bus-shaped network for control.

[0009]

According to the present invention, there is provided a bus-like communication path for performing data communication between a plurality of computers, and an input device arranged between the communication path and the computer for controlling input / output of data between them. It is a serial multiplex communication system that consists of an output interface and transmits / receives data between input / output interfaces by putting data in each time slot of a data frame transmitted on the transmission path or by capturing data from each time slot. Each I / O interface has a sync signal generation circuit that generates a sync signal that serves as a reference when another I / O interface takes in data from each time slot of the data frame, and serial data in a predetermined time slot of the data frame. An output shift register for loading and a predetermined time slot of the data frame The input shift register that captures serial data from the device, the monitor circuit that detects each time slot of the data frame by detecting the start signal of the data frame and the synchronization signal output by other input / output interfaces, and the detection result by the monitor circuit Based on the above, when it is determined that the time slot has reached the predetermined time slot assigned as the transmission source of its own input / output interface, the synchronization signal from the synchronization signal generation circuit and the output shift register If it is determined that the time slot has reached a predetermined time slot assigned as a reception source of its own input / output interface, based on the detection result of the monitor circuit , From that time slot to the previous sync signal By, and having a control means for controlling capture serial data to the input shift register.

[0010]

The communication distance is considered to be at most 20 m for communication in a narrow range such as in the car body, so the communication delay during this period is about
It is 100ns. On the other hand, in the in-vehicle communication, since the communication data amount is relatively small, the communication speed is generally 1 Mbits / sec or less. Therefore, even considering the maximum speed of 1 Mbits / sec,
The communication delay is 1/10 of one data cycle, which is a negligible range. That is, it can be said that the data on the communication path are recognized almost simultaneously by the respective input / output interfaces.

The data frame is generated after the channel has been idle for a certain period of time. The data frame has at least a start signal indicating the beginning of the data frame. There may be a plurality of data frames, but when a plurality of data frames are provided, a data frame address for identifying the data frame is provided after the start bit. Each data is carried in each time slot of the data frame, and each data is transmitted through the communication path. Each time slot has a type of data to be put in the time slot, one input / output interface of a sender that can put the data in the time slot, and one of a receiver that should receive the data from the time slot or A plurality of input / output interfaces are assigned in advance for each time slot.

Therefore, since each input / output interface knows which time slot (which position on the data frame) of each data frame should be loaded, or from which time slot the data should be fetched. If the time slot on the data frame can be identified, necessary data transmission and reception are executed according to the preset logic.

Each time slot on the output data frame of data is formed by the source input / output interface that places the data in that time slot. For example, the input / output interface that should put data in the first time slot detects the start signal of the data frame by the monitor circuit, and from the timing after the predetermined clock after the detection of the start signal,
That is, in the first time slot, the synchronization signal and the serial data from the output shift register are output as one set of data. In this way, the synchronization signal and the predetermined data are carried in the first time slot.

The monitor circuit of each input / output interface is
The time slot number can be determined by constantly monitoring the start signal and the synchronization signal on the communication path and counting the number of occurrences of the synchronization signal with the start signal as the reset signal. And each input / output interface is
Based on the detected time slot, when the time slot reaches the time slot allocated so that its input / output interface becomes the data source, the synchronization signal and the time slot are added as described above. The power data is set as a set of serial data and placed in the time slot.

The synchronization signal comes at the beginning of the time slot except for bit synchronization. If the current time slot detected by the monitor circuit is the time slot immediately before the time slot to which the input / output interface of its own should be the source, resynchronize with the sync signal of the current time slot,
The number of bits is measured for the data length of each time slot that is known in advance, and the beginning of the next time slot is detected. At this leading detection timing, the synchronizing signal generating circuit outputs the synchronizing signal, and the output shift register continuously outputs the serial data based on the clock resynchronized with the synchronizing signal.

In this way, each input / output interface detects the time slot which the input / output interface of its own should be the source and puts the synchronization signal and the serial data in the time slot.

On the other hand, when it is determined that the time slot has reached the time slot in which its own input / output interface should receive the data, based on the time slot detected by the monitor circuit, the data is input from the time slot. , Each bit of serial data is fetched into the input shift register by resynchronizing with the synchronization signal at the head.

In the communication system of the present invention, each data on the data frame is read based on the immediately preceding sync signal, so that the communication delay between the data transmission node (the input / output interface is called a node) and the data read node is canceled. Therefore, it is possible to set the communication speed to 1 Mbits / sec or more and to apply it to a communication system having a longer communication distance. Further, although a synchronization signal is required for each data, a high data communication efficiency can be obtained because a data address is unnecessary. Further, since the generation of the data frame is centrally controlled, the communication system is basically free from data collision.

[0019]

EXAMPLES The present invention will be described below based on specific examples. (1) Overall Configuration FIG. 1 shows the overall configuration of this system. The system is a communication system between a plurality of computers A ₁ to A _n, a bus-like communication path B to perform data communication among a plurality of computers A ₁ to A _n, the communication path B and the computer It comprises input / output interfaces C _{1 to} C _n that are arranged and control data input / output between them, and a communication control device D that controls generation of data frames on the communication path B.

FIG. 2 is a block diagram showing the configuration of the input / output interface C. The input / output interface C generates a synchronization signal generation circuit E that generates a synchronization signal that serves as a reference when data is read by another input / output interface, a start signal of a data frame on the communication path B, a data frame address, and a synchronization signal. A monitor circuit G for monitoring, an input shift register H for inputting serial data from a predetermined position of a data frame on the communication path B based on a sync signal immediately before the data, and a computer A.
An output buffer register I for temporarily storing communication data from the computer, an input buffer register J for temporarily storing communication data to the computer A, and a control circuit K.

FIG. 3 is a block diagram showing the configuration of the communication control device D. When the communication control device D detects that the monitor circuit L that monitors the state of the communication path B and the monitor circuit L that the communication path B has been in an idle state for a certain period of time, the communication control device D receives this and communicates a start signal of the data frame. Start signal generation circuit M to be sent to path B
And a control circuit O for outputting a data frame address for identifying a data frame following a start signal.

At the time of data transmission, the input / output interfaces C _{1 to} C _n write a pair of the synchronization signal and the transmission data at a predetermined position of the data frame generated by the communication control device D and transmitted to the communication path B, and At the time of data reception, the sync signal immediately before the data is read from a predetermined position of the data frame as a reference. The system is configured as described above.

(2) Types of Communication Data and Frame Structure The types of data transmitted in this communication system are assumed to be 25 data shown in FIG. 9 for the sake of explanation. These data require a communication frequency of 1 ms or less and 2
Some require a communication frequency of ms or less. Therefore, if there are two types of data frames, data that requires a communication frequency of 1 ms or less is placed on both data frame 1 and data frame 2, and the data that requires a communication frequency of 2 ms or less is used. Communication is performed by placing only one data frame. This allocation is shown in FIG.

FIG. 7 shows the structure of a data frame. The data frame is composed of a start signal, a data frame address, and 20 sets of sync signal / data pairs. The idle state of the communication path is "1". The start signal is retained for 1.5 bits so that it can be distinguished from the others. Four "0s" and "1s" are alternated in succession (for a total of 6 bits).
It has a special pattern. The data frame address is a signal for distinguishing the data frames, and N
The data frame 1 is indicated by “0” “0” (2 bits) and the data frame 2 is indicated by “0” “1” (2 bits) of the RZ signal. In the present embodiment, the number of data frames is set to 2, so this allocation is performed, but the number of bits and pattern of the data frame address may be changed according to the type of data frame. The start signal and the data frame address are generated by the communication control device D.

In this embodiment, the number of data that can be carried in one frame is 20. A sync signal of a special pattern is prefixed for each data. This synchronizing signal suppresses the frequency component of each data to a low level so that each data is NR.
Since this is a Z (NON RETURN TO ZERO) signal, bit synchronization cannot be performed, so this signal is used as a reference for data read timing.

Each read input / output interface uses the rising edge of the synchronization signal as a reference and sets the transmission clock to 2
The first bit of the data after the clock is read, and thereafter, up to the eighth bit is read every clock. At this time, since the synchronization signal and the data are output from the same input / output interface, the communication delay for receiving the synchronization signal and the communication delay for receiving the data are the same at each read input / output interface. The communication delay can be ignored by reading

The data frame length is 228 bits. Even if the transmission interval of the data frame is set to a long transmission clock and 22 clocks are taken, a data communication frequency of 1 ms can be achieved at a clock rate of 250 KHz. On the contrary, even if the amount of data is quadrupled, if the transmission clock rate of 1 MHz is used, the condition of the data communication frequency of 1 ms can be satisfied.

(3) Detailed Configuration of Monitor Circuit As shown in FIG. 4, the monitor circuit G is an edge detection circuit G.
1, a frame detection circuit G2, and an internal timing signal generation circuit G3. The edge detection circuit G1 is a circuit that monitors the signal level on the communication path B and detects the transition timing (edge of the waveform) of the signal level, such as a differentiation circuit. That is, the edge of the signal shown in FIG. 7 is detected, and the detection signal S1 is output to the frame detection circuit G2 and the internal timing signal generation circuit G3 in synchronization with the clock.

The frame detection circuit G2 is an edge detection circuit G.
1, the edge detection signal S1 is input, the signal level of the communication path B is monitored, and the clock signal is input. The clock signal is a square wave signal having a frequency of about 20 pulses per bit. The frame detection circuit G2 measures the duration of the level of the communication path B after the input timing of the edge detection signal S1 by measuring the clock. And
When the same level continues for about 30 clocks (1.5 bits) and the levels alternately appear as "0", "1", "0", and "1" (time t1), as shown in FIG. As described above, the frame start signal S2 is output in synchronization with the clock.
The frame detection circuit G2 includes a counter circuit that counts 30 clocks and a counter circuit that measures the number of times the signal level is inverted.

Further, the internal timing signal generation circuit G3 is
3.5 bits (about 70 clocks) after the input of the frame start signal S2, when the edge detection signal S1 indicating the rising edge is input (time t3), the edge detection signal S1 and the clock are synchronized. Then, the internal timing signal S3 is output (FIG. 7). Next, after the internal timing signal S3 is output, after 11 bits (about 220 clocks), when the edge detection signal S1 indicating the rising edge is input (time equivalent to time t3), The internal timing signal S3 is output in synchronization with the edge detection signal S1 and the clock (FIG. 7). The generation of the internal timing signal S3 is repeatedly executed every time the frame starter signal S2 is detected. The internal timing signal generation circuit G3 uses clocks of about 70 and 220.
It is composed of a counter circuit for counting the number of pieces and a logic circuit (AND circuit or the like) for outputting the internal timing signal S3 in synchronization with the clock.

(4) Detailed Structure of Control Circuit As shown in FIG. 5, the control circuit C is composed of a counter / processing circuit C1, a write / read position data register C2, and an input / output buffer control circuit C3. ing. counter·
In addition to the clock signal, the frame start signal S2 from the frame detection circuit G2 and the internal timing signal S3 from the internal timing signal generation circuit G3 are input to the processing circuit C1. The counter / processing circuit C1 inputs the frame start signal S2 (time t1) to the input shift register H to input the 2-bit data frame address from the communication path B, and the shift register control signal for inputting the data frame address. S4 is output. This is because the number of clocks is counted after the frame start signal S2 is input, and the middle of the bits (0.5th and 1.5th bits:
This is performed by generating a signal for inputting a data frame address at the 10th and 30th clocks). Also, 2 bits (40 clocks) after the input of the frame start signal S2
By counting the clocks, it is determined that the first time slot has been entered (time t2).

The counter / processing circuit C1 is provided with a time slot counter C11 for managing which number of time slots the communication path B is currently at. The time slot counter C11 is updated by 1 every time it counts 11 bits (220 clocks) even after the number of the first time slot is set. The write / read position data register C2 is searched by using the frame address and the value of the time slot counter C11 as an address signal, and the current time slot is a slot for writing (outputting) data or reading data for this input / output interface. It is determined whether (input) slot. The write / read command data is preset in the data register C2 for each frame address and each time slot.

Further, the counter / processing circuit C1 is provided with a span counter C12 for measuring the span of the time slot with a clock. This span counter C1
2 is cleared every time the frame start signal S2 and the internal timing signal S3 are input (time t1 and t3),
Then, the clock is counted.

When it is determined that the current time slot is the data write slot (time t2), the sync signal output control signal S6 is output to the sync signal generation circuit E at a predetermined timing thereafter, and the sync signal is generated. Circuit E to communication path B
A sync signal is output to. This synchronization signal output control signal S
6 is output when the value of the span counter C12 reaches 70 (3.5 bits) in the first time slot (time t3), and in the case of other time slots, The value of the span counter C12 is 220 (1
1 bit) (time t in other frames)
(Equivalent time to 3).

Further, the time slot determination timing t2
At, the input / output buffer control signal S5 is output to the output buffer register I, and the contents of the output buffer register I are loaded into the output shift register F. The output buffer register I has a capacity capable of storing data of the number of frames × the number of data of one frame. The input / output buffer control signal S5 is composed of an address signal composed of a frame address and the value of the time slot counter C11, and a read / write signal. That is,
In this case, the contents of the output buffer register F at the address determined by the frame address and the value of the time slot counter C11 are output to the output shift register F by the read signal.

The output synchronization signal is also detected by the output I / O interface, and the span counter C12 is reset / started in synchronization with the rising edge (t3) of the detected synchronization signal. Then, the shift register control signal S4 for outputting the data bit is output for each of the count values 40, 60, 80 of the span counter C12 (0.5th, 1.5th, 2.5th bit of data). The output shift register F outputs the data to the communication path B bit by bit in synchronization with the signal S4.

When it is determined that the current time slot is the read slot, the shift register control signal S4 for inputting the data bit is output to the input shift register H at the same timing, and the data is transmitted from the communication path B. Input to the input shift register H bit by bit. And
The input / output buffer control signal S5 is output to the input buffer register J at the timing when the input of the predetermined bit of data is completed, and the data is written from the input shift register H to the input buffer register J. The input buffer register J has a capacity capable of storing data of the number of frames × the number of data of one frame. The input / output buffer control signal S5 is composed of an address signal composed of a frame address and the value of the time slot counter C11, and a read / write signal. That is, in this case, the frame address and the time slot counter C1
Input buffer register H of address determined by the value of 1
Then, the contents of the input shift register F are stored by the write signal.

The input / output buffer control circuit C3 inputs the address signal, the R / W signal and the clock signal from the computer A and stores the transmission data output from the computer A at the designated address of the output buffer register I. , A circuit for outputting the data stored in the designated address of the input buffer register J to the computer A. Thus, the computer A is free to read the received data from the predetermined address of the input buffer register J and write the transmission data to the predetermined address of the output buffer register I independently of the transmission / reception timing of the data to / from the communication path B. , It becomes possible to send and receive data to and from other input / output interfaces.

(5) Detailed Structure of Sync Signal Generation Circuit The sync signal generation circuit E is composed of a counter circuit E1 and a tri-state circuit E2, as shown in FIG.
The tri-state circuit E2 keeps the counter circuit E1 during the high level period of the output control signal S7 input from the control circuit C.
The output of the above is connected to the communication path B. The output control signal S7 is obtained by the span counter C12 from 30 clocks (1.5 bits) before (t2) to 30 clocks (1.5 bits) after the time (t3) when the synchronization signal should rise (t4) for a total of 60 times. This signal is high level during the clock (3 bits).

(6) Overall operation of this device The communication control device D confirms that the communication path D is in the idle state, and outputs the start signal and the data frame address to the communication path D as shown in FIG. To do. All the input / output interfaces monitor the signal level of the communication path D, the frame start timing t1 is detected by the detection of the start signal, the data frame address is input, and the frame address of the current frame is determined.

Thereafter, the start timing t2 of the first time slot is determined as described above, and whether the time slot is a write slot or a read slot is determined by referring to the write / read position data register C2. .. The input / output interface that determines that the first time slot is the write slot outputs the synchronization signal shown in FIG. 7 to the communication path D at a predetermined timing.

Further, the contents of the address specified by the frame address of the output buffer register I and the time slot number are loaded into the output shift register F, and the transmission data thereof is output to the transmission path D. Further, all the input / output interfaces receive the synchronizing signal from the transmission path D, reset the span counter C12 in synchronization with the rising edge of the synchronizing signal, and monitor the position in the time slot. In synchronization with the predetermined value of the span counter C12, the input / output interface for transmitting data outputs the transmission data from the output shift register F to the communication path B bit by bit, and the input / output interface for receiving the data is communication. It is read from the path B into the input shift register H bit by bit.

The received data input to the input shift register H is stored in the address specified by the frame address and the time slot number in the input buffer register J. The computer A can transmit predetermined data by writing data to a predetermined address of the output buffer register I without being aware of the communication procedure, and can receive the data only by reading the content of the predetermined address of the input buffer register J. (7) Application to Automotive Control Device Next, a communication system in an automotive control device will be described in which the present system uses three microcomputers and enables data communication between them. As shown in FIG. 8, each microcomputer (hereinafter abbreviated as μc) A ₁ to
A ₃ is connected to each of the input / output interfaces C _{1 to} C ₃ , and these input / output interfaces and communication control device D
Are connected to the communication path B in a bus shape.

ΜcA ₁ is EFI (ELECTRONIC FUELINJECT
ION), ESA (ELECTRONIC SPARK ADVANCE) control computer that receives engine signals related to the engine, such as crank angle signal, intake air amount, accelerator pedal amount, etc. Receives the data required for the control calculation from the computer through the input / output interface C ₁ and calculates the EFI, ES
Control A. Data necessary for another computer is sent out via the input / output interface C ₁ .

ΜcA ₂ is HPS (HYDRO-PNEUMATICSUSPEN
SION) is a computer for controlling the front and rear G,
Receiving a sensor signal related to lateral G or the like suspensions, performs signal processing of these sensors, calculates receives output interface C ₂ data necessary for control computation from another computer, controls the HPS. Data required by another computer is sent out via the input / output interface C ₂ .

ΜcA ₃ is ABS (ANTILOCK BRAKE SYSTE
M) is a computer for controlling TRC (TRANCTION CONTROL SYSTEM), receives sensor signals related to road surface μ, wheel speed, and braking, performs signal processing of these sensors, and performs control calculation from other computers. The necessary data is received and calculated via the input / output interface C ₃ , and the ABS and TRC are controlled. Further, it is sent out via the input / output interface C ₃ which is required in another computer. The types of data transmitted and received by this system are shown in FIG.
And which time slot of which data frame each data is transmitted is shown in FIG.

(8) Modified Example (a) Data Coding The NRZ signal is used for both the frame address data and the data, but in order to improve the reliability of the data, encoding such as Manchester coding is performed. , Bit synchronization may be performed. However, as a matter of course, the reliability of the data increases, but the frequency component increases, so that the upper limit of the communication clock rate decreases.

(B) Modification of the synchronization system The data frame has a structure in which each data is preceded by a synchronization signal. However, by encoding the data frame address and data like Manchester code, bit synchronization is achieved. It is also possible to omit the synchronization signal. However, when reading data with each input / output interface,
The synchronization of the first bit of data is different from the synchronization timing of the preceding bit by the difference of the communication delay, so that it is difficult to increase the clock rate.

(C) Built-in communication control device In the centralized control system for communication, if the master (communication control device) fails, communication becomes impossible. On the other hand, the communication control device D of the present invention
I / O interface C
The circuit scale is very small compared to. Therefore, the reliability of the communication system can be improved by incorporating the function of the communication control device D in each input / output interface and changing the master depending on the situation.

[0050]

The present invention is a system for performing data communication between a plurality of computers by serial transmission via each input / output interface, and the time slot is automatically entered based on the detection result of the monitor circuit. When it is determined that the output interface has reached the predetermined time slot assigned as the transmission source, data including a set of the sync signal from the sync signal generation circuit and the serial data from the output shift register is set to the time slot. Ride
When it is determined that the time slot has reached the predetermined time slot assigned to the input / output interface of its own based on the detection result by the monitor circuit, the time slot is re-established to the immediately preceding sync signal. It is characterized in that the serial data is controlled so as to be synchronously loaded into the input shift register. Therefore, in the system of the present invention, one source and one or more destinations are assigned to each time slot of the data frame in advance, and the data frame includes an address indicating the source and the destination of the data. Since it is not, a lot of data frames can be opened to practical data to be communicated. That is, the substantial amount of data transmission per unit time is improved. Further, since the determination of the time slot in the data frame is performed based on each synchronization signal having a simple bit structure added to each time slot,
Data can be detected even if there is a transmission delay.

[Brief description of drawings]

FIG. 1 is a block diagram showing the overall configuration of the present system.

FIG. 2 is a block diagram showing a configuration of an input / output interface in FIG.

FIG. 3 is a block diagram showing a configuration of a communication control device in FIG.

FIG. 4 is a specific circuit diagram of a monitor circuit in FIG.

5 is a specific circuit diagram of the control circuit in FIG.

6 is a specific circuit diagram of the synchronization signal generation circuit in FIG.

FIG. 7 is an explanatory diagram showing the structure of a data frame.

FIG. 8 is a block diagram showing the configuration of a specific example system.

FIG. 9 is an explanatory diagram showing the relationship between the type of data, the source computer, the destination computer, and the transmission frequency.

FIG. 10 is an explanatory diagram showing allocation of data to each time slot in each data frame.

[Explanation of symbols]

A _1, ... A _n ... Computer C _1, ... C _n ... Input / output interface D ... Communication control device

Claims (1)

Claim: What is claimed is: 1. A bus-like communication path for performing data communication between a plurality of computers, and an input device arranged between the communication path and the computer for controlling input / output of data between them. A serial multiplex communication system comprising an output interface and transmitting / receiving data between the input / output interfaces by putting data in each time slot of a data frame transmitted on the transmission path or by capturing data from each time slot. Wherein each of the input / output interfaces generates a synchronization signal that is a reference when another input / output interface takes in data from each time slot of the data frame;
An output shift register that puts serial data into a predetermined time slot of the data frame, an input shift register that takes in serial data from a predetermined time slot of the data frame, and a start signal of the data frame and another input / output interface A monitor circuit that detects each time slot of the data frame by detecting the generated synchronization signal, and based on the detection result by the monitor circuit, a predetermined time slot assigned a source of its own input / output interface. When it is determined that the time slot has been reached, the time slot is loaded with data that is a set of the sync signal from the sync signal generation circuit and the serial data from the output shift register, and detection by the monitor circuit is performed. Based on the results When it is determined that the mobile slot has reached a predetermined time slot assigned as its reception source by its own input / output interface, the serial data is input again by resynchronizing from the time slot to the previous synchronization signal. A serial multiplex communication system, comprising: a control unit that controls loading into a shift register.