WO2015056291A1

WO2015056291A1 - Control and monitoring signal transmission system

Info

Publication number: WO2015056291A1
Application number: PCT/JP2013/077922
Authority: WO
Inventors: 錦戸憲治
Original assignee: 株式会社エニイワイヤ
Priority date: 2013-10-15
Filing date: 2013-10-15
Publication date: 2015-04-23
Also published as: JPWO2015056291A1; JP5748924B1

Abstract

[Problem] To provide a control and monitoring signal transmission system which allows configuring a desired number of channels in a transmission synchronization scheme. [Solution] In this control and monitoring signal transmission system, a parent station and multiple child stations are connected by a common data signal line, and under the control of a timing signal generated by a timing generation means of the parent station, a transmission signal is transmitted to the common data signal line, said transmission signal comprising multiple transmission data signals which start from the starting point of the beginning or ending of a start signal and have a prescribed time width per period. For each period, the transmission data signals are transmitted as half-duplex transmissions that comprise either a control signal, which is a transmission signal from the parent station, or a monitoring signal, which is a transmission signal received signal which is received by the parent station. Then, taking a prescribed plural number of consecutive periods of the transmission signal as a single unit, arbitrary transmission data signals in that unit are allocated to prescribed channels.

Description

Control and monitoring signal transmission system

The present invention reduces the number of signal lines between a master station connected to a control unit and a plurality of output units and input units, or a plurality of slave stations corresponding to a plurality of controlled devices, and connects them with a common data signal line. In addition, the present invention relates to a control / monitor signal transmission system that transmits data by a transmission synchronization method such as synchronization by a transmission clock signal.

In a control system including a control unit, a plurality of output units and input units, or a plurality of controlled devices, so-called wiring saving, which reduces the number of wirings, is widely implemented. As a general technique for reducing the wiring, a parallel signal and a serial signal are used instead of a parallel connection that directly connects a plurality of output units and input units or signal lines extending from a controlled device to the control unit. The master station and the plurality of slave stations having the conversion function are connected to the control unit, the plurality of output units and the input unit, or the plurality of controlled devices, respectively, and common data between the master station and the plurality of slave stations. A method of exchanging data with a serial signal via a signal line is widely adopted.

Also, a transmission synchronization method such as synchronization with a transmission clock is widely adopted as a method for transferring data using a serial signal, and studies for applying it to various situations have been made. For example, when bit data and word data are transmitted independently, it is necessary to perform transmission using a plurality of logically different transmission paths (channels), but a plurality of channels are also provided in the transmission synchronization method. Techniques for this are being considered.

For example, in the control / monitor signal transmission system disclosed in Japanese Patent Application Laid-Open No. 2002-271878, the first control signal from the control unit to the controlled device is a binary signal having a predetermined pulse width (duty ratio). 2 The control signal is a signal of a predetermined level during a period of a level other than the level of the power supply voltage, the first monitoring signal from the input unit to the control unit is the presence or absence of a current signal, and the second monitoring signal is a frequency signal Thus, two channels can be provided in the transmission synchronization method.

JP 2002-271878 A

However, in the prior art including the control / monitor signal transmission system described above, the limit is to superimpose several kinds of multiplexed signals in one cycle of the transmission clock signal, and the number of channels that can be set is limited.

Therefore, an object of the present invention is to provide a control / monitor signal transmission system capable of setting a desired number of channels in a transmission synchronization method.

In the control / monitoring signal transmission system according to the present invention, the master station and a plurality of slave stations are connected by a common data signal line, and the start signal is controlled under the control of the timing signal generated by the timing generator included in the master station. A plurality of transmission data signals starting from the start or end point and having a predetermined time width as one cycle are continuous. A transmission signal is transmitted to the common data signal line, and from the master station every cycle. The transmission data signal is transmitted as a half-duplex transmission in which only one of a control signal that is a transmission transmission signal and a monitoring signal that is a transmission reception signal received by the master station is transmitted. A plurality of transmission data signals are defined as one unit, and any transmission data signal in the unit is assigned to a predetermined channel.

The slave station may generate a pseudo clock signal synchronized with the timing signal from the start or end of the start signal, and count a transmission address based on the pseudo clock signal. .

The transmission data signal includes a corresponding transmission clock signal, and at least one of the channels is a high-speed transmission channel, and a slave station belonging to the high-speed transmission channel starts from the start or end of the start signal. The transmission address count based on the start address is started, and in one frame period between the start signal and the next start signal, a number smaller than the address count value corresponding to the number of the transmission data signal periods is set to the maximum address count value. The address counter may be provided to exchange data with the master station at a frame period shorter than the one-frame period.

At least one of the channels is a high-speed transmission channel, and a slave station belonging to the high-speed transmission channel is based on a pseudo clock signal synchronized with the timing signal generated by the local station, starting from the start or end of the start signal An address that starts counting transmission addresses and sets a smaller number than the address count value corresponding to the number of transmission data signal periods in one frame period between the start signal and the next start signal as the maximum address count value. A counter may be provided to exchange data with the master station at a frame period shorter than the one frame period.

The terminal according to the present invention has a predetermined time width that starts from the start or end of the start signal under the control of the timing signal generated by the timing generation means of the master station connected to the master station. There are a plurality of transmission data signals in one cycle, and only one of a control signal that is a transmission transmission signal from the master station or a monitoring signal that is a transmission reception signal received by the master station is provided for each cycle. It is connected to a common data signal line through which the transmission data signal is transmitted as a half-duplex transmission. Further, an address setting means for setting the logical address of the own station and an absolute address generation table for calculating an absolute address in the transmission signal corresponding to the logical address are provided. Further, the number of the transmission data signals is counted, and the control data extraction process for extracting the control data superimposed on the transmission data signal at the timing coincident with the data of the own station address, and the input unit at the coincidence timing A slave station input / output unit that performs monitoring data transmission processing to superimpose the monitoring data corresponding to the input signal from the transmission signal as a transmission reception signal, or a slave station output unit that performs the control data extraction processing and the monitoring data transmission Either one of the slave station input units for processing is provided. The address setting means sets the logical address with a plurality of the transmission data signals as a unit.

The terminal according to the present invention generates a pseudo clock signal synchronized with the timing signal from the start or end of the start signal, and counts transmission addresses based on the pseudo clock signal.

The transmission data signal includes a corresponding transmission clock signal, and the terminal according to the present invention starts counting transmission addresses based on the transmission data signal starting from the start or end of the start signal, and the start signal and An address counter having a smaller number than the address count value corresponding to the number of transmission data signals in one frame period between the next start signals, and a frame period shorter than the one frame period Thus, data may be exchanged with the master station.

The terminal according to the present invention starts counting transmission addresses based on the pseudo clock signal starting from the start or end of the start signal, and in one frame period between the start signal and the next start signal, An address counter having a maximum address count value smaller than the address count value corresponding to the number of transmission data signals is provided, and data is exchanged with the master station in a frame period shorter than the one frame period. You may do it.

In the control / monitor signal transmission system according to the present invention, a plurality of transmission data signals are defined as one unit, and any transmission data signal in one unit is assigned to a predetermined channel. It is possible to provide channels.

In addition, the start signal is included in the transmission signal, and the interval between the start signal and the next start signal is defined as one frame period, and for each channel, the slave station repeats the frame period defined for its own channel within the range of one frame period. If the master station and the slave station exchange data of the channel to which the slave station belongs for each unit, high-speed scanning of predetermined data is performed at a frame period shorter than one frame period of the transmission signal. Is possible.

The terminal according to the present invention includes address setting means for setting an address with a plurality of transmission data signals as a unit, and an absolute address generation table for calculating an absolute address in the transmission signal corresponding to the logical address. In the control / monitor signal transmission system, the address can be easily set without being aware of the absolute address.

The control / monitoring signal transmission system and terminal according to the present invention generate a pseudo clock signal synchronized with a timing signal generated by the timing generating means of the master station at the slave station (own station), and the pseudo clock signal. The transmission address can be counted even if the transmission signal includes only the start signal and the transmission data signal does not include the corresponding transmission clock signal. Therefore, the time width of the transmission data signal of the transmission signal can be shortened and the transmission speed can be increased.

1 is a system configuration diagram showing a schematic configuration of a control / monitor signal transmission system according to the present invention. It is a system configuration | structure figure of a master station. It is a block diagram of a slave station input unit in an input slave station belonging to the first channel. It is a figure which shows the absolute address generation table of the input slave station which belongs to the 1st channel. It is a block diagram of a slave station output unit in an output slave station belonging to the first channel. It is a figure which shows the absolute address generation table of the output slave station which belongs to the 1st channel. It is a block diagram of a slave station input unit in an input slave station belonging to the second channel. It is a figure which shows the absolute address generation table of the input slave station which belongs to the 2nd channel. It is a block diagram of a slave station output unit in an output slave station belonging to the second channel. It is a figure which shows the absolute address generation table of the output slave station which belongs to the 2nd channel. It is a block diagram of a slave station input unit in an input slave station belonging to the third channel. It is a figure which shows the absolute address generation table of the input slave station which belongs to the 3rd channel. It is a block diagram of a slave station output unit in an output slave station belonging to the third channel. It is a figure which shows the absolute address generation table of the output slave station which belongs to the 3rd channel. It is a schematic diagram of the 1st channel data extracted from the transmission signal transmitted / received between a main | base station and a sub_station | mobile_unit, and a transmission signal. It is a schematic diagram of the 2nd channel data extracted from the transmission signal transmitted / received between a main | base station and a sub_station | mobile_unit, and a transmission signal. It is a schematic diagram of the 3rd channel data extracted from the transmission signal transmitted / received between a main | base station and a sub_station | mobile_unit, and a transmission signal. It is a schematic diagram of the transmission signal which shows the frame period of each channel. It is a time chart of a transmission signal. It is a time chart of other embodiments of a transmission signal. It is a time chart of further another embodiment of a transmission signal. It is a block diagram of the slave station input part in the input slave station of other embodiment. It is a block diagram of the slave station output part in the output slave station of other embodiment.

An embodiment of a control / monitor signal transmission system according to the present invention will be described with reference to FIGS.
As shown in FIG. 1, the control / monitor signal transmission system includes a single master station 2 connected to a control unit 1 and common data signal lines DP and DN (hereinafter also referred to as transmission lines), First CH I / O slave station 4a, first CH output slave station 6a, second CH output slave station 6b, third CH output slave station 6c, and first CH input slave station 7a, second CH connected to the common data signal lines DP and DN It is composed of a plurality of input slave stations 7b and a third CH input slave station 7c. In FIG. 1, for convenience of illustration, each slave station is shown one by one, but there is no limitation on the type and number of slave stations connected to the common data signal lines DP and DN.

First CH I / O slave station 4a, first CH output slave station 6a, second CH output slave station 6b, third CH output slave station 6c, first CH input slave station 7a, second CH input slave station 7b, third CH input slave station 7c Performs either or both of signal output processing for the output unit 8 that operates in response to an output instruction of the control unit 1 and input signal processing from the input unit 9 that incorporates input information to the control unit 1. And it is classified into three groups by the transmission data according to the purpose of use. Specifically, the first CH input / output slave station 4a, the first CH output slave station 6a, and the first CH input slave station 7a are connected to the low-speed data transmission group in which low-speed data transmission is performed. The slave station 7b is classified into a high-speed data transmission group in which high-speed data is transmitted, and the third CH output slave station 6c and the third CH input slave station 7c are classified into word data transmission groups in which a plurality of bits of word data are transmitted. The transmission data signals allocated to the low-speed data transmission group, the high-speed data transmission group, and the word data transmission group are referred to as a first channel (first CH), a second channel (second CH), and a third channel (third CH), respectively. In the following description, the parts corresponding to these groups are denoted by “first CH”, “second CH”, and “third CH”, respectively.

The output unit 8 is, for example, an actuator, a (stepping) motor, a solenoid, a solenoid valve, a relay, a thyristor, or a lamp. The input unit 9 is, for example, a reed switch, a micro switch, a push button switch, a photoelectric switch, various sensors, or the like. It is. The first CH input / output slave station 4a is connected to the controlled device 5 including the output unit 8 and the input unit 9, and the first CH output slave station 6a, the second CH output slave station 6b, and the third CH output slave station 6c are output. The first CH input slave station 7 a, the second CH input slave station 7 b, and the third CH input slave station 7 c are connected only to the input unit 9. The first CH output slave station 6a, the second CH output slave station 6b, and the third CH output slave station 6c may include the output unit 8 (output unit integrated slave station 80). 7a, the second CH input slave station 7b, and the third CH input slave station 7c may include the input unit 9 (input unit integrated slave station 90).

The control unit 1 is, for example, a programmable controller, a computer, and the like, and includes a first CH output unit 11a, a second CH output unit 11b, a second CH output parallel data 13c, a second CH control parallel data 13b, and a third CH control parallel data 13c. The 3CH output unit 11c, the first CH input / output slave station 4a, the first CH input slave station 7a, the second CH input slave station 7b, and the first data obtained based on the monitoring data extracted from the monitoring signals from the third CH input slave station 7c. It has a first CH input unit 12a, a second CH input unit 12b, and a third CH input unit 12c that receive the 1CH monitoring parallel data 14a, the second CH monitoring parallel data 14b, and the third CH monitoring parallel data 14c. The first CH output unit 11a, the second CH output unit 11b, the third CH output unit 11c, the first CH input unit 12a, the second CH input unit 12b, and the third CH input unit 12c are connected to the master station 2.

As shown in FIG. 2, the master station 2 includes a first CH output data unit 21a, a second CH output data unit 21b, a third CH output data unit 21c, a timing generation unit 23, a master station output unit 24, a master station input unit 25, A first CH input data unit 26a, a second CH input data unit 26b, and a third CH input data unit 26c are provided. The control signal, which is connected to the common data signal lines DP and DN and is a series of pulse signals, is sent to the common data signal lines DP and DN, and the first CH input / output slave station 4a, the first CH input slave station 7a, The first CH monitoring parallel data 14a, the second CH monitoring parallel data 14b, and the third CH monitoring parallel data 14c extracted from the monitoring signals transmitted from the second CH input slave station 7b and the third CH input slave station 7c are used as the first CH of the control unit 1. The data is sent to the input unit 12a, the second CH input unit 12b, and the third CH input unit 12c.

The first CH output data unit 21a delivers the first CH control parallel data 13a from the first CH output unit 11a of the control unit 1 to the master station output unit 24 as serial data. The second CH output data unit 21b delivers the second CH control parallel data 13b from the second CH output unit 11b of the control unit 1 to the master station output unit 24 as serial data. The third CH output data unit 21c delivers the third CH control parallel data 13c from the third CH output unit 11c of the control unit 1 to the master station output unit 24 as serial data.

The timing generation unit 23 includes an oscillation circuit (OSC) 31 and a timing generation unit 32. The timing generation unit 32 generates a timing clock of the system based on the oscillation circuit (OSC) 31, and generates a master station output unit 24, Delivered to the station input unit 25.

The master station output unit 24 includes control data generation means 33 and a line driver 34. Based on the data received from the first CH output data unit 21a, the second CH output data unit 21b, the third CH output data unit 21c, and the timing clock received from the timing generation unit 23, the control data generation means 33 passes through the line driver 34. The transmission signal is sent to the common data signal lines DP and DN.

The transmission signal is composed of a plurality of transmission data signals. The transmission data signal has a potential level area (corresponding to the transmission clock signal corresponding to the transmission data signal of the present invention, +24 V in this embodiment) higher than the threshold Vst (18 V in this embodiment) of the transmission clock signal and the transmission clock. It is composed of a potential level area lower than the signal threshold Vst. A potential level area lower than the threshold Vst of the transmission clock signal corresponds to a control signal or a monitor signal, and a potential level area (+12 V in this embodiment) higher than the threshold Vlt of logic data (6 V in this embodiment). Or a potential level area (0 V in this embodiment) lower than the threshold value Vlt of the logical data. The logical data of the control signal or the logical data of the monitoring signal is represented by whether the potential level in the potential level area lower than the threshold value Vst of the transmission clock signal is higher or lower than the threshold value Vlt. In this embodiment, a potential level lower than the threshold Vlt (0 V in this embodiment) represents the logical data “1”, and a potential level higher than the threshold Vlt (12 V in this embodiment) represents the logical data “0”. However, the potential level representing each logical data is the value of each data of the first CH control parallel data 13a, the second CH control parallel data 13b, and the third CH control parallel data 13c input from the control unit 1, or the first CH input / output. As long as it corresponds to the data of each monitoring signal transmitted from the slave station 4a, the first CH input slave station 7a, the second CH input slave station 7b, and the third CH input slave station 7c, there is no limitation on the size thereof. You can decide. Furthermore, the transmission signal has a start signal ST at the head having a potential level that is longer than the time width of the transmission data signal and higher than the threshold value Vst of the transmission clock signal.

The first CH input / output slave station 4a, the first CH output slave station 6a, the first CH input slave station 7a, the second CH output slave station 6b, the second CH input slave station 7b, the third CH output slave station 6c, and the third CH input slave station In both cases, power is obtained from the external common power supplies VP and VN.

As shown in FIG. 18, the number of transmission data signals constituting one frame period is 768, and the absolute address is 767 because the start address is 0. Also, transmission data signals of 6-interval absolute addresses (# 0, # 6, # 12...) From 0 to 762 and 6-interval absolute addresses (# 1, # 7, # 13...) From 1 to 763 are present. Transmission of 6-interval absolute addresses (# 2, # 8, # 14 ...) from 2 to 764 and 6-interval absolute addresses (# 3, # 9, # 15 ...) from 3 to 765 to the first channel The data signal is sent to the second channel at 6-interval absolute addresses from 4 to 766 (# 4, # 10, # 16...) And 6-interval absolute addresses from 5 to 767 (# 5, # 11, # 17...). ) Is assigned to the third channel. A transmission data signal assigned to the first channel, a transmission data signal assigned to the second channel, and a plurality of transmission data signals assigned to the third channel (six transmission data signals in this embodiment) are consecutive. This is a unit of the present invention.

The master station input unit 25 includes monitoring signal detection means 35, first CH monitoring data extraction means 36a, second CH monitoring data extraction means 36b, and third CH monitoring data extraction means 36c. The monitoring signal detection means 35 is transmitted from the first CH input / output slave station 4a, the first CH input slave station 7a, the second CH input slave station 7b, and the third CH input slave station 7c via the common data signal lines DP and DN. Detect supervisory signals. As described above, the data of the monitoring signal is expressed as logical data at a potential level lower and higher than the threshold value Vlt. After the start signal ST is transmitted, the first CH input / output slave station 4a and the first CH A monitoring signal is received from each of the input slave station 7a, the second CH input slave station 7b, and the third CH input slave station 7c. Then, the monitoring signal detected by the monitoring signal detection means 35 is delivered to the first CH monitoring data extraction means 36a, the second CH monitoring data extraction means 36b, and the third CH monitoring data extraction means 36c.

The first CH monitoring data extracting unit 36a extracts the first CH monitoring data in synchronization with the timing from the timing generating unit 32, and sends it to the first CH input data unit 26a as serial input data.

The second CH monitoring data extracting means 36b extracts the second CH monitoring data in synchronization with the timing from the timing generating means 32, and sends it to the second CH input data section 26b as serial input data.

The third CH monitoring data extracting unit 36c extracts the third CH monitoring data in synchronization with the timing from the timing generating unit 32, and sends it to the third CH input data unit 26c as serial input data.

The first CH input data unit 26a converts the serial input data received from the first CH monitoring data extraction unit 36a into parallel data, and sends it to the first CH input unit 12a of the control unit 1 as the first CH monitoring parallel data 14a. To do. Further, the second CH input data unit 26b converts the serial input data received from the second CH monitoring data extracting unit 36b into parallel data, and the second CH input data 12b of the control unit 1 is converted into the second CH monitoring parallel data 14b. To send. Further, the third CH input data unit 26c converts the serial input data received from the third CH monitoring data extracting unit 36c into parallel data, and the third CH input data 12c of the control unit 1 is converted into the third CH monitoring parallel data 14c. To send.

As shown in FIG. 3, the first CH input slave station 7a includes transmission reception means 41, address extraction means 43, first CH monitoring data transmission means 45a, CH number setting means 47, first CH address data storage means 51, first CH final address. An address data storage unit 52 and a first CH slave station input unit 70 a having an input unit 71 are provided. The input slave station 7a of this embodiment includes an MCU which is a microcomputer control unit as an internal circuit, and this MCU functions as the first CH slave station input unit 70a. Calculations and storages necessary for the processing are executed using the CPU, RAM, and ROM included in the MCU. The CPU, RAM, and processing in each processing of each of the above-described units constituting the first CH slave station input unit 70a. The relationship with the ROM is not shown for convenience of explanation.

The transmission receiving means 41 receives the transmission data signal transmitted to the common data signal lines DP and DN via the slave station line receiver 62 and delivers it to the address extracting means 43.

The CH number setting means 47 designates the number of channels to be used, and the set channel number is delivered to the address extraction means 43.

The first CH address data storage means 51 corresponds to the address setting means of the present invention, and designates the logical monitoring address data of the first channel (

1M #

0, 1M # 1, etc. shown in FIG. 15) and is set. The data of the logical monitoring address of the first channel is transferred to the address extracting means 43. The logical monitoring address corresponds to the logical address of the present invention, and the logical control address described later also corresponds to the logical address of the present invention.

The first CH final address data storage means 52 sets the maximum value of the logical monitoring address data of the first channel. The maximum value of the logical monitoring address data of the set first channel is stored in the address extracting means 43. Delivered.

The address extraction means 43 has an absolute address generation table 48 and is based on the data obtained from the CH number setting means 47 at the time of system startup of this embodiment (in this embodiment, the number of channels is 3) as shown in FIG. Addresses are expanded into 6 columns (3 channels and 2 columns for each channel) (S1 shown in FIG. 4). Next, based on the setting data 1M # 127 (maximum value of the logical monitoring address) in the first CH final address data storage unit 52, the logical monitoring addresses are expanded from 1M # 0 to 1M # 127 (S2 in FIG. 4). Then, a predetermined absolute monitoring address corresponding to the data of the logical monitoring address that matches the setting data (data of the logical monitoring address) in the first CH address data storage means 51 is obtained (S3 in FIG. 4).

For example, in the embodiment shown in FIG. 4, since the setting data (logical monitoring address data) of the first CH address data storage means 51 is 1M # 0, 6 intervals from the absolute monitoring addresses # 0, # 6, # 12, # 18 Get the data. Data of a predetermined absolute monitoring address obtained in the absolute address generation table 48 is sequentially delivered to the absolute address counter 44. The absolute address counter 44 counts the number of transmission data signals starting from the end of the start signal ST indicating the start of the transmission signal. The absolute address counter 44 is data of a predetermined absolute monitoring address (# 0, # 6, # 12 in the embodiment shown in FIG. 4) corresponding to the setting data (logical monitoring address data) of the first CH address data storage means 51. , Data at intervals of 6 until # 18) is transmitted to the first CH monitoring data transmitting unit 45a each time, and the first CH monitoring data transmitting unit 45a is validated. Note that the data of a predetermined plurality of absolute monitoring addresses corresponding to the logical monitoring address 1M # 0 obtained from the absolute address generation table 48 is first the absolute monitoring address data handed over to the absolute address counter (shown in FIG. 4). In the embodiment, at the output timing when # 0) coincides with the data of the absolute address counter 44, the data of the next absolute monitoring address (# 6 in the embodiment shown in FIG. 4) is delivered to the absolute address counter 44 and the subsequent absolute Similarly, the monitoring address data is sequentially delivered.

The first monitoring data transmission unit 45a outputs a monitoring signal to the common data signal lines DP and DN via the slave station line driver 72 when it is validated by the address extraction unit 43.

The input unit 71 delivers the monitoring data to the first monitoring data transmission unit 45a based on the input data from the input unit 9.

As shown in FIG. 5, the first CH output slave station 6a includes a transmission receiving means 41, an address extracting means 43, a first CH control data extracting means 46a, a CH number setting means 47, a first CH address data storage means 51, and a first CH final data. A first CH slave station output unit 60 a having address data storage means 52 and output means 61 is provided. Similarly to the first CH input slave station 7a, the first CH output slave station 6a also includes an MCU that is a microcomputer control unit as an internal circuit. This MCU functions as the first CH slave station output unit 60a. The calculations and storages required for the processing are executed using the CPU, RAM, and ROM included in the MCU. The CPU, RAM, and processing in each processing of each of the above-described means constituting the first CH slave station output unit 60a. The relationship with the ROM is not shown for convenience of explanation. In FIG. 5, the same reference numerals are given to substantially the same parts as those of the first CH input slave station 7a, and the description thereof will be simplified or omitted.

The address extracting means 43 of the first CH output slave station 6a also has an absolute address generation table 48, which is based on data obtained from the CH number setting means 47 at the time of system activation in this embodiment (in this embodiment, the number of channels is 3). As shown in FIG. 6, the absolute addresses are expanded into 6 columns (2 channels for each channel with 3 channels) (S1 shown in FIG. 6). Next, based on the setting data 1C # 127 (the maximum value of the logical control address) in the first CH final address data storage means 52, the logical control addresses are expanded from 1C # 0 to 1C # 127 (S2 in FIG. 6). Then, a predetermined absolute control address corresponding to the logical control address data matching the setting data (logical control address data) in the first CH address data storage means 51 is obtained (S3 in FIG. 6).

For example, in the embodiment shown in FIG. 6, since the setting data (logical control address data) of the first CH address data storage means 51 is 1C # 0, there are 6 intervals from absolute control addresses # 1, # 7, # 13, # 19. Get the data. Data of a predetermined absolute control address obtained in the absolute address generation table 48 is sequentially delivered to the absolute address counter 44. The absolute address counter 44 counts the number of transmission data signals starting from the end of the start signal ST indicating the start of the transmission signal. The absolute address counter 44 is data of a predetermined absolute monitoring address corresponding to the setting data (logical control address data) of the first CH address data storage means 51 (# 1, # 7, # 13 in the embodiment shown in FIG. 6). , # 19 at the same time), each time, the transmission reception signal of that cycle is delivered to the first CH control data extraction means 46a. Note that the data of a plurality of predetermined absolute control addresses corresponding to 1C # 0 obtained in the absolute address generation table 48 are first absolute control address data handed over to the absolute address counter (in the embodiment shown in FIG. 6). At the output timing when # 1) coincides with the data of the absolute address counter 44, the data of the next absolute monitoring address (# 7 in the embodiment shown in FIG. 6) is transferred to the absolute address counter 44, and the subsequent absolute monitoring address Data is also delivered sequentially.

The first CH control data extraction means 46a extracts control data from the transmission reception signal delivered from the address extraction means 43. Then, the data is delivered to the output means 61 as the first CH control data.

The output unit 61 converts the first CH control data delivered from the first CH control data extraction unit 46a into parallel data, outputs the parallel data to the output unit 8, and causes the output unit 8 to perform a predetermined operation.

Both the output unit 8 and the input unit 9 having a corresponding relationship are connected to the first CH input / output slave station 4a. Similarly to the first CH output slave station 6a and the first CH input slave station 7a, the first CH input / output slave station 4a also includes an MCU that is a microcomputer control unit as an internal circuit. It functions as the station input / output unit 40a. Similar to the MCU of the first CH slave station output unit 60a and the MCU of the first CH slave station input unit 70a, the computation and storage required in the processing of the first CH input / output slave station 4a are performed by the CPU and RAM of this MCU. And is executed using a ROM. The first CH slave station input / output unit 40a has a configuration in which both the first CH slave station output unit 60a and the first CH slave station input unit 70a are combined, and each component includes the first CH slave station output unit 60a or the first CH slave unit. Since it is the same as the component of the station input part 70a, description is abbreviate | omitted.

Similarly to the first CH input slave station 7a, the second CH input slave station 7b shown in FIG. 7 includes an MCU which is a microcomputer control unit as an internal circuit, and this MCU serves as the second CH slave station input unit 70b. It is supposed to function. As with the MCU of the first CH slave station input unit 70a, the calculations and storages required for the processing of the second CH input slave station 7b are executed using the CPU, RAM and ROM included in this MCU. It has become.

As shown in FIG. 7, the functional configuration of the second CH slave station input unit 70b includes the first CH address data storage unit 51 and the first CH final address data storage unit 52 of the first CH slave station input unit 70a shown in FIG. These are replaced with the second CH address data storage means 53 and the second CH final address data storage means 54, respectively, and the others are the same as the first CH slave station input unit 70a. Therefore, in FIG. 6, the same reference numerals are given to substantially the same parts as the first CH slave station input unit 70a shown in FIG. 3, and the description thereof is simplified or omitted. The second CH monitoring data transmission unit 45b has the same function as the first CH monitoring data transmission unit 45a, and therefore has the same reference numeral, but the name is different for convenience of explanation of the drawing.

The second CH address data storage means 53 corresponds to the address setting means of the present invention, and designates the second channel logical monitoring address (

2M #

0,

2M #

1,

2M #

2, or 2M # 3). Thus, the set data of the logical monitoring address of the second channel is delivered to the address extracting means 43.

In the second CH final address data storage means 54, 2M # 3 is set as the maximum value of the logical monitoring address of the second channel.

The address extraction means 43 of the second CH slave station input unit 70b also has an absolute address generation table 48, and is based on data obtained from the CH number setting means 47 at the time of system activation of the present invention (in this embodiment, the number of channels is 3). As shown in FIG. 8, absolute addresses are developed in 6 columns (3 channels and 2 channels in each channel) (S1 shown in FIG. 8). Next, based on the setting data 2M # 3 (maximum value of the logical monitoring address) in the second CH final address data storage means 54, the logical monitoring addresses 2M # 0 to 2M # 3 are repeatedly expanded (S2 in FIG. 8). ). Then, a predetermined absolute monitoring address corresponding to the data of the logical monitoring address that matches the setting data (data of the logical monitoring address) in the second CH address data storage means 53 is obtained (S3 in FIG. 8).

For example, in the embodiment shown in FIG. 8, since the setting data (logical monitoring address data) in the second CH address data storage means 53 is 2M # 0, absolute monitoring addresses # 2, # 26, # 50, etc., # 2 to # 764 Each predetermined data of 24 intervals is obtained. Data of a predetermined absolute address obtained in the absolute address generation table 48 is sequentially delivered to the absolute address counter 44. The absolute address counter 44 counts the number of transmission data signals starting from the end of the start signal ST indicating the start of the transmission signal. The absolute address counter 44 is a predetermined absolute address data (# 2, # 26, # 50, etc. in the embodiment shown in FIG. 8) corresponding to the setting data (logical monitoring address data) of the second CH address data storage means 53. Each time, the transmission transmission signal of that cycle is handed over to the second CH monitoring data transmission means 45b at a timing that coincides with the predetermined data of 24 intervals from # 2 to # 764, and the second CH monitoring data transmission means 45b is made effective. To do. The data of a predetermined plurality of absolute addresses corresponding to 2M # 0 obtained in the absolute address generation table 48 is first the absolute address data handed over to the absolute address counter (# 2 in the embodiment shown in FIG. 8). Is the output timing that coincides with the data of the absolute address counter 44, the data of the next absolute address (# 26 in the embodiment shown in FIG. 8) is delivered to the absolute address counter 44, and the subsequent absolute address data is also sequentially sequentially. Delivered.

Note that the smaller the logical address data set in the second CH final address data storage means 54, the faster the transmission response.

Similarly to the first output slave station 6a, the second CH output slave station 6b also includes an MCU that is a microcomputer control unit as an internal circuit, and this MCU functions as the second CH slave station output unit 60b. It has become. As with the MCU of the first CH slave station output unit 60a, the calculations and storages required for the processing of the second CH output slave station 6b are executed using the CPU, RAM, and ROM included in this MCU. It has become.

As shown in FIG. 9, the functional configuration of the second CH slave station output unit 60b is the same as that of the first CH address data storage unit 51 of the first CH slave station output unit 60a shown in FIG. The 1CH final address data storage means 52 is replaced with the second CH final address data storage means 54, and the rest is the same as the first CH slave station output unit 60a. Therefore, in FIG. 9, the same reference numerals are given to substantially the same parts as those of the first CH output slave station 6a, and the description thereof will be simplified or omitted.

The address extraction means 43 of the second CH slave station output unit 60b also has an absolute address generation table 48, which is based on data obtained from the CH number setting means 47 when the system of the present invention is started (in this embodiment, the number of channels is 3). As shown in FIG. 10, the absolute addresses are expanded into 6 columns (3 channels and 2 columns for each channel) (S1 shown in FIG. 10). Next, the logical control addresses from 2C # 0 to 2C # 3 are repeatedly expanded based on the setting data 2C # 3 (the maximum value of the logical monitoring address) in the second CH final address data storage means 54 (S2 in FIG. 10). ). Then, a predetermined absolute address corresponding to the logical control address data matching the setting data (logical control address data) in the second CH address data storage means 53 is obtained (S3 in FIG. 10).

For example, in the embodiment shown in FIG. 10, since the setting data (logical control address data) of the second CH address data storage means 53 is 2C # 0, absolute control addresses # 3, # 27, # 51, etc., # 3 to # 765 Each predetermined data of 24 intervals is obtained. Data of a predetermined absolute address obtained in the absolute address generation table 48 is sequentially delivered to the absolute address counter 44. The absolute address counter 44 counts the number of transmission data signals starting from the end of the start signal ST indicating the start of the transmission signal. The absolute address counter 44 is a predetermined absolute address data (# 3, # 27, # 51, etc. in the embodiment shown in FIG. 10) corresponding to the setting data (logical control address data) of the second CH address data storage means 53. Each time, a transmission reception signal of that cycle is delivered to the second CH control data extraction means 46b at a timing that coincides with (predetermined data of 24 intervals from # 3 to # 765). The data of a predetermined plurality of absolute addresses corresponding to 2C # 0 obtained in the absolute address generation table 48 is first the absolute address data handed over to the absolute address counter (# 3 in the embodiment shown in FIG. 10). Is the output timing coincident with the data of the absolute address counter 44, the data of the next absolute address (# 27 in the embodiment shown in FIG. 10) is delivered to the absolute address counter 44, and the subsequent absolute address data is also sequentially sequentially. Delivered.

Similarly to the first CH input slave station 7a, the third CH input slave station 7c shown in FIG. 11 includes an MCU that is a microcomputer control unit as an internal circuit, and this MCU serves as the third CH slave station input unit 70c. It is supposed to function. Similar to the MCU of the first CH slave station input unit 70a, the computation and storage necessary for the processing of the third CH input slave station 7c are executed using the CPU, RAM, and ROM provided in this MCU. It has become.

The functional configuration of the third CH slave station input unit 70c shown in FIG. 11 also includes the first CH address data storage unit 51 and the first CH final address data storage unit 52 of the first CH slave station input unit 70a shown in FIG. The third CH address data storage means 55 and the third CH final address data storage means 56 are replaced, and the others are the same as the first CH slave station input unit 70a. Therefore, in FIG. 11, parts that are substantially the same as those of the first CH slave station input unit 70a are denoted by the same reference numerals, and description thereof is simplified or omitted. Note that the third CH monitoring data transmission unit 45c has the same function as the first CH monitoring data transmission unit 45a, so that the reference numerals are the same, but the names are different for convenience of explanation of the drawing.

The third CH address data storage means 55 corresponds to the address setting means of the present invention, and designates the third channel logical monitoring address (

3M #

0, 3M # 1, etc. shown in FIG. 12). The data of the logical monitoring address of the three channels is delivered to the address extracting means 43. As shown in FIGS. 17 and 18, the third channel is for transmitting 8 words with one frame period of the transmission signal as one period Twc. The third CH address data storage means 55 is set with the logical monitoring address at the head of the word to be exchanged,

3M #

0, 3M # 16, and the like.

The third CH final address data storage means 56 sets the maximum value of the data of the third channel logical monitoring address. The maximum value of the set third channel logical monitoring address data is stored in the address extracting means 43. Delivered.

The address extracting unit 43 of the third CH slave station input unit 70c also has an absolute address generation table 48, and is based on data obtained from the CH number setting unit 47 when the system of the present invention is started (in this embodiment, the number of channels is 3). As shown in FIG. 12, the data of the absolute address is expanded into 6 columns (3 channels and 2 channels for each channel) (S1 shown in FIG. 12). Next, based on the setting data 3M # 127 (the maximum value of the logical monitoring address) in the third CH final address data storage unit 56, the logical monitoring addresses are expanded from 3M # 0 to 3M # 127 (S2 in FIG. 12). Then, a predetermined absolute monitoring address corresponding to the logical monitoring address that matches the setting data (logical control address data) in the third CH address data storage means 55 is obtained (S3 in FIG. 12).

For example, in the embodiment shown in FIG. 12, since the setting data (data of the logical monitoring address) in the third CH address data storage means 55 is 3M # 0, absolute addresses # 4, # 10, etc., at intervals of 6 from # 4 to # 766. Get the data. Data of a predetermined absolute monitoring address obtained in the absolute address generation table 48 is delivered to the absolute address counter 44. The absolute address counter 44 counts the number of transmission data signals starting from the end of the start signal ST indicating the start of the transmission signal, and outputs predetermined absolute monitoring address data (corresponding to the setting data in the third CH address data storage means 55). In the embodiment shown in FIG. 12, the transmission transmission signal of that cycle is handed over to the third CH monitoring data transmission means 45c each time at a timing that coincides with data of 6 intervals from # 4 to # 766), and the third CH monitoring data transmission means Enable 45c. Note that the data of a plurality of predetermined absolute monitoring addresses corresponding to 3M # 0 obtained in the absolute address generation table 48 is first the absolute monitoring address data handed over to the absolute address counter (in the embodiment shown in FIG. 12). At the output timing when # 4) coincides with the data of the absolute address counter 44, the data of the next absolute address (# 10 in the embodiment shown in FIG. 12) is transferred to the absolute address counter 44, and the data of the subsequent absolute monitoring address Are also delivered sequentially.

Similarly to the first output slave station 6a, the third CH output slave station 6c includes an MCU which is a microcomputer control unit as an internal circuit, and this MCU functions as the third CH slave station output unit 60c. It has become. As with the MCU of the first CH slave station output unit 60a, the calculations and storages required for the processing of the third CH output slave station 6c are executed using the CPU, RAM and ROM included in this MCU. It has become.

As shown in FIG. 13, the functional configuration of the third CH slave station output unit 60c is such that the first CH address data storage unit 51 of the first CH slave station output unit 60a shown in FIG. The final address data storage means 52 is replaced with the third CH final address data storage means 56, and the rest is the same as the first CH slave station output unit 60a. Therefore, in FIG. 13, the same reference numerals are given to substantially the same parts as those of the first CH output slave station 6a, and the description thereof will be simplified or omitted.

The address extraction means 43 of the third CH output slave station 6c also has an absolute address generation table 48, and is based on the data obtained from the CH number setting means 47 when the system of the present invention is started (in this embodiment, the number of channels is 3). As shown in FIG. 14, the data of the absolute address is expanded into 6 columns (3 channels and 2 columns for each channel) (S1 shown in FIG. 14). Next, based on the setting data 3C # 127 (maximum value of the logical control address) in the third CH final address data storage means 56, the logical control addresses are expanded from 3C # 0 to 3C # 127 (S2 in FIG. 14). Then, a predetermined absolute control address corresponding to the logical control address that matches the setting data (logical control address data) in the third CH address data storage means 55 is obtained (S3 in FIG. 14).

For example, in the embodiment shown in FIG. 14, since the setting data (logical control address data) of the third CH address data storage means 55 is 3C # 0, absolute addresses # 5, # 11, etc. Get the data. Data of a predetermined absolute control address obtained in the absolute address generation table 48 is delivered to the absolute address counter 44. The absolute address counter 44 counts the number of transmission data signals starting from the end of the start signal ST indicating the start of the transmission signal, and outputs predetermined absolute control address data (corresponding to setting data in the third CH address data storage means 55). In the embodiment shown in FIG. 14, the transmission reception signal of that cycle is delivered to the third CH control data extraction means 46c each time at a timing that coincides with data of 6 intervals from # 5 to # 767. Note that the data of a predetermined plurality of absolute control addresses corresponding to 3C # 0 obtained in the absolute address generation table 48 are first absolute control address data delivered to the absolute address counter (in the embodiment shown in FIG. 14). At the output timing when # 5) coincides with the data of the absolute address counter 44, the data of the next absolute address (# 11 in the embodiment shown in FIG. 14) is transferred to the absolute address counter 44, and the data of the subsequent absolute control address Are also delivered sequentially.

In this control / monitor signal transmission system, the first and second transmission data signals of one unit starting from the end of the start signal are the first channel, the third and the fourth are the second channel, The fifth and sixth channels are allocated to the third channel. In addition, the first CH logical monitoring addresses 1M # 0 to 1M # 127, or the first CH logical control address 1C are assigned to one unit (hereinafter referred to as one unit of the first CH) of the transmission data signal allocated to the first channel. # 0 to 1C # 127 are assigned. Furthermore, the second CH logical monitoring addresses

2M #

0,

2M #

1,

2M #

2 and 2M # 3 are assigned to one unit (hereinafter referred to as a second CH unit) of the transmission data signal allocated to the second channel. Or the second CH logical monitoring addresses

2C #

0,

2C #

1,

2C #

2 and 2C # 3 are allocated. Furthermore, the third CH logical monitoring addresses 3M # 0 to 3M # 127, or the third CH logical control address are assigned to one unit (hereinafter referred to as a third CH unit) of the transmission data signal allocated to the third channel. 3M # 0 to 3M # 127 are assigned as word addresses.

Any of the first CH logical monitoring addresses 1M # 0 to 1M # 127 is assigned to the first CH input / output slave station 4a belonging to the first channel, and the first CH logical control addresses 1C # 0 to 1C # are assigned to the first CH output slave station 6a. One of the first CH input slave station 7a, one of the first CH logical monitoring addresses 1M # 0 to 1M # 127, and the first CH logical control address 1C # 0 to 1C. Any of # 127 is given. Then, the first transmission data signal of the first CH unit assigned the first CH logical monitoring address assigned to the own station is transmitted, and the second transmission data of the first CH unit assigned the first CH logical control address. Receive a signal. In FIG. 15, the first CH control data is data received by the slave station from the master station at the first CH input / output slave station 4a or the first CH output slave station 6a, and the first CH monitoring data is the first CH input / output slave station 4a. Or the data received by the master station from the first CH input slave station 7a.

Any of the second CH logical control addresses

2C #

0,

2C #

1,

2C #

2, and 2C # 3 is assigned to the second CH output slave station 6b belonging to the second channel, and the second CH input slave station 7b Any one of the second CH logical monitoring addresses

2M #

0,

2M #

1,

2M #

2, and 2M # 3 is assigned. Then, the first transmission data signal of the second CH unit assigned the second CH logical monitoring address assigned to the own station is transmitted, and the second transmission data of the second CH unit assigned the second CH logical control address. Receive a signal. The logical frame period Thc of the second channel is repeated 32 times within one frame period Tc (period from the start signal to the next start signal) of the transmission data signal. On the other hand, the logical frame period of the first channel is equal to one frame period Tc of the transmission data signal. Accordingly, the transmission response speed of the second channel is 32 times the transmission response speed of the first channel.

The start address of the word data (

3C #

0, 3C # 16, etc.) among the third CH logical control addresses 3C # 0 to 3C # 127 is given to the third CH output slave station 6c belonging to the third channel, and the third CH input The start address (

3M #

0, 3M # 16, etc.) of the word data among the third CH logical monitoring addresses 3M # 0 to 3M # 127 is assigned to the slave station 7c. Then, the first transmission data signal of the third CH unit assigned with the third CH logical address assigned to the own station is transmitted, and the second transmission data signal of the third CH unit assigned with the third CH logical control address. Receive.

Note that the order of transmission data signals of one unit starting from the end of the start signal assigned to each channel is in a predetermined arbitrary order (for example, the third and third channels in the first and second, (4th, 1st channel, 5th and 6th, 2nd channel) may be allocated.

In addition, the start of transmission address counting may start from the start of a start signal.

There is no limitation on the logical data expression by the transmission data signal, and an appropriate expression method may be adopted according to the use situation. For example, as shown in FIG. 20, the threshold Vst of the transmission clock signal in the first half of one cycle (this implementation) In the potential level area lower than 18V in the example, the logical data of the control signal or the logical data of the monitoring signal is expressed by the pulse width length lower than the threshold Vlt (6V in this embodiment). It may be a thing. In this embodiment, when one period of the transmission data signal is t0, the length of the pulse width of the potential level lower than the threshold value Vlt is (1/4) t0, and the logical data “1”, (1/2) t0. Represents logical data “0”. However, the pulse width representing each logical data is the value of each data of the first CH control parallel data 13a, the second CH control parallel data 13b, and the third CH control parallel data 13c input from the control unit 1, or the first CH input / output. As long as it corresponds to the data of each monitoring signal transmitted from the slave station 4a, the first CH input slave station 7a, the second CH input slave station 7b, and the third CH input slave station 7c, there is no limitation on the length thereof. You can decide.

Further, as shown in FIG. 21, the one-cycle potential level of the transmission data signal may represent the logical data of the control signal or the logical data of the monitoring signal. In this embodiment, one cycle of the ground level (OV) transmission data signal represents the logical data “1”, and one cycle of the 12 V transmission data signal represents the logical data “0”. However, in this case, there is a transmission data signal in which one cycle of potential (rising or falling) does not appear, so the slave station can count and synchronize the number of transmission data signals. Can not. Therefore, as shown in FIGS. 22 and 23, the slave station is provided with a pseudo timing generation unit 42 and is synchronized with a pseudo timing signal generated internally from the end of the start signal included in the transmission signal. To do. 22 and FIG. 23 are slave stations belonging to the first CH (first CH input slave station 7e, first CH output slave station 6e), but the same applies to the slave stations belonging to the second CH and third CH. . Further, in FIG. 22, in the configuration of the first CH slave station output unit 60e, substantially the same components as those in the first CH slave station output unit 60a shown in FIG. . Similarly, in the first CH slave station output unit 70e shown in FIG. 23, substantially the same parts as those of the first CH slave station output unit 70a shown in FIG.

Similar to the timing generation unit 23 of the master station 2, the pseudo timing generation unit 42 includes an oscillation circuit (OSC) (not shown) and timing generation means. The pseudo timing generation unit 42 is based on the internal OSC starting from the end of the start signal included in the transmission signal. Then, a pseudo timing signal synchronized with the timing clock generated by the timing generator 23 of the master station 2 is generated and delivered to the absolute address counter 44. The timing at which the pulse signal rises or falls in the pseudo timing signal coincides with the potential change in one cycle of the transmission data signal synchronized with the timing clock generated by the master station 2. Therefore, the slave station can grasp the address of the transmission data signal without counting the number of transmission data signals by counting the rise or fall of the pulse of the pseudo timing signal.

As shown in FIG. 21, when a non-return to zero transmission signal is used, one cycle of the transmission data signal may be a time required for the transmission / reception of the signal, and the return to zero as shown in FIG. 19 and FIG. The transmission speed can be increased compared to the case of using the transmission signal of the system. For example, the transmission rate of the transmission signal shown in FIG. 21 is twice as long as one cycle of the transmission data signal is half the length of one cycle of the transmission data signal of the transmission signal shown in FIGS. .

1 Control Unit 2 Master Station 4a First CH I / O Slave Station 5 Controlled

Devices

6a, 6e First CH Output Slave Station 6b Second CH Output Slave Station 6c Third CH

Output Slave Station

7a, 7e First CH Input Slave Station 7b Second CH Input Slave Station 7c Third CH input slave station 8 Output unit 9 Input unit 11a First CH output unit 11b Second CH output unit 11c Third CH output unit 12a First CH input unit 12b Second CH input unit 12c Third CH input unit 13a First CH control parallel data 13b Second channel control parallel data 13c Third channel control parallel data 14a First channel monitoring parallel data 14b Second channel monitoring parallel data 14c Third channel monitoring parallel data 21a First channel output data unit 21b Second channel output data unit 21c Third channel output data unit 23 Timing generation Part 24 Master station output part 25 Part 26a first 1CH input data section 26b first 2CH input data section 26c first 3CH input data unit 31 OSC (oscillation circuit)
32 Timing generating means 33 Control data generating means 34 Line driver 35 Monitoring signal detecting means 36a First CH monitoring data extracting means 36b Second CH monitoring data extracting means 36c Third CH monitoring data extracting means 40a First CH slave station input / output unit 41 Transmission receiving means 42 pseudo timing generating unit 43 address extracting means 44 absolute address counter 45a first CH monitoring data transmitting means 45b second CH monitoring data transmitting means 45c third CH monitoring data transmitting means 46a first CH control data extracting means 46b second CH control data extracting means 46c second 3CH control data extraction means 47 CH number setting means 48 Absolute address generation table 51 First CH address data storage means 52 First CH final address data storage means 53 Second CH address data storage means 54 Second CH final address Less data storage means 55 Third CH address data storage means 56 Third CH final address data storage means 60a, 60e First CH slave station output section 60b Second CH slave station output section 60c Third CH slave station output section 61 Output means 62 Slave station line receiver 70a, 70e First CH slave station input section 70b Second CH slave station input section 70c Third CH slave station input section 71 Input means 72 Slave station line driver 80 Output section integrated slave station 90 Input section integrated slave station

Claims

The master station and multiple slave stations are connected by a common data signal line.
Under the control of the timing signal generated by the timing generating means possessed by the master station, a transmission signal consisting of a plurality of transmission data signals starting from the start or end of the start signal and having a predetermined time width as one cycle is provided. Transmitted to the common data signal line,
In each cycle, the transmission data is transmitted as half-duplex transmission in which only one of a control signal that is a transmission transmission signal from the master station and a monitoring signal that is a transmission reception signal received by the master station is transmitted. Signal is transmitted,
A control / monitoring signal transmission system characterized in that a plurality of the transmission data signals are defined as one unit, and an arbitrary transmission data signal in the unit is allocated to a predetermined channel.
2. The slave station according to claim 1, wherein the slave station generates a pseudo clock signal synchronized with the timing signal from the start or end of the start signal, and counts transmission addresses based on the pseudo clock signal. Control and monitoring signal transmission system.
The transmission data signal includes a corresponding transmission clock signal, and at least one of the channels is a high-speed transmission channel, and a slave station belonging to the high-speed transmission channel starts from the start or end of the start signal. The transmission address count based on the start address is started, and in one frame period between the start signal and the next start signal, a number smaller than the address count value corresponding to the number of transmission data signals is set as the maximum address count value. The control / monitoring signal transmission system according to claim 1, further comprising: an address counter that transmits and receives data to and from the master station in a frame period shorter than the one frame period.
At least one of the channels is a high-speed transmission channel, and a slave station belonging to the high-speed transmission channel starts counting transmission addresses based on the pseudo clock signal, starting from the start or end of the start signal, and the start An address counter having a smaller number than the address count value corresponding to the number of transmission data signals in one frame period between the signal and the next start signal is provided, and is shorter than the one frame period. The control / monitor signal transmission system according to claim 2, wherein data is exchanged with the master station in a frame cycle.
A transmission data signal having a predetermined time width as one cycle, which is started from the start or end of the start signal under the control of the timing signal generated by the timing generation means of the parent station connected to the parent station A half-duplex transmission in which only one of a control signal that is a transmission transmission signal from the master station and a monitoring signal that is a transmission reception signal received by the master station is transmitted in each cycle. Connected to a common data signal line through which the transmission data signal is transmitted,
Address setting means for setting the logical address of the own station;
An absolute address generation table for calculating an absolute address in the transmission signal corresponding to the logical address;
The number of the transmission data signals is counted, and the control data extraction process for extracting the control data superimposed on the transmission data signal at the timing that coincides with the data of the local station address; A slave station input / output unit that performs monitoring data transmission processing that superimposes monitoring data corresponding to an input signal as a transmission reception signal on the transmission signal, or a slave station output unit that performs control data extraction processing and the monitoring data transmission processing One of the slave station input parts to perform
The terminal according to claim 1, wherein the address setting means sets the logical address using a plurality of transmission data signals as a unit.
6. The terminal according to claim 5, wherein a pseudo clock signal synchronized with the timing signal is generated at a start point from the start or end of the start signal, and a transmission address is counted based on the pseudo clock signal.
The transmission data signal includes a corresponding transmission clock signal, and starts counting transmission addresses based on the transmission data signal starting from the start or end of the start signal, and between the start signal and the next start signal An address counter having a maximum address count value that is smaller than an address count value corresponding to the number of transmission data signals in one frame period, and a frame period shorter than the one frame period, The terminal according to claim 5, wherein data is exchanged between the terminals.
Starting from the start or end of the start signal, transmission address counting based on the pseudo clock signal is started, and corresponds to the number of transmission data signals in one frame period between the start signal and the next start signal. An address counter having a smaller number than the address count value to be used as a maximum address count value is provided, and data is exchanged with the master station in a frame period shorter than the one frame period. Terminal.