JPH05347390A - Semiconductor memory and manufacture thereof - Google Patents

Abstract

PURPOSE:To suppress a parasitic transistor effect and to prevent deterioration of a capacitor insulating film by increasing a width of a groove of a shallow part of a groove formed in a networklike state on a substrate, forming a thick insulating film on a side of the part and forming a storage node in the groove in height lower than an inlet of the groove and lower than a plate electrode. CONSTITUTION:A groove 3' having a first width and a first depth is formed in a groove formed with a capacitor connected to a MOSFET, and a groove 6 having a second width narrower than the first width and a second depth deeper than the first depth is formed, thereby forming a step 6' in the first depth. A capacitor is formed by forming an insulating film 13 inside the groove, removing the film 13 near the step 6' by using a resist pattern, and exposing part of a semiconductor substrate 1. Thereafter, it is connected to the substrate 1 near the step 6'. Thus, the film 13 between a storage node 11 and a plate electrode 14 is not exposed on a surface of the groove, and a breakdown strength between the node 11 and the electrode 14 can be improved.

Description

Detailed Description of the Invention

[0001]

BACKGROUND OF THE INVENTION 1. Field of the Invention The present invention relates to a dynamic RAM having a memory cell composed of a MOSFET and a capacitor.
(DRAM) STRUCTURE AND METHOD FOR MANUFACTURING THE SAME

[0002]

2. Description of the Related Art MOS type DRAMs are becoming more highly integrated and larger in capacity due to miniaturization of elements. High integration,
As a DRAM structure suitable for a large capacity, by forming grooves in a mesh shape on a semiconductor substrate, semiconductor island projections are formed in an array in each memory cell region, and capacitors are formed so as to surround the side surfaces of each island projection. Formed and M on the upper surface of the island-shaped protrusion
Those that form an OSFET have been proposed (eg,
S.Nakajima, K.Miura and T.Morie, IEDM Tech.Diges
t, 1984, pp.240-243). FIG. 38 shows such a DRAM structure.
Shown in.

This conventional DRAM comprises a MOSFET 101 formed on the upper surface of a semiconductor substrate and a capacitor 103 connected thereto. Capacitor 103
Is a groove 10 that is dug to surround the MOSFET 101.
5 is formed inside, and is composed of a plate 107 and a storage node 111 which is in contact with the plate 107 via an insulating film 109. The storage node 111 is connected to the source or drain 113 of the MOSFET 101 at a connecting portion 115. That is, a signal is sent to one of the word lines 119 connected to the gate 117, and information is exchanged with the capacitor 103 via the bit line connected to the contact 121.

In the DRAM structure of FIG. 38, a vertical capacitor is formed on the side surface of the groove, and an element isolation region is also formed in the same place. Therefore, the occupied area of the memory cell can be small and high integration can be achieved. It is possible. Moreover, since the capacitor is formed so as to surround the island-shaped protrusions,
It is possible to earn the maximum capacitor capacity in each memory cell region.

However, in this DRAM structure, the capacitor electrode (storage node) 1 is formed on the side surface of the island-shaped protrusion.
The formation of the parasitic transistor having the gate of 11 has a drawback that the leak current increases.

Further, when the plate electrode 107, the element isolation layer, the FET, etc. are formed, the capacitor insulating film 109 is easily damaged by ion implantation and stress,
There is a problem that the breakdown voltage of the capacitor deteriorates.

Further, in this DRAM structure, the MO
It is necessary to electrically connect the diffusion layer 113 of the source or drain of the SFET and the capacitor electrode 111 formed on the side surface of the island-shaped protrusion, and the manufacturing method of that portion is complicated and difficult.

[0008]

As described above, in the conventional memory cell structure in which the semiconductor island-shaped projections are used to arrange the capacitors on the side surfaces of the island-shaped projections and the MOSFETs on the upper surface, the parasitic transistor is formed. There are problems such as leakage due to the above, deterioration of withstand voltage of the capacitor, and complicated storage electrode forming method.

The present invention has been made to solve such a problem, and an object thereof is to reduce leakage due to a parasitic transistor, to secure the breakdown voltage of a vertical capacitor, and to simplify and shorten the manufacturing process. Another object of the present invention is to provide a DRAM structure and a manufacturing method thereof.

[0010]

A feature of the present invention is that a plurality of semiconductor island-shaped protrusions separated by grooves running on a substrate are provided on a substrate, and a gate electrode of a MOSFET is formed on an upper surface of each of the island-shaped protrusions. Source and drain diffusion layers are formed, and bit lines are connected to one of the diffusion layers,
On the other hand, there is a semiconductor memory device in which a storage node of a capacitor formed inside the groove on the side surface of the island-shaped projection is connected, and a cell plate is formed by filling the groove. The width of the shallow part of the mesh-like groove is increased, and a thick insulating film is formed on the side surface of that part, and the storage node inside the groove is lower than the groove inlet and lower than the plate electrode. It is formed only up to the height. By adopting such a DRAM structure, the above problems can be solved. Also,
Other embodiments include the following.

The electrode of the storage node is the MOSFE
2 to 3 of junction depth of diffusion layer of source or drain of T
Only the depth of more than double is extended inside the groove.

The storage electrode inside the groove is formed lower than the electrode of the cell plate inside the groove.

An insulating film thicker than the inner walls of the other trenches is formed on the inner walls of the trench up to a depth of 3 to 4 times the junction depth of the diffusion layer of the source or drain of the MOSFET.

An insulating film thickness between the cell plate and the side surface of the island-shaped protrusion is thicker at least at a position above the storage node electrode than a capacitor insulating film inside the groove.

The word line structure connected to the gate electrode has a multi-layer structure only on the semiconductor island-shaped protrusions.

The periphery is surrounded by a groove formed on the semiconductor substrate, and a MOSFET is formed in a region separated from the other portion of the surface of the semiconductor substrate by the groove, and the MOSFET is connected to the inside of the groove. A method of manufacturing a semiconductor memory device having a plurality of structures in which a capacitor is formed, wherein the groove is initially formed to have a first width and a first depth, and then a first width smaller than the first width. And a second depth deeper than the first depth, a step is formed at the first depth, and the capacitor forms an insulating film inside the groove. A part of the semiconductor substrate is exposed by removing the insulating film in the vicinity of the step using a resist pattern, and is formed so as to be connected to the semiconductor substrate in the vicinity of the step in which the insulating film is removed. It.

The groove is first formed as a plurality of parallel grooves having the first width and the first depth, a conductive film is formed on the inner walls of the parallel grooves, and then the first groove is formed. And a groove having the first depth and a plurality of grooves extending in parallel at a right angle to the parallel groove having the first depth, and then having the first width and the first depth. Further forming a groove at the bottom of the substrate with the second width and the second depth.

On the semiconductor substrate, an insulating film and a conductive film to be a gate insulating film and a gate electrode of the MOSFET are formed, and then the groove is formed.

[0019]

According to the above structure, the capacitor insulating film between the storage node and the plate electrode is not exposed on the upper surface of the groove and is not easily damaged by ion implantation or the like, so that the breakdown voltage between the storage node and the plate electrode is deteriorated. There is no. Further, not only the capacitor insulating film but also the relatively thick side wall insulating film is formed between the plate electrode near the entrance of the groove and the substrate.
There is no deterioration in breakdown voltage between the plate electrode and the substrate.

Further, according to this structure, the storage node does not extend up to the vicinity of the entrance of the groove, and a relatively thick insulating film exists between the plate electrode and the substrate. The electrode does not act as the gate of the parasitic transistor.

On the other hand, in this structure, since the etching is performed in two steps to form the first and second grooves, a stepped portion (corner portion) of the Si substrate is formed in the middle of the side wall of the groove. Therefore, the thickness of the film formed on the surface is thin at the corner portions, and the corner portions of the substrate are easily exposed during the etch back. Therefore, it is easy to form a direct contact portion between the storage node and the diffusion layer of the source or drain of the FET.

[0022]

DESCRIPTION OF THE PREFERRED EMBODIMENTS FIG. 1 is a plan view showing several bits of the DRAM of the first embodiment. FIG. 15 is a sectional view taken along the line AA ′ of FIG.

2 to 15 are sectional views showing the manufacturing steps of this DRAM. The manufacturing process will be described in detail with reference to FIGS. 2 to 15. First, a multilayer film of a CVD oxide film 1 ′ and a nitride film 2 is deposited as an etching mask on a p-type Si semiconductor substrate 1 and a resist is formed. Anisotropic etching is used to form a first groove 3'having a mesh shape of about 0.5 .mu.m on the substrate to form a plurality of semiconductor island projections in an array (FIG. 2). The inner wall of the groove is oxidized to form an oxide film 4 of about 200 Å, a nitride film 5 of about 200 Å is deposited on the inner wall of the groove, and the side wall is left.
An O film (a composite film of a nitride film and an oxide film) is formed (FIG. 3).

Next, using the oxide film 4 and the nitride film 5 as a mask, the second groove 6 is formed again by anisotropic etching (FIG. 4). At this time, since the second groove 6 has a groove width smaller than that of the first groove 3 ′, the step portion (corner portion) is formed on the Si substrate.
I can do 6 '.

Next, after oxidizing the inner wall 7 of the second groove 6 to some extent, a poly-Si film 8 is formed only about 150 Å only inside the groove (FIG. 5). All of this poly-Si is oxidized to form an oxide film 10 (FIG. 6), the resist 10 'is patterned by photolithography to connect the storage node to the substrate, and a part of the sidewall of the groove is etched by NH ₄ F etching. Oxide film 1
0 is selectively removed to expose the Si substrate (FIG. 7).
After patterning the resist here, the storage node and F
N to connect the source or drain diffusion layer of ET
Type ion implantation may be performed.

Next, a poly-Si film 11 is formed on the inner wall of the groove by about 300Å, and an n-type diffusion layer 12 is formed in the storage node contact portion by ion implantation and a thermal process. However, the poly-Si film 11 is formed at the entrance of the second groove (corner portion 6 ').
It is formed so as to extend up to about 0.1 μm higher so as not to extend to the height of the entrance of the first groove 3 (FIG. 8).

Next, a NO film (a composite film of an oxide film and a nitride film, which serves as a capacitor insulating film) 13 of about 70 Å is formed on the entire surface, poly-Si is buried in the groove, and etched back to form a plate electrode 14. To do. However, this plate electrode is buried and formed up to a position higher than the storage node 11 (FIG. 9). Embedded on the plate electrode 14 or
Alternatively, the oxide film 15 for element isolation is formed by oxidizing poly-Si. The surface of such a substrate is oxidized to form a gate oxide film 16 having a thickness of about 90Å.
An i film 17 is deposited on the order of 1000Å (FIG. 10).

A nitride film 19 is deposited on the poly-Si film 17 through the oxide film 18 having a thickness of about 300 Å to a thickness of about 1000 Å (FIG. 11). After that, the gate poly is patterned and the gate poly is lightly oxidized by heat treatment to form an oxide film 20, and then a nitride film 21 is formed on the side wall to a thickness of about 300 Å. Here, the diffusion layer 22 serving as a source and a drain is formed by ion implantation of N-type impurities (FIG. 12).

Subsequently, a nitride film 23 is formed on the order of 200 Å, an oxide film 24 is formed on the order of 300 Å, and BPSG 25 is formed on the order of 2000.
About Å is deposited (Fig. 13). After that, a contact hole for drawing out a bit line is formed by photolithography using a resist 26 and etching (FIG. 14). B
After the BPSG 25 is flattened by the OX reflow heat treatment, a poly Si film 27 as a bit line and a WSi film 28 of about 500 Å are deposited as bit lines and patterning is performed (FIG. 15).

As described above, the DRAM of the first embodiment
Is completed.

According to the above structure, the capacitor insulating film 13 between the storage node 11 and the plate electrode 14 is not exposed on the upper surface of the groove and is not easily damaged by ion implantation or the like, so that the storage node 11 and the plate electrode 14 are not damaged. There is no deterioration in withstand voltage. In addition, the plate electrode 14 and the substrate 1 near the entrance of the groove
Since not only the capacitor insulating film 13 but also the relatively thick side wall insulating film 5 is formed between them, the plate electrode 1
There is no deterioration in breakdown voltage between the substrate 4 and the substrate 1.

Further, according to this structure, since the storage node 11 does not extend up to the vicinity of the entrance of the groove and a relatively thick insulating film exists between the plate electrode 14 and the substrate 1, the storage node 11 is stored. The node 11 and the plate electrode 14 do not function as the gate of the parasitic transistor.

On the other hand, in this structure, the etching is performed in two steps to form the first and second grooves 3'and 6, so that the stepped portion (corner) of the Si substrate is formed in the middle of the side wall of the groove. Since the portion 6'is formed, the thickness of the film formed on the surface is thin at the corner portion 6'and the substrate corner portion 6'is easily exposed during the etch back. Therefore, the storage node 11 and F
It is easy to form a direct contact portion with the source or drain diffusion layer of ET.

A second embodiment of the DRAM according to the present invention will be described with reference to FIGS.

FIG. 16 shows a second embodiment of the present invention,
FIG. 6 is a plan view of an example showing a number of bits of memory cells laid out by a Folded Bit Line method. FIG. 32 is a cross-sectional view of one memory cell portion showing the configuration of the main part of the present invention, and corresponds to the AA ′ cross section of FIG. 16.

Here, in the second embodiment, the same elements as those in the first embodiment are designated by the same reference numerals.

In FIG. 32, MOSFE is formed on the upper surface of the semiconductor island-shaped protrusions 31 separated by the grooves 30 running like a mesh on the substrate.
A capacitor is formed by the storage node 11 formed with T and surrounding the side surface of the island-shaped projection, and the plate electrode 14 embedded in the groove. Here, the plate electrode 14 is formed to a position higher than the uppermost end of the storage node 11, and the storage node 11 and the plate electrode 14 are formed.
The capacitor insulating film 13 between and is not exposed. Further, in order to suppress the leakage due to the parasitic transistor on the side surface of the island projection, the upper surface of the plate electrode 14 is formed at a position lower than the channel region of the MOSFET on the upper surface of the island projection, and at the same time, a thick insulating film is formed around the upper portion of the island projection. 4 and 5 are formed. Furthermore, a thick element isolation oxide film 15 is formed on the upper part of the groove to protect the storage node 11, the capacitor insulating film 13, and the plate electrode 14 in the groove.

A manufacturing process for realizing the memory cell having such a structure will be described in detail with reference to FIGS.

First, the surface of the p-type semiconductor substrate 1 is oxidized to 9
After forming the gate oxide film 16 of about 0Å, gate poly S
Accumulate about 1000Å of i17. The gate poly-Si is lightly oxidized by heat treatment, and a multilayer film of the nitride film 40 and the CVD oxide film 40 'is deposited. After patterning by photolithography using the resist film 3, anisotropic etching is performed to form a first groove 3 ′ having a mesh shape of about 0.3 to 0.5 μm, and a plurality of semiconductor island-shaped projections 3 are formed.
1 is formed (FIG. 17).

The inner wall of the groove is oxidized to form an oxide film 4 of about 200Å, a nitride film 5 of about 400Å is deposited on the oxide film 4 to leave a side wall, and as a result, about 400Å NO is formed on the inner wall of the groove.
A film is formed (FIG. 18). Next, the second groove 6 is again formed by anisotropic etching using the oxide film 4 and the nitride film 5 as a mask. At this time, the second groove 6 is the first groove 3 '.
Since the groove width is smaller than that, a step portion (corner portion) 6 ′ is formed on the Si substrate (FIG. 19).

The inner wall of the second groove 6 is slightly oxidized to form the oxide film 7, and then the poly-Si film 8 is formed only about 150 Å only inside the groove (FIG. 20). After oxidizing all of this poly-Si and covering the inner wall of the trench with an oxide film, p-type ion implantation is performed at the bottom of the trench for element isolation to form a p ^- type region (FIG. 2).
1).

Next, a resist pattern 44 is formed by photolithography to connect the storage node to the Si substrate, and a part of the oxide film on the side wall of the groove is removed by NH ₄ F etching to expose the Si substrate (see FIG. 22).

Next, about 300Å of n-doped poly-Si is formed on the inner wall of the groove, and n is applied to the storage node contact portion by a thermal process.
A mold diffusion layer 12 is formed. In addition, the bottom of poly-Si is R
The storage node 11 is formed by cutting with the IE. Here, the storage node 11 is formed so as to cover the exposed portion of the Si substrate and extend up to about 0.1 μm higher than the entrance (corner portion 6 ′) of the second groove, and extend to the height of the entrance of the first groove. So that it does not exist (Fig. 23).

Next, after patterning the resist 45, n-type ion implantation is performed to connect the storage node 11 and the diffusion layer of the source or drain of the FET (FIG. 2).
4). However, this ion implantation may be performed after forming the first groove.

Next, after forming an NO film (composite film of oxide film and nitride film) 13 of about 70 Å which becomes a capacitor insulating film on the entire surface, poly Si is filled in the groove, and the upper surface of poly Si is Si.
The plate electrode 14 is formed by etching back so that the plate electrode 14 is lower than the upper surface of the substrate by about 0.1 to 0.2 μm (FIG. 25). In the figure, the oxide film is drawn integrally with the NO film 13.

Further, the exposed surface of the plate electrode 14 is lightly oxidized by heat treatment, and an oxide film 15 for element isolation is formed by BPSG deposition and etch back (FIG. 26). A capacitor could be formed through the above steps. Next, after removing the NO film 13 and the oxide film on the surface of such a base, the WSi film 41, the oxide film 18, and the nitride film 46 are deposited (FIG. 27), and the word line 41 is formed by photolithography and RIE. At the same time, a gate electrode is formed.

Further, the side surfaces of the gate poly-Si are lightly oxidized by heat treatment, N-type diffusion layers 22 serving as a source and a drain are formed on both sides of the gate electrode by ion implantation, and a nitride film 48 is formed on the side wall to a thickness of about 300 Å (FIG. 28).

Subsequently, a nitride film 50 is formed to a thickness of about 200 Å, and then the base is planarized by TEOS oxide film deposition and etch back (FIG. 29). After that, a contact portion for drawing out the bit line is formed by an oxide film etching process by photolithography using the resist pattern 49 (FIG. 30).

Further, the nitride film 50 and the gate oxide film 16 in the contact portion are removed in a self-aligned manner to form a contact hole for drawing out a bit line (FIG. 31). Finally, as a bit line, a poly-Si film 27 of about 500 Å
8 is deposited to about 500 Å and patterned (FIG. 32).

In this structure, since the capacitor portions 11, 13, 14 which are easily damaged during the process are protected by the thick oxide film on the upper portion of the groove, the DRAM having excellent withstand voltage of the capacitor is provided.
The device can be manufactured with high yield. Further, in this embodiment, since the gate oxide film 16 and the gate poly are formed first,
In the final shape, the gate poly exists only on the upper surface of the semiconductor island projection, and only the word line 41 such as WSi is formed on the groove portion in which various electrodes are embedded. Therefore, the load capacitance between the word line, the storage node 11 and the plate electrode can be significantly reduced.

Next, a third embodiment of the present invention is shown in FIG. FIG. 33 is a plan view showing several bits of memory cells laid out by the Folded Bit Line method as in FIG. 16, but in the present embodiment, the storage node contact portion and the bit line lead-out contact portion of adjacent memory cells are connected to each other. They are formed facing each other. In this case, the patterning of the storage node contact portion and the bit line lead-out contact portion can be performed with two adjacent cells as a set, so that a misalignment margin at the time of patterning can be provided.

The fourth embodiment of the present invention is shown in FIGS.
It shows in FIG. FIG. 34 is a plan view showing several bits of memory cells laid out by the Open Bit Line method. Figure 3
35 to 37 corresponding to the AA ′ cross section of FIG.
The manufacturing process of this embodiment will be described. In this embodiment, a poly-Si side wall is used to connect the storage node to the FET source or drain diffusion layer. This sidewall is only on the source / drain part of MOSFET,
Since it is necessary to form the first groove, the present embodiment is characterized in that the first groove is formed twice in the word line direction and the bit line direction. The other conditions are the same as those in the second embodiment unless otherwise specified.

The manufacturing process will be described with reference to FIGS. Here, the same is true up to FIG. 17 of the second embodiment. That is, in FIG. 35, after forming the gate oxide film 16,
After depositing the gate poly Si17 and depositing a multilayer film of an oxide film, a nitride film and a CVD oxide film of an etching mask, a first groove in the word line direction (perpendicular to the paper surface) is formed by anisotropic etching. Next, after depositing poly-Si on the entire surface, it is etched back to form a side wall 50 (FIG. 35). In this state, long island-shaped projections having long sides in the word line direction are formed on the substrate. Further, when the second groove in the bit line direction is formed by anisotropic etching, the poly-Si sidewall 50 is formed.
Can be divided, and the Si side walls 50 that are poly-separated can be left only on both side surfaces of the semiconductor island-shaped protrusions. here,
Similar to the second embodiment, the oxide film 4 and the nitride film 5 are formed on the inner wall of the shallow groove (FIG. 35).

Next, using the oxide film 4 and the nitride film 5 as a mask, a third deep groove is formed by anisotropic etching. After covering the inner wall of the groove with an oxide film, p-type ion implantation is performed on the bottom of the groove for element isolation, and the Si substrate and the poly Si side wall 50 of the storage node contact portion are subjected to photolithography and NH ₄ F etching treatment. Expose.

Next, n-doped poly-Si serving as a storage node
The film 11 is formed on the inner wall of the groove, and the poly-Si sidewall 50 is formed.
Connect to. Since the diffusion rate of the n-type impurity in poly-Si is faster than that in the Si substrate, the n-type impurity diffuses quickly from the connection portion with the storage electrode to the poly-Si sidewall, and as a result, the source or drain of the FET is A conductive layer connecting the diffusion layer and the storage node 11 is formed. An ion implantation method may be used to implant the n-type impurity into the storage node 11. Further, ion implantation may be further performed in a portion connecting the diffusion layer of the source or drain of the FET and the storage node 11. After this, capacitor insulation film 1
3, the plate 14 (the oxide film 42 is formed on the surface), the element isolation oxide film 15 are formed in the same manner as in Example 1, and the WSi film 41, the oxide film 18, and the nitride film 19 are formed on the gate electrode 17. Formed (FIG. 36). Finally, the nitride film 21 on the side wall of the gate electrode is used to form a contact hole for drawing out a bit line in a self-aligned manner, and the poly Si film 27 and the WSi film 28 form a bit line (FIG. 37).

By adopting this structure, the open defect of the storage node contact portion can be significantly reduced, and as a result, the functional yield of the memory cell can be increased by 30%.

[0057]

As described above, if the structure and the manufacturing method according to the present invention are applied to the DRAM cell, the parasitic transistor effect on the side surface of the semiconductor island protrusion, which has been the biggest problem in the past, can be suppressed, and at the same time, the manufacturing can be performed. It is possible to realize a structure that prevents deterioration of the capacitor insulating film that is easily damaged during the process. Since this type of DRAM cell has a shape suitable for high integration, 256M has been solved by solving the above problems.
A large-capacity DRAM having more than one bit can be realized at low cost.

That is, when the structure and the manufacturing method according to the present invention are adopted in the DRAM, the capacitor insulating film between the storage node and the plate electrode is not exposed on the upper surface of the groove,
Since it is less susceptible to damage such as ion implantation, the breakdown voltage between the storage node and the plate electrode is dramatically improved. Since not only the capacitor insulating film but also the relatively thick side wall insulating film is formed between the plate electrode near the entrance of the groove and the substrate, the breakdown voltage between the plate electrode and the substrate is significantly improved. Also, with this structure, the storage node does not extend to the vicinity of the entrance of the groove, and there is a relatively thick insulating film between the plate electrode and the substrate, so the storage node and the plate electrode are parasitic. It does not act as the gate of a transistor.

On the other hand, in this structure, since the etching is performed in two steps to form the groove, a stepped portion (corner portion) of the Si substrate is formed in the middle of the side wall of the groove. At the time of backing, this board corner portion is easily exposed. Therefore, there is a storage node, F
It is easy to form a direct contact portion between the source or drain diffusion layer of ET.

[Brief description of drawings]

FIG. 1 is a plan view of a first embodiment of a DRAM according to the present invention.

FIG. 2 is a cross-sectional view of the manufacturing method of the first embodiment of the DRAM according to the present invention.

FIG. 3 is a cross-sectional view of the manufacturing method of the first embodiment of the DRAM according to the present invention.

FIG. 4 is a sectional view of the manufacturing method of the first embodiment of the DRAM according to the present invention.

FIG. 5 is a cross-sectional view of the manufacturing method of the first embodiment of the DRAM according to the present invention.

FIG. 6 is a cross-sectional view of the manufacturing method of the first embodiment of the DRAM according to the present invention.

FIG. 7 is a sectional view of the manufacturing method of the first embodiment of the DRAM according to the present invention.

FIG. 8 is a sectional view of the manufacturing method of the first embodiment of the DRAM according to the present invention.

FIG. 9 is a cross-sectional view of the manufacturing method of the first embodiment of the DRAM according to the present invention.

FIG. 10 is a sectional view of the manufacturing method of the first embodiment of the DRAM according to the present invention.

FIG. 11 is a cross-sectional view of the manufacturing method of the first embodiment of the DRAM according to the present invention.

FIG. 12 is a sectional view of the manufacturing method of the first embodiment of the DRAM according to the present invention.

FIG. 13 is a sectional view of the manufacturing method of the first embodiment of the DRAM according to the present invention.

FIG. 14 is a cross-sectional view of the manufacturing method of the first embodiment of the DRAM according to the present invention.

FIG. 15 is a sectional view of the manufacturing method of the first embodiment of the DRAM according to the present invention.

FIG. 16 is a plan view of a second embodiment of a DRAM according to the present invention.

FIG. 17 is a sectional view of the manufacturing method of the second embodiment of the DRAM according to the present invention.

FIG. 18 is a cross-sectional view of the manufacturing method of the second embodiment of the DRAM according to the present invention.

FIG. 19 is a cross-sectional view of the manufacturing method of the second embodiment of the DRAM according to the present invention.

FIG. 20 is a sectional view of the manufacturing method of the second embodiment of the DRAM according to the present invention.

FIG. 21 is a cross-sectional view of the manufacturing method of the second embodiment of the DRAM according to the present invention.

FIG. 22 is a sectional view of the manufacturing method of the second embodiment of the DRAM according to the present invention.

FIG. 23 is a sectional view of the manufacturing method of the second embodiment of the DRAM according to the present invention.

FIG. 24 is a sectional view of the manufacturing method of the second embodiment of the DRAM according to the present invention.

FIG. 25 is a cross-sectional view of the manufacturing method of the second embodiment of the DRAM according to the present invention.

FIG. 26 is a cross-sectional view of the manufacturing method of the second embodiment of the DRAM according to the present invention.

FIG. 27 is a cross-sectional view of the manufacturing method of the second embodiment of the DRAM according to the present invention.

FIG. 28 is a cross-sectional view of the manufacturing method of the second embodiment of the DRAM according to the present invention.

FIG. 29 is a sectional view of the manufacturing method of the second embodiment of the DRAM according to the present invention.

FIG. 30 is a sectional view of the manufacturing method of the second embodiment of the DRAM according to the present invention.

FIG. 31 is a cross-sectional view of the manufacturing method of the second embodiment of the DRAM according to the present invention.

FIG. 32 is a sectional view of the manufacturing method of the second embodiment of the DRAM according to the present invention.

FIG. 33 is a plan view of a third embodiment of the DRAM according to the present invention.

FIG. 34 is a plan view of a fourth embodiment of a DRAM according to the present invention.

FIG. 35 is a sectional view of the manufacturing method of the fourth embodiment of the DRAM according to the present invention.

FIG. 36 is a sectional view of the manufacturing method of the fourth embodiment of the DRAM according to the present invention.

FIG. 37 is a sectional view of the manufacturing method of the fourth embodiment of the DRAM according to the present invention.

FIG. 38 is a plan view of a conventional DRAM.

[Explanation of reference numerals] 1 semiconductor substrate 1 ′ CVD oxide film 2, 5, 19, 21, 23, 40, 46, 48, 50
Nitride film 3,10,49 Resist 3'First groove 4,15,18,24 Oxide film 6 Second groove 6'Corner portion 8 Poly Si 11 Storage node 13 NO film 14 Plate electrode 16 Gate oxide film 17 Gate Poly-Si film 22 diffusion layer 25 BPSG 28 WSi 41 word line 50 poly-Si sidewall

Claims (1)

[Claims] 1. A plurality of semiconductor island-shaped protrusions separated by grooves running on a substrate are provided on a substrate, and a diffusion layer for a gate electrode, a source and a drain of a MOSFET is formed on an upper surface of each island-shaped protrusion. The bit line is connected to one of the diffusion layers, and the storage node of the capacitor formed inside the groove on the side surface of the island-shaped protrusion is connected to the other of the diffusion layers, and the cell plate is formed by filling the groove. In the semiconductor memory device in which the groove is formed, the width of the groove near the surface is larger than the width deeper than the surface, and a step is formed between these two widths, and the storage node and the groove are formed. A semiconductor memory device characterized by being connected to a MOSFET in the vicinity of this step.