JPH0534711B2 - - Google Patents

Description

DETAILED DESCRIPTION OF THE INVENTION [Technical Field of the Invention] The present invention relates to an image processing device having a simple and highly practical configuration capable of effectively extracting features of small regions in an image.

[Technical background of the invention and its problems]

When inspecting the particle size or flaws on the surface of an object, image processing is often used to input an image of the object to be inspected and calculate the number of objects to be inspected within a certain area of the image and the total area of the objects to be inspected. used. Conventionally, in order to shorten the processing time in such image processing, the entire area to be inspected is divided into multiple small areas, and predetermined image processing is performed within each small area. There is. but,
Such a processing method is very effective when the inspection target in the image is uniformly distributed over the entire area of the image, but if the distribution is uneven, as shown in Figure 1, for example, If so, the question arises as to which sub-area is to be inspected.

That is, as shown in FIG. 1, focusing on a small area 2 consisting of (m x n) pixels in an inspection target image 1 consisting of (M x N) pixels, the number of scratches 3 within this small area 2 is counted. If the inspection results are obtained using the same method, the number of scratches 3 will vary depending on the setting position of the small area 2, as shown in FIGS. 2a and 2b. For this reason, even though the same image 1 is being processed (inspected), the inspection result may pass or fail, which is extremely inconvenient. For this reason, conventionally, when the inspection targets are unevenly distributed,
It was necessary to perform image processing over the entire area of the target image 1.

[Purpose of the invention]

The present invention was made in consideration of these circumstances, and its purpose is to locally easily and quickly obtain error-free inspection results even for non-uniform images of the inspection target. The object of the present invention is to provide a highly practical image processing device that can perform the following tasks.

[Summary of the invention]

The present invention uses time-series input pixel data obtained by two-dimensionally scanning an image consisting of (M×N) pixels.
×(n-1)} stages, and further delayed by m stages, and the pixel data delayed by (n-1) lines, the current output pixel data, and the added pixel data stored in the M-stage storage means are The summation pixel data of each pixel column extending over (n-1) lines is determined recursively from The feature information (cumulative sum data) of a small area consisting of (m×n) pixels is gradually stored in the cumulative sum register from the summed pixel data of the pixel string extending over (n-1) lines and the m-stage delayed data. It was designed to be obtained chemically.

〔Effect of the invention〕

Therefore, according to the present invention, it is possible to easily and rapidly obtain the cumulative sum data of a small area consisting of (m×n) pixels for an image in a recursive manner. Moreover, by setting the small area positions for the entire area of the image, the cumulative sum data at each position can be determined with high precision. Therefore, information on the image to be processed can be accurately obtained from any small area, and its practical advantage is enormous.

[Embodiments of the invention]

Hereinafter, one embodiment of the present invention will be described with reference to the drawings.

Figure 3 shows the principle of operation in this device, where 1 is an image to be processed consisting of (M×N) pixels;
2 indicates a small area of (m×n) pixels to be subjected to arithmetic processing. Further, 4 indicates time-series pixels obtained by two-dimensionally scanning the small image 1. In addition, 5 in the figure is (n-1) of the above region 6.
Vertical addition data for a line, that is, vertical direction n
This is a virtual representation of the sum of pixel data.
Note that 6 in the figure indicates a partial area consisting of {m×(n-1)} pixels excluding the top line of the small area 3.

Now, here, the cumulative sum 〓 _i-1,j of the small area 2 consisting of (m×n) pixels has already been found, and the data sum S _in,j of each column (vertical direction) in the partial area 6,
It is assumed that S _i-n+1,j to _{S i-1,j} are respectively determined. It is assumed that the next small area 2 to be calculated is shifted to the right by one pixel. In this case, new pixel data d _i,j of (i, j) is input through scanning, and this data is used to calculate the data sum T _i,j of n pixels in that column. Further, from this data sum T _i,j , a sum S _i,j of data for (n-1) pixels excluding the top line is calculated. This calculation is based on (n-1) of the column that has already been found.
This is done by adding the above input pixel data d _i,j to the sum of pixel data S _i,j-1 , and as T _i,j = S _i,j-1 + d _i,j , the n pixels The sum of the data is calculated. Furthermore, the sum S _i,j of data for (n-1) pixels is S _i,j = T _i,j −d _i,j-(o-1) = S _i,j-1 +d _i,j −d It is determined as _i,j-(o-1) . Then, this newly obtained addition data T _i,j is applied to the previously obtained small area 2
In addition to the cumulative sum of _i-1,j , the leftmost column of the previous small area 2 is erased and a new small area 2 is set by shifting it to the right by one pixel.
Sum S _in,j of data in the leftmost column of the partial area 6 and pixel data in the leftmost column and top row of the small area 2
By subtracting d _in,jo-1, a new small area 2 is obtained as 〓 _i,j =〓 _i-1,j +T _i,j −S _in,j −d _in,j-(o-1) The cumulative sum data is obtained. In other words, if the above calculation process is performed each time new pixel data d _i,j is input by two-dimensional scanning of image 1, (m ×n) Small area 2 consisting of pixels
The cumulative sum of can be obtained sequentially at high speed.

FIG. 4 is a schematic diagram of an apparatus according to an embodiment of the present invention that executes image processing in this manner.

Data of an image to be processed consisting of (M×N) pixels temporarily stored in an image memory or the like is two-dimensionally raster scanned by a control device (not shown) and sequentially read out in time series, and the series of input pixel data is read out in sequence.
d _i,j is led to the adder 11 and is divided into {M pixels×
(n-1) line} stage is guided to the shift register 12, which is the first storage means. This shift register 12 is driven for data transfer by the pixel data clock, and is made up of (n-1) shift registers 12a each having one line and M stages connected in series. With this shift register 12, the pixel data is delayed by one line each time it passes through one shift register 12a, that is, the timing is delayed by M pixels. and,
The pixel data delayed through the shift register 12 is guided to the subtracter 13, and the second
is supplied to the storage means (shift register) 14 of
It is designed to be delayed by m pixels.

By the way, M inputs the output of the subtracter 13 as addition data of (n-1) pixels in the vertical direction of the image.
The third storage means (shift register) 15 of the stage is
The added data is transferred in synchronization with the input timing of the image data, delayed by one line, and output. The output data of this shift register 15 is fed back to the adder 11. This adder 11 adds the current input pixel data to the one-line delayed addition data, thereby obtaining vertical addition data T _i,j of n pixels. Then, this addition data T _i,j is led to the subtracter 13, and the (n-1)
The line-delayed pixel data is subtracted and is finally input to the third shift register 15 as addition data of (n-1) pixels. In other words, (n-
1) The previous pixel data of the line is removed, and the new current input pixel data is added, resulting in 1 row in the vertical direction.
The data is input to the shift register 15 as addition data of new (n-1) pixels shifted by the pixel. As a result, new addition data S _i,j of (n-1) pixels are always stored in the shift register 15 in a gradual manner corresponding to the pixel positions.

On the other hand, the vertical addition data T _i,j for n pixels obtained by the adder 11 is led to the adder 16, and
It is added to the output data of the cumulative sum register 17, which is the fourth storage means. Also, shift register 1
The tap output data of the m-th stage of No. 5 is led to a subtracter 18 and subtracted from the output data of the adder 16. Further, a subtracter 19 subtracts the output data of the shift register 14 from the output data of the subtracter 18. The cumulative sum register 17
The data obtained by these adders 16 and subtracters 18 and 19 are expressed as cumulative sum data of (m×n) pixels with the pixel position (i, j) of the current input data as the reference position 〓 _i,j This is stored temporarily.

According to the device configured in this way, first, all shift registers 12, 14, 15, and 17 are set to "0".
After resetting to , two-dimensionally scanned time-series pixel data d _i,j is input. As a result, the pixel data d _i,j are sequentially stored in the shift register 12. At this time, all data sequentially read from the shift register 12 is zero (0).
Therefore, one line of pixel data that is first input is sequentially stored in the shift register 15 as is. Then, the next line (second
When inputting pixel data for a line), the data read out from the shift register 12 is zero (0), and data at the same row address one line before is read out from the shift register 15. The data obtained by adding the pixel data of the first and second lines corresponding to the row address positions is stored in each of them. In this way, (n-1) lines of pixel data are inputted in time series to the shift register 15.
1) Data S _1,o-1 , S _2,o-1 to _{S M,o-1} obtained by adding each line's worth of pixel data in the vertical direction are stored, respectively. Thereafter, from the time when pixel data of the n-th line is input, pixel data delayed by (n-1) lines is read out from the shift register 12. At this time, adder 11
Now, since the current input data d _i,j is added to the output data of the shift register 15, the output is data T _i,j added vertically for n lines. Since the output data from the shift register 12 is subtracted from this data T _i,j by the subtracter 13,
Eventually, the addition data S _i,j for new (n-1) pixels is transferred from the subtracter 13 to the shift register 15 as follows: S _i,j =S _i,j-1 +d _i,j −d _i,j- It will be given as _(o-1) . In other words, the gradual addition data of (n-1) pixels is sequentially stored in the shift register 15.

On the other hand, in the cumulative sum register 17, pixel data _d1,1 is sent to the adders 11,1 as the pixel data is input.
6 and subtractors 18, 19, m
The data is sequentially accumulated until the data for the pixel is input. After that, the cumulative sum of m pixels from which the data of m pixels before is sequentially subtracted is stored. Then, the accumulation process is repeated from the second line to the input of the (n-1)th line. Thereafter, when data for the n-th line is input, the shift register 15 has already stored the addition data S of each n-1 pixel in the vertical direction, and a delayed output can be obtained via the shift register 14. Therefore, when the m-th pixel of the n-th line is input, the cumulative sum 〓 _i,j of the first small area consisting of (m×n) pixels is calculated in the cumulative sum register 17. In other words, the cumulative sum data of the small region 2, which is the cumulative value, is determined according to each vertical addition data T _i,j . Thereafter, each time pixel data is input, the subtracter 18 subtracts the summation data S of the previous (n-1) pixels in the vertical direction, and the subtracter 19 subtracts m pixels (n-1) rows. Since the previous pixel data is subtracted, as mentioned above, 〓 _i,j =〓 _i-1,j +T _i,j −S _in,j −d _in,j-(o-1) , one pixel Cumulative sum data of separated small areas〓
_{i and j} are sequentially obtained, stored in the cumulative sum register 17, and output.

As described above, according to the present device, along with pixel data inputted in time series through two-dimensional scanning, cumulative sum data of a small area consisting of (m×n) pixels determined by the data input pixel position is calculated. They can be found sequentially. Moreover, the arithmetic processing can be performed at high speed in real time. Therefore, it is possible to set each small area by shifting one pixel over the entire area of the image 1 to be processed, and to accurately obtain information in that small area. Therefore, there is no possibility of obtaining erroneous inspection results due to non-uniform distribution of inspection objects, which has been a problem in the past, and there is no problem such as the need to take measures to set small areas in order to prevent such errors. Furthermore, the continuous cumulative sum processing (m x n), which conventionally requires an enormous amount of calculation processing (M x N x m x n) times to inspect the entire image area, has been realized in real time using a high-speed calculation method. possible. Furthermore, as described above, the hardware configuration is simple by only performing delay processing for (n-1) lines and m pixels, and its practical advantages are enormous. Further, as described above, since the size of the small area can be set arbitrarily, it is highly versatile in processing images as processing targets, and enables flexible image processing. Furthermore, when processing a grayscale image,
It is possible to calculate the local density sum, and thereby dynamic binarization processing of so-called uneven images can be performed.

Note that the present invention is not limited to the above embodiments. For example, the number n of constituent lines of the shift register 12 may be determined according to specifications. In addition, RAM is used instead of a shift register, and this
Similar processing may be performed by controlling access to RAM. Furthermore, by performing the addition and cumulative sum processing simultaneously using a plurality of arithmetic circuits provided in parallel, it is also possible to perform image processing on various small areas of different m and n in parallel. In summary, the present invention can be implemented with various modifications without departing from the gist thereof.

[Brief explanation of the drawing]

Figures 1 and 2 a and b are diagrams showing the relationship between images and small areas to explain problems in image processing, Figure 3 is a diagram showing the processing concept of the present invention, and Figure 4
The figure is a schematic configuration diagram of an apparatus according to an embodiment of the present invention. 11...Adder, 12...First shift register, 13...Subtractor, 14...Second shift register, 15...Third shift register, 16...
Adder, 17... Cumulative sum register, 18, 19...
...Subtractor.

Claims (1)

[Claims] Time-series input pixel data obtained by two-dimensionally scanning an image consisting of 1 (M×N) pixels (M, N: arbitrary integers) is divided into {M×(n-1)} stages. (n≦N: integer) first storage means that delays and this {M×(n
-1)} second storage means for further delaying the input pixel data delayed by m stages (m≦M: integer); and third storage means for delaying the given addition pixel data by M stages; The input pixel data is added to this added pixel data delayed by M stages, and the input pixel data delayed by {M×(n-1)} stages by the first storage means is subtracted to generate new added pixel data. the first to generate and provide to the third storage means
a calculation means, a fourth storage means for temporarily storing the given cumulative sum data, and an addition that is delayed by M stages by the third storage means to the cumulative sum data temporarily stored in the fourth storage means. Addition data is obtained by adding pixel data and the input pixel data, and from this addition data, m-stage delayed addition pixel data that is the m-th stage tap output of the third storage means and the second storage means are obtained. and a second calculation means that subtracts the input pixel data delayed by m stages respectively to generate new cumulative sum data and provide it to the fourth storage means,
N) An image processing device characterized by obtaining characteristic information of a small area made up of (m×n) pixels in an image made up of pixels. 2. The image processing apparatus according to claim 1, wherein each of the first to fourth storage means is constituted by a shift register driven to transfer data in synchronization with a clock of time-series input pixel data. . 3 The first and second calculation means commonly obtain addition data of the addition pixel data delayed by M stages by the third storage means and the input pixel data, and perform predetermined calculation processing using each of the addition data. An image processing apparatus according to claim 1, wherein the image processing apparatus executes the following.