JPH05346890A - Data invalidation control system - Google Patents

Abstract

PURPOSE:To obtain a microprocessor whose reliability and availability are high by constituting it so that even when a parity error is detected in an invalidated address, a processing is continued without suspending an instruction processing and an interruption processing which are being executed at present, and also, a coincidence property of data of a cache memory and data of a main storage device can be secured. CONSTITUTION:In the case a parity error is detected in an invalidated address, a reference to a continued cache memory 22 is inhibited temporarily, and all entries of the cache memory 22 are invalidated forcibly, by which an instruction processing and an interruption processing which are being executed at present are continued, and also, a coincidence property of data of the cache memory 22 and data of a main storage device 24 is secured.

Description

Detailed Description of the Invention

[0001]

BACKGROUND OF THE INVENTION 1. Field of the Invention The present invention relates to guaranteeing consistency between data in a cache memory and data in a main memory in a computer system having a microprocessor having a buffer memory (hereinafter referred to as cache memory) and a main memory. The present invention relates to a data invalidation control method for invalidating the data in the cache memory for.

[0002]

2. Description of the Related Art A cache memory internally holds data in the main storage device in units of an area of the main storage device evenly divided into a certain size (this is called a block). Address in memory and address in main memory (called main memory address)
It also holds information for associating with each other (this is called associative storage address information or tag information). At the same time, the block (called a cache entry) corresponding to the address in the cache memory holds the state information (also called a valid bit) indicating that the block correctly matches the data in the main memory and is valid. In this method of associating blocks in the main memory device with blocks in the cache memory, or in the associative method, the method of associating the main memory address with a specific cache entry on a one-to-one basis is called a direct map associative memory method, and N caches A method of associating with an entry is called an N-way set associative associative memory method. For the access to the main memory that is issued in response to the execution of an instruction, the tag information in the cache memory determines whether the block containing the data corresponding to the main memory address exists in the cache memory. If it matches and is a valid cache entry, it is determined that the block exists. This is called a cache hit, and if the above block does not exist, it is called a cache miss. Further, a method of constantly changing the data in the main storage device regardless of a cache hit or a cache miss in the operation of changing the data in the main storage device, which is issued along with the execution of an instruction, is called the main memory update control by the store-through method. If there is a cache hit at this time, it is general to update the block in the cache memory at the same time. According to this method, it is guaranteed that the block data in the cache memory and the corresponding block data in the main memory always match. Has been done.

If another processor or device updates the data in the main storage device, the matching cannot be guaranteed, and a function for invalidating the block in the cache memory is needed. This cache invalidation processing is an invalidation address that specifies a block corresponding to the main memory address to be changed, and an invalidation request that invalidates any valid cache entry corresponding to that address. When an invalidation request signal and an invalidation address cause an internal cache hit in the cache entry by the invalidation request signal and invalidation address, the cache memory sets block data in the cache memory and main memory by invalidating the valid bit. This is a process that guarantees the consistency of block data in the device. Further, in order to improve the reliability of the invalidation address, a parity bit which is a redundant bit is simultaneously added to the invalidation address.

FIG. 2 is a block diagram showing the configuration of a computer system used in a conventional example and an embodiment described later. In FIG. 2, reference numeral 24 is a main storage device that stores data necessary for data processing, and 21 is a part of the main storage device 24 that stores some data in the main storage device 24 in order to speed up data processing. It is a microprocessor provided with a cache memory 22 for performing data update control and an invalidation unit 23 for performing the cache invalidation processing.

FIG. 3 is a block diagram showing the configuration of a conventional data invalidation control system in a microprocessor having a built-in cache memory for controlling the update of data in the main memory by the store-through system. In FIG. 3, 1
Is a tag memory that holds the associative memory address of the built-in cache memory, and 2 is a comparator that compares the associative address information read from the tag memory 1 with the input address and outputs a hit signal if they match. 3 is a status memory that holds the valid / invalid state of the corresponding cache entry as associative storage state information of the built-in cache memory. 4 is the invalidation address and the parity bit as input and performs a parity check and outputs a parity laye signal when an error is detected. Parity checkers 5 and 5 indicate control circuits for invalidating the corresponding entry in the status memory 3 when the hit signal output from the comparator 2 is detected when the invalidation request signal is input. The invalidation of the entry in the status memory 3 will be described below as being equivalent to the invalidation of the entry in the cache memory.

The operation of the cache invalidation function of the conventional microprocessor will be described with reference to FIG. The input invalidation address refers to the tag memory 1 to read the associative address information from the tag memory 1, and the read associative address information and the input invalidation address are compared by the comparator 2
When the two are compared with each other and the two match, the comparator 2 outputs a hit signal. At this time, the control circuit 5 that receives the invalidation request signal input and the hit signal performs control such that the associative memory state information stored in the cache entry corresponding to the corresponding address in the status memory 3 is invalidated. .. At the same time, the parity checker 4 performs a parity check on the input invalidation address, and if a parity error is detected, the cache entry invalidated by the control circuit 5 is an incorrect entry and the invalidation address itself has a parity error. Since there is a problem that the correct address is not guaranteed, the cache entry that should be invalidated is not invalidated and remains valid, so that normal instruction execution and interrupt processing should be performed. However, the parity error signal is output and the interruption of the processing currently being executed is requested.

[0007]

As described above, the data invalidation control system in the conventional microprocessor is as follows.
When a parity error is detected in the invalidation address, the cache entry that should be invalidated is not invalidated but remains valid. Therefore, normal instruction execution and interrupt processing are performed. However, there is a problem that the reliability and availability of the microprocessor deteriorates remarkably because the processing currently being executed cannot be performed and must be interrupted.

The present invention has been made in order to solve the above problems, and even if a parity error is detected in an invalidation address, the processing is continued without interrupting the currently executed instruction processing or interrupt processing. It is also an object of the present invention to provide a data invalidation control method capable of realizing a microprocessor capable of guaranteeing the consistency between the data in the cache memory and the data in the main memory.

[0009]

According to the data invalidation control method of the present invention, when a parity error is detected in an invalidation address, the continuous reference to the cache memory 22 is temporarily suppressed, and the cache memory 22 is prevented. By forcibly invalidating all entries of the cache memory, instruction processing and interrupt processing currently being executed are continued, and the cache memory 2
The consistency between the data of No. 2 and the data of the main memory 24 is guaranteed.

[0010]

When a parity error is detected in the invalidation address, the parity error signal forcibly invalidates all the associative memory information of all entries in the cache memory 22.

[0011]

【Example】

Example 1. (Corresponding to Claim 1) FIG. 1 is a block diagram showing a configuration of an invalidation unit (see FIG. 2) of a microprocessor according to a data invalidation control system according to an embodiment of the present invention. In FIG. 1, 1 is a tag memory that holds the associative memory address of the internal cache memory, and 2 is a hit signal when the associative address information read from the tag memory 1 and the input address are compared and both match. It is a comparator that outputs 2a. 3 is a status memory that holds the valid / invalid state of the corresponding cache entry as associative memory state information of the built-in cache memory. Each associative memory information can be validated / invalidated in 1-bit units corresponding to a specified address. At the same time, all entries can be made invalid.
Reference numeral 4 is a parity checker that inputs a nullification address and a parity bit, performs a parity check, and outputs a parity error signal 4a when an error is detected. 6 indicates that when the hit signal output from the comparator 2 is detected when the invalidation request signal is input and no parity error is detected in the invalidation address, the corresponding entry in the status memory 3 is invalidated, and the input invalidation address is input. This is a control circuit for invalidating all the entries in the status memory 3 when a parity error is detected.

Next, the operation of this embodiment will be described with reference to FIG. The data in the cache memory that exists inside the microprocessor and controls update of the data in the main memory by the store-through method is different from the data in the main memory outside the microprocessor or the microprocessor. Input the invalidation request signal, invalidation address, and parity bit of the invalidation request signal to guarantee the consistency with the data in the cache memory inside the microprocessor (cache coherency), and invalidate the corresponding entry in the internal cache memory. When a parity error is detected in the input invalidation address in the microprocessor having the function of converting, all the entries in the cache memory inside the microprocessor are invalidated. This operation will be described in detail below.

The input invalidation address is the tag memory 1
, The associative address information is read from the tag memory 1, the read associative address information and the input invalidation address are compared by the comparator 2, and a hit signal 2a is output when the two match. At the same time, the parity checker 4 performs a parity check on the input invalidation address and outputs a parity error signal 4a when an error is detected. At this time, the control circuit 6 which receives the invalidation request signal, the hit signal 2a, and the parity error signal 4a performs the following control according to the state of each signal. That is, the control circuit 6
Indicates that the invalidation request signal is output, and the hit signal 4a
Is output and the parity error signal 4a is not output, the entry invalidation request signal 6a is output to the status memory 3, and the associative memory stored in the entry corresponding to the corresponding address of the status memory 3 is output. Control is performed so that the state information is invalid. Further, the control circuit 6 outputs the invalidation request signal and the hit signal 2a.
Irrespective of the above, when the parity error signal 4a is being output, the all-entry invalidation request signal 6 is sent to the status memory 3.
b is output and the associative memory state information stored in all entries corresponding to all addresses in the status memory 3 is controlled to be invalid at the same time. In other cases, the associative memory state information is stored in the status memory 3. Do not change the memory status information.

When the invalidation request signal input is accepted, the control circuit 6 is controlled and operated so as not to accept subsequent reference to the cache memory until the control is completed. Further, the output of the parity error signal of the invalidation address is configured not to request the interruption of the process currently being executed.

Example 2. In the above description, the status memory 3 is an example in which all the entries are invalidated at the same time. However, a counter for counting the addresses of the status memory 3 is provided, and all the addresses of the status memory 3 are provided. It is needless to say that the same effect can be obtained even if the control circuit is configured to repeat the operation of invalidating the control circuit.

Embodiment 3. Further, in the above description, the tag memory 1, the comparator 2, and the status memory 3 are each an example of the direct map associative storage system.
It goes without saying that the same effect can be obtained even with a set associative associative memory system in which a plurality of sets are provided.

[0017]

As described above, according to the present invention, when a parity error is detected in the input invalidation address, all the entries in the buffer memory device in the microprocessor are invalidated. Therefore, there is an effect that the processing can be continued without interrupting the instruction processing and the interrupt processing which are currently being executed while guaranteeing the consistency of data, and thus a microprocessor having high reliability and availability can be obtained.

[Brief description of drawings]

FIG. 1 is a block diagram showing the configuration of a data invalidation control method according to an embodiment of the present invention.

FIG. 2 is a block diagram showing a configuration of a computer system according to a conventional example and an example.

FIG. 3 is a block diagram showing a configuration of a conventional data invalidation control method.

[Explanation of symbols]

 1 Tag Memory 2 Comparator 3 Status Memory 4 Parity Checker 6 Control Circuit 21 Microprocessor 22 Cache Memory 23 Invalidation Section 24 Main Storage Device

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[Procedure amendment]

[Submission date] October 7, 1992

[Procedure Amendment 1]

[Document name to be amended] Statement

[Name of item to be amended] Claims

[Correction method] Change

[Correction content]

[Claims]

Claims (1)

[Claims] 1. A microprocessor provided with a buffer memory device for storing a part of data in a main memory device for speeding up data processing and controlling update of the data in the main memory device. Therefore, the consistency between the data in the buffer storage device of the microprocessor and the data in the main storage device outside the microprocessor, or the data in the buffer storage device inside the microprocessor different from the microprocessor. For the purpose of guarantee, when the data in the main memory is updated, the invalidation address that specifies the address of the main memory in which the updated data is stored and the valid address corresponding to this invalidation address. If there is an entry in the buffer storage device, an invalidation request signal requesting that the entry be invalidated, and the invalidation address In the microprocessor having the function of invalidating the corresponding entry in the buffer memory device by inputting the parity bit, the buffer memory device that continues when a parity error is detected in the invalidation address input to the microprocessor. By temporarily suppressing the reference to and forcibly invalidating all the entries in the buffer storage device, the instruction processing and the interrupt processing currently being executed are continued, and the above-mentioned consistency is guaranteed. Data invalidation control method.