JPH05346887A - Peripheral lsi of microcomputer - Google Patents

Abstract

PURPOSE:To decrease the number of parts of an applied circuit constituted of the microcomputer and the peripheral LSI, and also, to realize the address arrangement desired by a user without changing the applied circuit. CONSTITUTION:The peripheral LSI is provided with a rewritable PROM 120, a ROM 130 for storing an instruction code and data of a microcomputer 100, an output AR bus 123 of device selecting information stored in advance in the PROM 120 and an internal address IAD bus 121, and a coincidence detecting circuit 122 for comparing the IAD bus 121 and the AR bus 123, and outputting a selecting signal 125 of the ROM 130, in the case they coincide with each other.

Description

Detailed Description of the Invention

[0001]

BACKGROUND OF THE INVENTION 1. Field of the Invention The present invention relates to a peripheral LSI of a microcomputer.

[0002]

2. Description of the Related Art Generally, a peripheral L of a microcomputer
The SI ROM or RAM device has no built-in means for recognizing that it is in the selected state. Therefore, it has a selection terminal for recognizing that it is in a selected state by a signal input from the outside.

An example of forming an application circuit using a ROM device as a peripheral LSI of a conventional microcomputer will be described with reference to FIGS. 3 and 4.

The circuit of FIG. 3 has a microcomputer 300 which does not include a program memory having an address space of 64 Kbytes, and a peripheral L for storing an instruction code or data processed by the microcomputer 300.
16K byte ROM 301, 302, 303 which is SI
And 304, an address bus (hereinafter referred to as "A bus") 309 having a 16-bit bus width for outputting an address from the microcomputer 300 to peripheral circuits, and A.
The ROM 3 of the peripheral LSI is decoded by decoding the states of bit 14 and bit 15 of the address information output from the bus 309.
A selection circuit 305 that outputs selection signals 326, 327, 328, and 329 to 01, 302, 303, and 304, and an 8-bit wide data bus (hereinafter referred to as “D bus”) that inputs and outputs data to and from the microcomputer 300. 311 and ROMs 301, 302, 303, 304
ROM timing for reading data stored in
Signals output from the microcomputer 300 (hereinafter referred to as "RD") to be given to the 301, 302, 303, 304.
Signal 310).

Next, the details of the selection circuit 305 will be described with reference to FIG. Selection circuit (decoder) 305 of FIG.
Are disk read element AND circuits 321, 322, 3
23 and 324, each of which is fixedly wired on the substrate by a metal wire.

Next, the circuit operation will be described.

During the operation of the microcomputer 300, address information to be accessed is output to the ROMs 301, 302, 303, 304 and the selection circuit 305 via the A bus 309. The selection circuit 305 is A
ROM selection signals 326, 327, 328, 3 depending on the states of bit A15 and bit A14 of the address of bus 309.
29 is output.

When the bit A15 of the A bus 309 is "0" and the bit A14 is "0", the output of the AND circuit 321 is "1". The selection circuit 305 has a selection signal 326 ″.
1 "is output to the ROM 301. At this time, RO
When M301 is in the selected state and the RD signal 310 is active, the data stored in the ROM301 is the D bus 31.
Is read out to the microcomputer 300 via 1.
The microcomputer 300 performs a predetermined operation according to the read data.

Similarly, the bit A15 of the A bus 309 is "
If 0 ”and the bit A14 are“ 1 ”, the AND circuit 32
The ROM selection signal 327 which is the output of 2 becomes "1" and R
The data of the OM 302 is read by the microcomputer 300.

When the bit A15 of the A bus 309 is "1" and the bit A14 is "0", the ROM selection signal 328 output from the AND circuit 323 is "1".
The data No. 3 is read out to the microcomputer 300.

When the bit A15 of the A bus 309 is "1" and the bit A14 is "1", the ROM selection signal 329 output from the AND circuit 324 becomes "1".
The data of No. 4 is read out to the microcomputer 300.

[0012]

The conventional peripheral LSI described above has the following problems.

Conventional peripheral LSIs 301, 302, 30
No. 3,304 has no built-in means for recognizing that it is in the selected state. Therefore, it is necessary to have a selection terminal without fail and to recognize selection / non-selection according to the state of the selection terminal.

Therefore, when forming the application circuit, the decoder circuit is added by using the discrete element. However, if the number of peripheral LSIs increases, the area occupied by the decoder circuit on the application circuit increases.

Further, since the application circuit is usually constructed by fixing the microcomputer, the peripheral LSI and the discrete element on the glass epoxy resin substrate with metal wiring,
It is difficult to change the decoder once formed.

[0016]

A feature of the present invention is that a ROM
Alternatively, a RAM and a rewritable non-volatile memory that stores device selection information in advance (hereinafter referred to as PROM)
And a coincidence detection circuit that compares the device selection information stored in the PROM with the address information input from the outside and outputs the device selection information.

[0017]

DETAILED DESCRIPTION OF THE PREFERRED EMBODIMENTS A first embodiment of a peripheral LSI according to the present invention will be described with reference to FIG.

The circuit shown in FIG. 1 is a microcomputer 10 which does not include a ROM having an address space of 64 Kbytes.
0, and an 8-bit bus width D bus 106 for inputting / outputting data between the microcomputer 100 and peripheral devices.
A 16-bit bus width A bus 105 output from the microcomputer 100, and a peripheral LSI according to the present invention.
, 101, 102, 103, 104. Further, the microcomputer 100 sends an RD signal 107 for giving a read timing to the peripheral LSIs 101, 102, 103, 104.

Peripheral LSIs 101 and 10 according to the present invention
Each of 2, 103, and 104 is a PROM 120 in which device selection information is stored in advance, and 16K in which an instruction code and data of the microcomputer 300 are stored.
Byte ROM 130 and internal address bus (hereinafter referred to as "IA bus") 121 directly connected to A bus 105
And the output of PROM 120 (hereinafter referred to as "AR bus")
123, the AR bus 123 and the IA bus 121 are compared, and if they match, the selection signal 12 is sent to the ROM 130.
5 is set to "1" and the selection signal 125 is set to "1" when they do not match.
The coincidence detection circuit 122 for setting to 0 ", and the internal data bus for outputting the read data of the ROM to the external bus (hereinafter referred to as" ID
Bus 124).

Next, the circuit operation will be described. First,
The case of the peripheral LSI 101 will be described.

During operation of the microcomputer 100,
The address information to be accessed is output to the IA bus 121 via the A bus 105, and the address information is input to the match detection circuit 122 and the ROM 130.

At this time, the PROM 13 of the device 101
The device selection information stored in 0 is output to the AR bus 123, and the AR bus 123 and the IA bus 121 are input to the coincidence detection circuit 122 for comparison.

When they match, the selection signal 125 becomes "1", and the ROM 130 enters the selected state. ROM130 is
While the RD signal 107 is active, data is output to the D bus 106 via the ID bus 124, and the microcomputer 100 reads the data on the D bus 106 and performs a predetermined operation.

The AR bus 123 and the IA bus 121 are compared, and if they do not match, the selection signal 125 becomes "0",
The ROM 130 is in a non-selected state, and no data is output even if the RD (read) signal 107 becomes active.

This operation is performed by the peripheral LSIs 102, 10
The same applies to 3,104.

Next, a second embodiment of the peripheral LSI according to the present invention will be described with reference to FIG.

In the second embodiment, the peripheral LSI
201, 202, 203 and 204 of the ROM 130
Instead of this, a RAM 230 capable of writing / reading is built in, and from the microcomputer 200, an RD signal 207 for giving a data reading timing and a signal for giving a data writing timing (hereinafter referred to as "
208 is a microcomputer 30.
Since the only difference is that it is output from 0, the description of the configuration of the other parts is the same as that of the first embodiment shown in FIG.

Next, the circuit operation will be described. First,
A case of writing data to the peripheral LSI 201 will be described.

During operation of the microcomputer 100,
The address information to be accessed is output to the IA bus 221 via the A bus 205, and the address information is input to the match detection circuit 222 and the RAM 230.

At this time, the PROM of the peripheral LSI 201
The device selection information stored in 230 is output to the AR bus 223, and the AR bus 223 and the IA bus 221 are input to the match detection circuit 222 for comparison.

When they match, the selection signal 225 becomes "1", and the RAM 230 enters the selected state.

At this time, the write data is output from the microcomputer 300 to the D bus 206 and the ID
The data is input to the RAM 230 via the bus 224, and data is written to a predetermined address of the RAM 230 while the WR signal 208 is active.

The data read operation is the same as that of the first embodiment shown in FIG. 1 and will not be repeated here.

The above operation is performed by the peripheral LSIs 202 and 20.
The same applies to 3,204.

[0035]

As described above, in the peripheral LSI according to the present invention, the device selection information is written in advance.
Selection / non-selection can be discriminated by comparing the ROM and the input address information and performing coincidence detection.

Therefore, when the application circuit is formed, there is an effect that the application circuit can be configured with a compact structure without adding a special decoder circuit.

Further, since the PROM is used with the selection information written therein, the address mapping desired by the user can be easily realized by rewriting the information of the PROM even after the circuit is formed on the substrate.

[Brief description of drawings]

FIG. 1 is a diagram showing a first embodiment of the present invention.

FIG. 2 is a diagram showing a second embodiment of the present invention.

FIG. 3 is a diagram showing a conventional technique.

FIG. 4 is a diagram showing a conventional selection circuit.

[Explanation of symbols]

100 Microcomputer 101, 102, 103, 104 Peripheral LSI 105 A bus 106 D bus 107 RD signal 120 PROM 121 IA bus 122 Match detection circuit 123 AR bus 124 ID bus 125 Selection signal 130 ROM 200 Microcomputer 201, 202, 203, 204 Peripheral LSI 205 A bus 206 D bus 207 RD signal 208 WR signal 220 PROM 221 IA bus 222 Match detection circuit 223 AR bus 224 ID bus 225 selection signal 300 Microcomputer 301, 302, 303, 304 ROM (peripheral LS
I) 305 selection circuit 309 A bus 310 RD signal 311 D bus 321,322,323,324 AND circuit 326,327,328,329 selection signal

Claims (1)

[Claims] 1. A ROM or RAM, and a rewritable non-volatile memory that stores device selection information in advance.
A peripheral LSI for a microcomputer, comprising: a coincidence detection circuit that compares the device selection information stored in the non-volatile memory with address information input from the outside and outputs device selection information.