JPH05344178A - Electric circuit - Google Patents

Abstract

PURPOSE:To specify the device of a low level output source in the electric circuit used by AND tie connecting open collector bidirectional signals. CONSTITUTION:An output source detection circuit 10 composed of a smoothing circuit, which is composed of inverter circuits 4a, 4b, 4c, 4d and 4e of active pull-up outputs, inverter circuits 5a and 5b of open collector outputs, pull-up resistor 7 and capacitor 8, and a flip-flop 9 for detecting which device is the low level output source is provided between the AND tie connection of open collector bidirectional signals at devices 2a and 2b. When the output of the device 2b is at a low level, a signal at the low level is outputted from the bar Q terminal of the flip-flop 9 and when the output of the device 2a is at the low level, this low level signal is not outputted.

Description

Detailed Description of the Invention

[0001]

BACKGROUND OF THE INVENTION 1. Field of the Invention The present invention relates to an electric circuit in which two devices are connected in an open-collector or open-drain bidirectional signal and tie connection, and more particularly to a low level output source of the open-collector or open-drain bidirectional signal. The present invention relates to an electric circuit for detecting.

[0002]

2. Description of the Related Art FIG. 1 is a diagram showing an example of an AND-tie connection of open collector bidirectional signals in an electric circuit, in which 2a and 2b are devices having open collector bidirectional signal pins 1a and 1b, respectively. .. The open collector bidirectional signal pins 1a and 1b are connected to each other by a signal line 3 of AND-tie connection.

Next, the operation will be described. Device 2a
Outputs a low level to the pin 1a, the low level is transmitted through the signal line 3 and input to the pin 1b of the device 2b. On the other hand, similarly, when the device 2b outputs a low level to the pin 1b, the low level is transmitted through the signal line 3 and input to the pin 1a of the device 2a. In this way, when either one of the devices 2a and 2b outputs a low level, the signal line 3 becomes a low level.

[0004]

As described above, in the electric circuit in which the open collector bidirectional signal is used in an AND-tie connection, in the conventional example, when the signal line 3 becomes low level, the signal line 3 But low level is device 2
There is a problem that it is not possible to determine which device, a or device 2b, is caused by the low level output, that is, which device is the low level output source.

The present invention has been made in view of such circumstances, and is an electric circuit that uses an open-collector or open-drain bidirectional signal in an AND-tie connection, and an electric circuit that can specify the device of the low level output source. The purpose is to provide a circuit.

[0006]

SUMMARY OF THE INVENTION An electric circuit according to the present invention is a signal circuit for detecting which device is a low level output source during an AND tie connection of an open collector or open drain bidirectional signal. It is characterized by having.

[0007]

In the signal circuit for detecting the low level output source in the electric circuit of the present invention, the low level detection signal is output only when one of the two specific devices becomes the low level, and the other one. This detection signal does not become low level when the device of becomes low level. Therefore,
This detection signal identifies the device of the low level output source.

[0008]

DESCRIPTION OF THE PREFERRED EMBODIMENTS The present invention will be described in detail below with reference to the drawings showing the embodiments thereof.

Embodiment 1. FIG. 2 is a circuit diagram showing the configuration of the electric circuit of the first embodiment according to the present invention. In the figure, 2a and 2b are devices having open collector bidirectional signal pins 1a and 1b, respectively. An open-collector bidirectional signal output source detection circuit 10 composed of an inverter circuit, an AND circuit, a smoothing circuit, and a flip-flop circuit is provided between the open-collector bidirectional signal pins (hereinafter simply referred to as pins) 1a and 1b. Is provided.

An inverter circuit 4a having an active pull-up output and an inverter circuit 5a having an open collector output are connected in series between the pins 1a and 1b. Inverter circuit
The output terminal of 4a is connected to one input terminal of the AND circuit 6 through the inverter circuit 4b of active pull-up output,
The output end of the inverter circuit 5a is connected to the other input end of the AND circuit 6 via the active pull-up output inverter circuit 4c. The output terminal of the AND circuit 6 is connected to a smoothing circuit composed of a pull-up resistor 7 and a capacitor 8 and also an input terminal of a positive edge trigger flip-flop 9 via inverter circuits 4d and 4e of active pull-up output. Connected to T. An open collector output inverter circuit 5b is provided between the output terminal Q of the flip-flop 9 and the pin 1a of the device 2a. The output terminal bar Q and the D terminal of the flip-flop 9 are connected.

Next, the operation will be described. FIG. 3 is a timing chart of signals when the output of the device 2b is low level in the circuit having the above-described configuration, and FIG. 4 is a timing chart of signals when the output of the device 2a is low level. 3 and 4, (a) is the output a of the pin 1b of the device 2b, (b) is the input of the AND circuit 6 (output of the inverter circuit 4c), and (c) is the input of the AND circuit 6. (Output of inverter circuit 4b) c, (d)
Is the output d of the AND circuit 6, (e) is the input e of the flip-flop 9, (f) is the output (output for source detection) f of the output terminal bar Q of the flip-flop 9, and (g) is the output of the flip-flop 9. The outputs g and (h) of the output terminal Q represent the waveforms of the output h of the pin 1a of the device 2a, respectively.

First, as an initial state, the flip-flop 9
The output i for the output source detection (the output of the output terminal bar Q) is cleared by the input i to the reset terminal R of. When the output of the device 2b becomes low level, the low level signal is inverted by the inverter circuit 4c, the input b of the AND circuit 6 becomes high level, and the output d of the AND circuit 6 becomes high level. Further, the high level signal is transmitted through the inverter circuits 4d and 4e, the rising edge is trigger-input to the input e of the flip-flop 9, and the output source detection output f becomes the low level. At the same time, the output g of the output terminal Q becomes high level, and this high level signal is inverted by the inverter circuit 5b and transmitted to the device 2a as a low level input.

On the other hand, when the output of the device 2a becomes low level, the low level signal is transmitted through the inverter circuits 4a and 5a and input to the device 2b. The inputs b and c of the AND circuit 6 at this time are the inverter circuits 5a,
When the total of the propagation delays of 4c is larger than the propagation delay of the inverter circuit 4b, neither of them becomes high level, and the output d of the AND circuit 6 remains low level. Therefore, the output source detection output f of the flip-flop 9 does not go low. Then when the output of device 2a is disabled,
The inputs b and c of the AND circuit 6 are both at the high level and the output d of the AND circuit 6 is at the high level only for the period of the difference between the total of the propagation delays of the inverter circuits 5a and 4c and the propagation delay of the inverter circuit 4b. .. However, if the constants of the pull-up resistor 7 and the capacitor 8 for smoothing are set so that the voltage of this high-level signal becomes lower than the input threshold voltage of the next-stage inverter circuit 4d, The level signal is not transmitted to the inverter circuit 4d and thereafter, and the output f for detecting the output source of the flip-flop 9 does not become low level even during this period.

As described above, the output source detection output f becomes low level only when the output of the device 2b becomes low level, and does not become low level when the output of the device 2a becomes low level. Therefore, when the open collector bidirectional signal becomes low level, by checking whether or not the output source detection output f is low level, the device of the low level output source can be easily specified.

Example 2. Although the above-described first embodiment has described the case where the low level output source is specified in the open collector bidirectional signal, the low level output source can be specified in the same manner for the open drain bidirectional signal. An example of this case will be described below as a second embodiment.

FIG. 5 is a circuit diagram showing the configuration of the electric circuit of the second embodiment according to the present invention. In the figure, 22a and 22b are devices having open drain bidirectional signal pins 21a and 21b, respectively. An open drain bidirectional signal output source detection circuit 30 including an inverter circuit, an AND circuit, a smoothing circuit, and a flip-flop circuit is provided between the open drain bidirectional signal pins (hereinafter simply referred to as pins) 1a and 1b. Is provided.

An inverter circuit 4a having an active pull-up output and an inverter circuit 25a having an open drain output are connected in series between the pins 21a and 21b. The output terminal of the inverter circuit 4a is connected to one input terminal of the AND circuit 6 via the active pull-up output inverter circuit 4b, and the output terminal of the inverter circuit 25a is connected to the AND circuit via the active pull-up output inverter circuit 4c. 6 is connected to the other input terminal. The output terminal of the AND circuit 6 is
It is connected to a smoothing circuit composed of a pull-up resistor 7 and a capacitor 8, and is also connected to an input terminal T of a positive edge trigger flip-flop 9 via active pull-up output inverter circuits 4d and 4e.
Output terminal Q of flip-flop 9 and pin of device 22a
An open drain output inverter circuit 25b is provided between the inverter 21a and 21a. The output terminal bar Q and the D terminal of the flip-flop 9 are connected.

Next, the operation will be described. FIG. 6 is a timing chart of signals when the output of the device 22b is low level in the circuit having the above-described configuration, and FIG. 7 is a timing chart of signals when the output of the device 22a is low level. 6 and 7,
In either case, (a) is the output a of pin 21b of device 22b, (b)
Is an input of the AND circuit 6 (output of the inverter circuit 4c) b,
(c) is the input of the AND circuit 6 (output of the inverter circuit 4b)
c, (d) is the output d of the AND circuit 6, (e) is the input e of the flip-flop 9, (f) is the output (output source detection output) f, (g) of the output terminal bar Q of the flip-flop 9. Is the output g of the output terminal Q of the flip-flop 9, and (h) is the device 22a.
The waveform of the output h of the pin 21a of FIG.

First, as an initial state, the flip-flop 9
The output i for the output source detection (the output of the output terminal bar Q) is cleared by the input i to the reset terminal R of. When the output of the device 22b becomes low level, the low level signal is inverted by the inverter circuit 4c, the input b of the AND circuit 6 becomes high level, and the output d of the AND circuit 6 becomes high level. Further, the high level signal is transmitted through the inverter circuits 4d and 4e, and the flip-flop 9
The rising edge is input as a trigger to the input e, and the output source detection output f becomes low level. At the same time, output terminal Q
Output g becomes high level, and this high level signal is inverted by the inverter circuit 25b and transmitted to the device 22a as a low level input.

On the other hand, when the output of the device 22a becomes low level, the low level signal is output to the inverter circuits 4a and 25a.
And is input to the device 22b. Also,
At this time, the inputs b and c of the AND circuit 6 do not both become high level when the total propagation delay of the inverter circuits 25a and 4c is larger than the propagation delay of the inverter circuit 4b, and the output d of the AND circuit 6 becomes It remains low level.
Therefore, the output source detection output f of the flip-flop 9 does not go low. Next, when the output of the device 22a is invalidated, the inputs b and c of the AND circuit 6 are both set to the high level for the period of the difference between the total propagation delay of the inverter circuits 25a and 4c and the propagation delay of the inverter circuit 4b. Then, the output d of the AND circuit 6 becomes high level. However, if the constants of the pull-up resistor 7 and the capacitor 8 for smoothing are set so that the voltage of this high-level signal becomes lower than the input threshold voltage of the inverter circuit 4d at the next stage,
This high level signal is not transmitted to the inverter circuit 4d and thereafter, and the output f for detecting the output source of the flip-flop 9 does not become low level even during this period.

As described above, the output f for detecting the output source becomes low level only when the output of the device 22b becomes low level, and does not become low level when the output of the device 22a becomes low level. Therefore, when the open drain bidirectional signal becomes low level, it is possible to easily identify the device of the low level output source by checking whether the output f for output source detection is low level.

[0022]

As described above, in the electric circuit of the present invention,
Since the signal circuit that detects the low level output source is configured between the AND tie connection of the open collector bidirectional signal or open drain bidirectional signal, when the open collector bidirectional signal or open drain bidirectional signal becomes low level, It becomes possible to specify the device of the low level output source.

[Brief description of drawings]

FIG. 1 is a schematic diagram showing an example of an AND-tie connection of an open collector bidirectional signal in an electric circuit.

FIG. 2 is a circuit diagram showing a configuration of a first embodiment of an electric circuit according to the present invention.

FIG. 3 is a timing chart of signals at various points in the circuit shown in FIG.

4 is a timing chart of signals at respective points of the circuit in FIG.

FIG. 5 is a circuit diagram showing a configuration of a second embodiment of the electric circuit according to the present invention.

FIG. 6 is a timing chart of signals at various points in the circuit shown in FIG.

FIG. 7 is a timing chart of signals at various points in the circuit shown in FIG.

[Explanation of symbols]

 1a, 1b Open collector bidirectional signal pin 2a, 2b Device 10 Output source detection circuit 21a, 21b Open drain bidirectional signal pin 22a, 22b Device 30 Output source detection circuit

Claims (2)

[Claims] 1. An electrical circuit in which two devices are connected in an open-collector bidirectional signal and tie,
An electric circuit, characterized in that means for detecting which device is a low level output source when the open collector bidirectional signal becomes low level is provided between the AND-tie connections. 2. An electric circuit in which two devices are connected in an open-drain bidirectional signal by AND-tie,
An electric circuit comprising means for detecting which device is a low level output source when the open drain bidirectional signal becomes low level, between the and-tie connections.