JPS61150413A - Input circuit for detecting high impedance state - Google Patents

Abstract

PURPOSE:To detect early the problems in the development and evaluation modes of a system using a microcomputer by producing a detection signal in case no normal input signal is applied to an input terminal and this terminal is kept under a high impedance state. CONSTITUTION:A p channel transistor TR21 serving as the 1st control means is provided together with an n channel TR18 serving as the 2nd control means, an initial input signal holding means 14 serving as the 1st input signal holding means, a final input signal holding means serving as the 2nd input signal holding means, and an exclusive OR circuit 24 serving as a deciding means which compares the contents of the means 14 and those held by the final input signal holding means and delivers the result of this comparison. An H level, i.e., the output of the circuit 24 obtained at a timing point t4 is kept at and after the point t4 when a control signal 10 is set at an L level as long as an input terminal 1 is set under a high impedance state in an input operation mode. Then a high impedance state detecting signal 4 is delivered.

Description

DETAILED DESCRIPTION OF THE INVENTION (Field of Industrial Application) The present invention relates to an input circuit for a microcomputer, and more particularly to a high impedance state detection input circuit.

(Prior Art) Conventionally, the input circuit of a micro combinator has an input terminal, an input cover connected to the input terminal, a fa, and an input signal holding means for taking in and holding an input signal from the input cover. It consists of , and according to the input circuit side - signal,
I was performing an input operation.

(Problems to be Solved by the Invention) In the conventional input circuit, when the input circuit is controlled to perform an input operation by the input circuit control signal pressure, a normal input signal from the outside is not applied to the input terminal. If the input terminal is in a high-impedance state, it is impossible to detect that the input signal is an unstable signal due to a high-impedance state, even though K takes in signals that are more unstable than K, such as noise. It was impossible.

For this reason, when developing or evaluating a system using a microcomputer equipped with a conventional input circuit, the microcomputer inputs signals from input terminals in a no-impedance state, resulting in unstable information. Even if it worked, it would be very difficult to discover, and the unstable information above would be used to proceed with the design and evaluation, causing great damage and significantly delaying the development schedule. , and incurs extra costs, and in the worst case,
There was a problem that there was a risk of causing a market defect.0 An object of the present invention is to solve the above problem and to
An object of the present invention is to provide a high impedance state detection input circuit that detects when an input terminal is in a high impedance state and generates a high impedance state detection signal.

(Means for Solving the Problems) The high impedance state detection input circuit of the present invention includes an input terminal, and a first resistive element connected between the input terminal and a high-potential side power source. a first control means capable of making conduction or non-conduction between the input terminal and the high-potential power source, and a second resistive element connected between the input terminal and the low-potential power source; and a second control means capable of making conduction or non-conduction between the IEI control means and the low potential side power source; A first input signal holding means for holding an input signal to be inputted with end preload, and either one of the first control means or the second control means are made conductive and the other is made non-conductive, and the signal is input to the input terminal. a second input signal holding means for holding an input signal; a determining means for comparing the contents held by the first input signal holding means and the second input signal holding means and outputting a signal indicating the result; (Example) Next, an example of the present invention will be described with reference to the drawings.

FIG. 1 is a circuit diagram of an embodiment of the present invention. This embodiment shows an input terminal 1, a high potential side voltage 23, and an input terminal 1.
and input terminal 1 through the first resistive element 29.
A P-channel transistor 21 as a first control means capable of conducting or non-conducting between the input terminal l and the high potential side power source 23, and a second resistor between the input terminal l and the low potential side power source 23. An N-channel transistor 18 as a second control means that is connected via an element 28 and can be made conductive or non-conductive between the input terminal 1 and the low potential side power supply 22, and both of these transistors 21 and 18. an initial input signal holding means 14 as a first input signal holding means for holding the input signal 11 which is inputted to the input terminal IK by making it non-conductive; and the transistor 21 or the transistor 18.
final input signal holding means 27 as a second input signal holding means for holding the input signal 11 that is input to the input terminal IK by making one of them conductive and the other non-conducting; The input signal holding means is configured to include an exclusive OR circuit 24 as a determining means for comparing the contents held in the input signal holding means and outputting the result.

Next, the operation of this embodiment will be explained.

Figure 2 is a waveform diagram of each signal when a normal input signal is applied from the outside to the input terminal during the input operation of the circuit shown in Figure 1, and Figure 3 is the input terminal of the circuit shown in Figure 1. FIG. 3 is a waveform diagram of each signal when is in a high impedance state.

First, the control signal will be explained.

The input circuit of this embodiment is controlled by an input circuit control signal 2. When the input circuit control signal 2 is at H level (high potential side power supply potential), an input operation is performed. The input circuit control signal 20 waveform is shown at 2 in FIG. The input circuit control signal 2 is
It is input to the two-man power AND circuit 12 together with the input signal 11, and when the input circuit control signal 2 is at L level (low potential side power supply potential), the two-man power AND circuit 12 performs an input cover, regardless of the state of the input signal 11. When the buffer signal 13 is at L level and at H level, the level of input buffer signal 130 is determined based on the state of input signal 11. In addition, input circuit control signal 2
is input to the final input signal holding means 27, and when the input circuit control signal 2 is at H level, the final input signal holding means 27
Input buffer 7 takes in the signal 13 and outputs it to the final input signal 3.
3 is held and output as the final input signal 3.

Next, the input circuit control signal 2 is input to the signal delay means 5, which delays the input circuit control signal 2 and outputs a control delay signal 6. The waveform of the control delay signal 6 is
Indicated by 6 in the figure. Furthermore, the input circuit control signal 2Fi and the control delay signal 6 are input to the two-man power AND circuit 9, and the two-man power AND circuit 9 outputs the control signal 1 to the detection signal holding means 25.
When the control signal 10 is at H level, the detection signal holding means 25 takes in the output signal of the exclusive OR circuit 24 and outputs it to the 70-ting state detection signal 4, and when it is at L level, it outputs 0. The output signal of the exclusive OR circuit 24 is held and outputted to the floating state detection signal 4. The control delay signal 6 is input to the two-man power AND circuit 9, as well as to the two-man power AND circuit 16 and the inverter 7.

The two-man power AND circuit 16 sets the gate signal 17 to the L level when the control delay signal 8 is at the L level, regardless of the initial input signal 15 which is another input (thereby turning the N-channel transistor 18 into the OFF state). When it is at H level, based on the initial input signal 15, through the gate signal 17,
Controls the N-channel transistor 18 and inverter 7
#'i, the control delay signal 6 is inverted and the inverted control signal 8 is output. The inverted control signal 80 waveform is shown at 8 in FIG.

Input 8 inverted control signals and 14tC of initial input holding means,
The initial input signal holding means 14 takes in the input cover 7a signal 13 when the inversion control signal 8 is at the H level, and outputs it as the initial input signal 15, and when it is at the L level.

The input capacitor 7a signal 13 at the time of falling is held and outputted to the initial input signal 15.

19 turns off the P-channel transistor 21 by setting the gate signal 20 to H level regardless of the initial input signal 15 when the inverted control signal 8 is at H level, and when it is at L level, the initial input signal 15 is turned off. Based on this, the P-channel transistor 21 is controlled through the gate signal 2o.

Next, the input operation of this embodiment will be explained.

The input operation will be explained in two cases: when a normal input signal is applied to the input terminal 1 from the outside, and when the input terminal is in a high impedance state.

First, while referring to Figure 2, connect the external H to input terminal 1.
A case will be explained in which a normal input signal of level (or L level) is given.

At timing tst, the control delay signal 6 is at L level and the inverted control signal 8 is at H level.
The N-channel transistor 18 and the P-channel transistor 21 are turned off by the ND circuit 16 and the two-man OR circuit 19, and are open to the input terminal 1#'i high potential side current 23 and low potential side power supply 22.

The input signal 11 from timing t1 to t3 is taken into the initial input signal holding means 14 through the two-man AND circuit 12 and the input buffer signal 13 in synchronization with timing t: which is the rising edge of the input circuit control signal 2. Furthermore, the H level (or L level) state at the fall timing ts of the 1 inverted control signal 8 is held by the initial input signal holding means 14.

Next, from timing t3 to timing ts, the
Since the delayed signal 6 is at H level and the inverted control signal 8 is at L level, the two-man AND circuit 16 turns on the N-channel transistor 18 based on the fact that the initial input signal 15 is at H level (or L level). By turning the P-channel transistor 21 off (or on), the two-man OR circuit 19 turns the input terminal 1 through the second resistance element 28 (or the first resistance element 29). , pulled down (or pulled up).

However, the input terminal l is normally applied with H level (or L level) from the outside, and the second resistive element 2
8 (or the first resistance element 29) has a sufficiently high resistance value, the level of the input signal 11 hardly changes, and from timing t3 to timing 1. Also, timing t!
In the same way as from to timing t3, the H level (or L level) is connected to the two-man power A N D circuit 12 and the input cover 7.
is taken into the final input signal holding means 27 through the
After the falling timing t4 of the input circuit control signal 2, it is held and further output to the final input signal 3.

The exclusive OR circuit 24 inputs the initial input signal 15 and the final input signal 3, and since both signals are at the H level and match, it outputs the L level, and the detection signal holding means 25 receives the control signal. 10 is at H level from timing t3 to timing t4, the output of the exclusive OR circuit 24 is taken in, the high impedance state detection signal 4 is output, and the control
After timing t4 when signal 10 becomes L level, the L level, which is the output of exclusive OR circuit 24 at timing 14, is held and output as high impedance state detection signal 4, and during input operation, input terminal 1 is connected to the external This indicates that a normal signal is being applied from the terminal and is not in a high impedance state.

Next, with reference to the waveforms of each signal shown in FIG. 3, a case will be described in which the input terminal 1 is in an impedance state during input operation.

Until timing ts, the control delay signal 6 is at L level and the inverted control signal 8 is at H level, so the two-man AND circuit 1
The N-channel transistor 18 and the P-channel transistor 21 are in an off state due to the circuit 19, and the input terminal 1 is connected to the high potential side power supply 23 and the low potential side power supply 2.
It is open to 2.

From timing t1 to timing 1. Input signal up to 11
The timing ts, which is the rising edge of the input circuit control signal 2, is determined as an H level (or L level) signal due to noise, input interference, characteristics of the transistors constituting 7A, etc.
K is synchronized and taken into the initial input signal holding means 14 through the two-man AND circuit 12 and the input buffer signal 13,
Further, the timing t3 when the inversion control signal 8 falls at 9
Thereafter, it is held by the initial input signal holding means 14tC.

Next 1 Timing 1. From timing 1. Until then, the control delay signal 6 is at H level and the inverted control signal 8 is at L level, so the initial input signal 15 is at H level (or L level).
Based on this, the two-man power AND circuit 16 turns the N-channel transistor 18 on (or off), and the two-man power OR circuit 19 turns the P-channel transistor 21
By turning off (or on), the input terminal 1 is pulled down (or pulled down) to the low potential power supply 22 (or high potential power supply 23) through the second resistance element 28 (or first resistance element 29) or pulled up) and becomes a stable L level. Therefore, from timing t3 to timing t, l(
At this time, the input signal 11 is at L level (or H level), is taken into the final input signal holding means 27 through the two-man AND circuit 12, the input cover, and the filter 13, and is taken in by the final input signal holding means 27 at the falling edge of the input circuit control signal 20. It is held after timing t4.

Furthermore, it is output to the final input signal 3.

The exclusive OR circuit 24 inputs the initial input signal 15 and the final input signal 3, detects a mismatch between the two signals, and outputs an H level. From a certain timing t3 to timing t4,
The output of the exclusive OR circuit 24 is taken in and outputted as the high impedance state detection signal 4, and after timing t4 when the control signal 10 becomes L level, the output of the exclusive OR circuit 24 at timing 14 is the H level. hold,
A high impedance state detection signal 4 is output, indicating that the input terminal 1 was in a high impedance state during the input operation.

Although only the internal force circuit has been described in the above embodiment, the present invention can of course be applied to a circuit in which an output circuit that shares a terminal is added to an input circuit to serve as an input/output circuit.

(Effects of the Invention) As explained above, when the high impedance state detection input circuit of the present invention performs an input operation, even if a normal input signal is not given to the input terminal and the input terminal is in the high impedance state. For example, since it is possible to detect this and generate a detection signal, it is possible to prevent unstable operation due to noise during input operation of a microcomputer equipped with an input circuit, and to improve the performance of a system using a microcomputer. It has the effect of being effective in early detection of problems during development and evaluation.

[Brief explanation of the drawing]

FIG. 1 is a circuit diagram of one embodiment of the present invention, FIG. 2 is a waveform diagram of each signal when a normal input signal is given during input operation of the circuit shown in FIG. 1, and FIG. FIG. 7 is a waveform diagram of each signal when a normal input signal is not applied to the circuit shown in the figure and the input terminal is in a high impedance state. 1...Input terminal, 2...Input circuit control signal, 3゜3A...Final input signal, 4,4A...
... High impedance detection signal, 5 ... Signal delay means, 6 ... Control delay signal, 7 ...
・Inverter, 8...Inversion control signal, 9...
...Two-person AND circuit, 10...Chest signal,
11. IIA...Input signal, 12...
Two-person AND circuit, 13.13A...input cover,
F signal, 14...Initial input signal holding means, 1
5,15A...Initial input signal, 16...
・Two-person AND circuit, 17.17A...Gate signal, 18...N channel transistor, 1
9...Two-person OR, circuit, 20.2OA...
... Gate signal, 21 ... P channel transistor, 22 ... Low potential side power supply, 23 ...
...High potential side power supply, 24...Exclusive OR circuit,
25...Detection signal holding means, 26...
High impedance detection means, 27... Fine end input signal holding means, 28... Second resistance element, 2
9...First resistance element. Trap 1 Figure 2

Claims (1)

[Claims] an input terminal, and a first resistor connected between the input terminal and a high-potential power source through a first resistance element, and capable of making the input terminal and the high-potential power source conductive or non-conductive. and a first control means that is connected between the input terminal and the low potential side power source via a second resistance element, and is capable of making conduction or non-conduction between the input terminal and the low potential side power source. a first input signal holding means for holding an input signal input to the input terminal by making both the first control means and the second control means non-conductive; a second input signal holding means for holding the input signal input to the input terminal by making one of the control means or the second control means conductive and the other non-conductive; and the first input signal holding means. 1. A high impedance state detection input circuit comprising: a determining means for comparing the contents held in the first input signal holding means and the second input signal holding means and outputting a signal indicating the result.