JPH05343846A - Manufacture of printed wiring board - Google Patents
Manufacture of printed wiring boardInfo
- Publication number
- JPH05343846A JPH05343846A JP30369991A JP30369991A JPH05343846A JP H05343846 A JPH05343846 A JP H05343846A JP 30369991 A JP30369991 A JP 30369991A JP 30369991 A JP30369991 A JP 30369991A JP H05343846 A JPH05343846 A JP H05343846A
- Authority
- JP
- Japan
- Prior art keywords
- inner layer
- via hole
- surface via
- resin
- printed wiring
- Prior art date
- Legal status (The legal status is an assumption and is not a legal conclusion. Google has not performed a legal analysis and makes no representation as to the accuracy of the status listed.)
- Granted
Links
Abstract
Description
【0001】[0001]
【産業上の利用分野】本発明はプリント配線板の製造方
法に関し、特に部品の表面実装に対応した多層プリント
配線板の製造方法に関する。BACKGROUND OF THE INVENTION 1. Field of the Invention The present invention relates to a method for manufacturing a printed wiring board, and more particularly to a method for manufacturing a multilayer printed wiring board which is suitable for surface mounting of components.
【0002】[0002]
【従来の技術】従来、多層プリント配線板において、各
配線層どうしの電気的接続はスルーホールにより行われ
る。又、配線を高密度化するために表裏貫通のスルーホ
ールではなく、例えば最外層とその真下の内層とを電気
的に接続するようなサーフェイスビアホールを用いる例
もある。2. Description of the Related Art Conventionally, in a multilayer printed wiring board, electrical connection between wiring layers is made by through holes. Further, in order to increase the density of wiring, there is also an example in which surface via holes that electrically connect the outermost layer and the inner layer thereunder are used instead of through holes penetrating the front and back.
【0003】一方、近年プリント配線板への部品の実装
方法は、挿入法から急速に表面実装方向へと切り替って
きている。これにより、スルーホールの機能は部品のリ
ードを挿入する機能から各配線層間の電気接続機能へと
変化している。このため、さらに配線密度を向上させる
ために、サーフェイスビアホール上に表面実装用パッド
を配置する方法が注目されている。On the other hand, in recent years, the method of mounting components on a printed wiring board has been rapidly switched from the insertion method to the surface mounting direction. As a result, the function of the through hole is changed from the function of inserting the lead of the component to the function of electrical connection between the wiring layers. Therefore, in order to further improve the wiring density, a method of arranging the surface mounting pads on the surface via holes is drawing attention.
【0004】[0004]
【発明が解決しようとする課題】従来の技術により、銅
張り積層板にサーフェイスビアホールを形成し、この上
に表面実装用パッドを配置したプリント配線板の製造方
法においては、図4の工程図(a)〜(c)に示すよう
に、銅張り積層板1にスルーホール3aをあけ、内層め
っき2を施してサーフェイスビアホール3を形成し、さ
らに露光技術等により内層回路4を形成して内層板を作
成する。この内層板を図5(d)のようにプリプレグ5
を介して積層し、加熱および加圧を同時に行う。その
際、樹脂の溶融が不充分のうちに加圧が行われるため図
5(e),(f)のようにサーフェイスビアホール3に
充分に樹脂が充填されないことがあり、さらに、図6
(g)のように外層めっき6を施してから図6(h)の
ように外層回路8aを形成した後も、実装用パッド8b
にくぼみ9が生じてしまうという問題があった。In the method of manufacturing a printed wiring board in which a surface via hole is formed in a copper-clad laminate and a surface mounting pad is arranged on the surface via hole by the conventional technique, the process diagram of FIG. As shown in a) to (c), a through hole 3a is opened in the copper clad laminate 1, an inner layer plating 2 is applied to form a surface via hole 3, and an inner layer circuit 4 is formed by an exposure technique or the like to form an inner layer plate. To create. This inner layer board is attached to the prepreg 5 as shown in FIG.
And heat and pressurize at the same time. At this time, since the resin is pressed while the resin is not sufficiently melted, the surface via hole 3 may not be sufficiently filled with the resin as shown in FIGS. 5 (e) and 5 (f).
Even after the outer layer plating 6 is applied as shown in (g) and the outer layer circuit 8a is formed as shown in FIG. 6 (h), the mounting pad 8b is also formed.
There was a problem that a hollow 9 was formed.
【0005】このくぼみの発生は部品実装時、例えばパ
ッド上への半田ペーストの印刷時に半田ペースト量の不
均一性等の支障をきたす原因となっている。特に、LS
I等のパッケージのリードピッチはますますせまくなる
傾向にあり、これによりパッド幅もせまくなってきてお
り、パッド表面の均一化は重要な課題となってきてい
る。尚、表面実装用パッドの下にサーフェイスビアホー
ルを配置しない場合は、くぼみが発生しても特に問題に
はなっていない。The occurrence of the depression causes troubles such as non-uniformity of the amount of the solder paste when mounting the component, for example, when printing the solder paste on the pad. In particular, LS
The lead pitch of packages such as I tends to become narrower, and the pad width also becomes narrower, and making the pad surface uniform has become an important issue. Incidentally, when the surface via hole is not arranged under the surface mounting pad, there is no particular problem even if the depression is generated.
【0006】[0006]
【課題を解決するための手段】本発明のプリント配線板
の製造方法は、内部配線層同士を積層する際に、サーフ
ェイスビアホールとなる内層のスルーホールより樹脂を
外部配線層側に流出させてくぼみを埋め、積層後外装表
面を研磨することにより平坦化した実装用パッド面を得
る方法である。According to the method of manufacturing a printed wiring board of the present invention, when the internal wiring layers are laminated, the resin is caused to flow out from the through hole of the inner layer serving as the surface via hole to the external wiring layer side to form the depression. Is buried, and after laminating, the outer surface of the package is polished to obtain a flattened mounting pad surface.
【0007】従って、従来工法のようにサーフェイスビ
アホール部への樹脂充填が不充分になることがなく、
又、余分な流出樹脂は研磨することにより除去できるの
で、外層めっき及び外層回路形成後サーフェイスビアホ
ール上に形成された実装用パッドにくぼみができるよう
なことはなく、極めて平坦なパッド形成が可能となる。Therefore, unlike the conventional method, the resin filling into the surface via hole portion does not become insufficient,
In addition, since excess spilled resin can be removed by polishing, it is possible to form an extremely flat pad without forming recesses on the mounting pads formed on the surface via holes after plating the outer layer and forming the outer layer circuit. Become.
【0008】[0008]
【実施例】次に本発明について図面を参照して説明す
る。図1,図2,図3は本発明の一実施例を説明する図
で、図1(a)〜(c),図2(d)〜(f),図3
(g),(h)は製造工程を示す断面図である。銅張り
積層板1の実装用パッドが位置する部分にスルーホール
用の穴3aをあけ(図1(a))、この銅張り積層板1
に内層めっき2を施すことによりサーフェイスビアホー
ル3を形成する(図1(b))。サーフェイスビアホー
ル3を形成した銅張り積層板1に内層となる層のみ内層
回路4を形成する(図1(c))。内層回路4を形成し
た銅張り積層板(内層板)をプリプレグ5をはさんで積
層する(図2(d))。内層板とプリプレグ5を積層す
ることにより、サーフェイスビアホール3内に樹脂が充
填され、積層板表面に樹脂が流出する(図2(e))。The present invention will be described below with reference to the drawings. 1, FIG. 2, and FIG. 3 are views for explaining one embodiment of the present invention, and FIGS. 1 (a) to 1 (c), 2 (d) to (f), and FIG.
(G), (h) is sectional drawing which shows a manufacturing process. A hole 3a for a through hole is formed in a portion of the copper-clad laminate 1 where the mounting pad is located (FIG. 1 (a)).
Surface via-holes 3 are formed by applying inner layer plating 2 to the substrate (FIG. 1 (b)). The inner layer circuit 4 is formed only on the inner layer on the copper-clad laminate 1 in which the surface via holes 3 are formed (FIG. 1C). A copper clad laminate (inner layer plate) on which the inner layer circuit 4 is formed is laminated with the prepreg 5 interposed therebetween (FIG. 2 (d)). By laminating the inner layer plate and the prepreg 5, the resin is filled in the surface via holes 3 and the resin flows out to the surface of the laminated plate (FIG. 2 (e)).
【0009】ここで、プリプレグ5は従来と樹脂量が同
じものを使用し、まず硬化状態(Bステージ)にあるプ
リプレグ5を内層板で上下にはさんで積層し130℃に
加熱する。その後、プリプレグ5の樹脂が溶融状態(A
ステージ)になった後、真空プレス機により35〜40
気圧で加圧する。この際樹脂量の多いプリプレグを用い
て樹脂流れが多くなるように加熱,加圧等の積層条件を
設定して積層を行えばさらに効果的である。Here, the prepreg 5 has the same amount of resin as the conventional one, and first, the prepreg 5 in the cured state (B stage) is sandwiched between the inner layer plates and is heated to 130.degree. After that, the resin of the prepreg 5 is in a molten state (A
Stage), 35-40 by vacuum press
Pressurize at atmospheric pressure. At this time, it is more effective to use a prepreg with a large amount of resin and set the laminating conditions such as heating and pressurization so that the resin flow increases, and perform laminating.
【0010】積層完了後、ベルトサンダー装置により基
板表面に流出した樹脂を内層めっき2の上層部と共に研
磨除去して平坦にし、続いて部品実装用および表裏導通
用の外層スルーホールを形成するためのスルーホール7
aをあける(図2(f))。これに外層めっき6を施す
ことにより外層スルーホール7を形成する(図3
(g)。その後、図1(a)〜(c)により形成したサ
ーフェイスビアホール3上に表面実装用パッド8bを形
成すると共に外層回路8aを形成し、プリント配線板が
完成する(図3(h))。なお、本実施例の回路形成等
にあたっては、通常の露光技術、エッチング技術等を使
用している。After the completion of the lamination, the resin which has flown out to the surface of the substrate is polished and removed together with the upper layer portion of the inner layer plating 2 by a belt sander device to be flattened, and subsequently, outer layer through holes for mounting components and for conducting the front and back are formed. Through hole 7
Open a (Fig. 2 (f)). An outer layer through hole 7 is formed by applying outer layer plating 6 to this (FIG. 3).
(G). Thereafter, the surface mounting pad 8b is formed on the surface via hole 3 formed according to FIGS. It should be noted that ordinary exposure technology, etching technology and the like are used in the circuit formation and the like of this embodiment.
【0011】[0011]
【発明の効果】以上説明したように本発明は、サーフェ
イスビアーホール上に表面実装用パッドを配置してもパ
ッド表面を平坦に仕上げることができるので、半田ペー
スト量の不均一性が解消され、これにより、挟ピッチの
リード部品実装時の不良を低減できる。As described above, according to the present invention, even if the surface mounting pad is arranged on the surface via hole, the pad surface can be finished flat, so that the non-uniformity of the amount of solder paste can be eliminated. As a result, it is possible to reduce defects when mounting lead components with a narrow pitch.
【図1】本発明の一実施例を説明する図で、同図(a)
〜(c)は製造工程を示すそれぞれ断面図である。FIG. 1 is a diagram for explaining an embodiment of the present invention, in which FIG.
(C) is each sectional drawing which shows a manufacturing process.
【図2】同図(d)〜(f)は図1に続く製造工程を示
すそれぞれ断面図である。2 (d) to (f) are cross-sectional views showing the manufacturing process subsequent to FIG.
【図3】同図(g),(h)は図2に続く製造工程を示
すそれぞれ断面図である。3 (g) and 3 (h) are cross-sectional views showing the manufacturing process following FIG.
【図4】従来の製造方法を説明する図で、同図(a)〜
(c)は製造工程を示すそれぞれ断面図である。FIG. 4 is a diagram for explaining a conventional manufacturing method, which is shown in FIG.
(C) is each sectional drawing which shows a manufacturing process.
【図5】同図(d)〜(f)は図4に続く製造工程を示
すそれぞれ断面図である。5 (d) to 5 (f) are cross-sectional views showing the manufacturing process following FIG.
【図6】同図(g),(h)は図5に続く製造工程を示
すそれぞれ断面図である。6 (g) and 6 (h) are cross-sectional views showing the manufacturing process following FIG.
1 銅張り積層板 2 内層めっき 3 サーフェイスビアホール 3a スルーホール 4 内層回路 5 プリプレグ 6 外層めっき 7 外層スルーホール 7a スルーホール 8a 外層回路 8b 実装用パッド 9 くぼみ 1 Copper-clad laminate 2 Inner layer plating 3 Surface via hole 3a Through hole 4 Inner layer circuit 5 Prepreg 6 Outer layer plating 7 Outer layer through hole 7a Through hole 8a Outer layer circuit 8b Mounting pad 9 Recess
【手続補正書】[Procedure amendment]
【提出日】平成4年3月23日[Submission date] March 23, 1992
【手続補正1】[Procedure Amendment 1]
【補正対象書類名】明細書[Document name to be amended] Statement
【補正対象項目名】0009[Correction target item name] 0009
【補正方法】変更[Correction method] Change
【補正内容】[Correction content]
【0009】ここで、プリプレグ5は従来と樹脂量が同
じものを使用し、まず半硬化状態にあるプリプレグ5を
内層板で上下にはさんで積層し130℃に加熱する。そ
の後、プリプレグ5の樹脂が再溶融状態になった後、真
空プレス機により35〜40気圧で加圧する。この際樹
脂量の多いプリプレグを用いて樹脂流れが多くなるよう
に加熱,加圧等の積層条件を設定して積層を行えばさら
に効果的である。Here, the prepreg 5 has the same amount of resin as the conventional one, and first, the prepreg 5 in a semi-cured state is laminated by an inner layer plate vertically and heated to 130.degree. Then, after the resin of the prepreg 5 is in a re-melted state, it is pressurized with a vacuum press machine at 35 to 40 atmospheres. At this time, it is more effective to use a prepreg with a large amount of resin and set the laminating conditions such as heating and pressurization so that the resin flow increases, and perform laminating.
Claims (2)
イスビアホール上に表面実装用パッドを形成するプリン
ト配線板の製造方法において、あらかじめサーフェイス
ビアホールと内層面にのみ回路を形成した1対の内層板
を内層回路形成面を内側にしてプリプレグを介して積層
し、加熱して前記プリプレグの樹脂を溶融させ、次いで
加圧してサーフェイスビアホールを通して前記溶融樹脂
を外層面側へ流出させ、積層完了後に外層表面を研磨す
る工程を含むことを特徴とするプリント配線板の製造方
法。1. A method of manufacturing a printed wiring board in which a surface mounting pad is formed on a surface via hole that electrically connects a surface layer and an inner layer, and a pair of inner layer boards in which circuits are previously formed only on the surface via hole and the inner layer surface. Is laminated with the inner layer circuit forming surface inside through a prepreg, and the resin of the prepreg is melted by heating, and then the molten resin is flown out to the outer layer surface side through a surface via hole, and after completion of lamination, the outer layer surface A method for manufacturing a printed wiring board, which comprises a step of polishing.
面に施されている内層めっきの下層部分を残して前記流
出樹脂を研磨除去する請求項1記載のプリント配線板の
製造方法。2. The method of manufacturing a printed wiring board according to claim 1, wherein when the outer layer surface is polished, the outflowing resin is removed by polishing while leaving a lower layer portion of the inner layer plating applied to the outer layer surface.
Priority Applications (1)
Application Number | Priority Date | Filing Date | Title |
---|---|---|---|
JP3303699A JP2808951B2 (en) | 1991-11-20 | 1991-11-20 | Manufacturing method of printed wiring board |
Applications Claiming Priority (1)
Application Number | Priority Date | Filing Date | Title |
---|---|---|---|
JP3303699A JP2808951B2 (en) | 1991-11-20 | 1991-11-20 | Manufacturing method of printed wiring board |
Publications (2)
Publication Number | Publication Date |
---|---|
JPH05343846A true JPH05343846A (en) | 1993-12-24 |
JP2808951B2 JP2808951B2 (en) | 1998-10-08 |
Family
ID=17924183
Family Applications (1)
Application Number | Title | Priority Date | Filing Date |
---|---|---|---|
JP3303699A Expired - Lifetime JP2808951B2 (en) | 1991-11-20 | 1991-11-20 | Manufacturing method of printed wiring board |
Country Status (1)
Country | Link |
---|---|
JP (1) | JP2808951B2 (en) |
Cited By (2)
Publication number | Priority date | Publication date | Assignee | Title |
---|---|---|---|---|
US5979044A (en) * | 1997-03-24 | 1999-11-09 | Nec Corporation | Fabrication method of multilayer printed wiring board |
JP2016012699A (en) * | 2014-06-30 | 2016-01-21 | 京セラサーキットソリューションズ株式会社 | Manufacturing method of wiring board |
Citations (2)
Publication number | Priority date | Publication date | Assignee | Title |
---|---|---|---|---|
JPH03120892A (en) * | 1989-10-04 | 1991-05-23 | Nec Corp | Multilayer printed circuit board and manufacture thereof |
JPH04315495A (en) * | 1991-04-15 | 1992-11-06 | Sony Corp | Manufacture of multilayer wiring board |
-
1991
- 1991-11-20 JP JP3303699A patent/JP2808951B2/en not_active Expired - Lifetime
Patent Citations (2)
Publication number | Priority date | Publication date | Assignee | Title |
---|---|---|---|---|
JPH03120892A (en) * | 1989-10-04 | 1991-05-23 | Nec Corp | Multilayer printed circuit board and manufacture thereof |
JPH04315495A (en) * | 1991-04-15 | 1992-11-06 | Sony Corp | Manufacture of multilayer wiring board |
Cited By (2)
Publication number | Priority date | Publication date | Assignee | Title |
---|---|---|---|---|
US5979044A (en) * | 1997-03-24 | 1999-11-09 | Nec Corporation | Fabrication method of multilayer printed wiring board |
JP2016012699A (en) * | 2014-06-30 | 2016-01-21 | 京セラサーキットソリューションズ株式会社 | Manufacturing method of wiring board |
Also Published As
Publication number | Publication date |
---|---|
JP2808951B2 (en) | 1998-10-08 |
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