JPH05343742A - Manufacture of gallium nitride series compound semiconductor chip - Google Patents
Manufacture of gallium nitride series compound semiconductor chipInfo
- Publication number
- JPH05343742A JPH05343742A JP17204292A JP17204292A JPH05343742A JP H05343742 A JPH05343742 A JP H05343742A JP 17204292 A JP17204292 A JP 17204292A JP 17204292 A JP17204292 A JP 17204292A JP H05343742 A JPH05343742 A JP H05343742A
- Authority
- JP
- Japan
- Prior art keywords
- gallium nitride
- layer
- compound semiconductor
- sapphire substrate
- type
- Prior art date
- Legal status (The legal status is an assumption and is not a legal conclusion. Google has not performed a legal analysis and makes no representation as to the accuracy of the status listed.)
- Granted
Links
Classifications
-
- H—ELECTRICITY
- H01—ELECTRIC ELEMENTS
- H01S—DEVICES USING THE PROCESS OF LIGHT AMPLIFICATION BY STIMULATED EMISSION OF RADIATION [LASER] TO AMPLIFY OR GENERATE LIGHT; DEVICES USING STIMULATED EMISSION OF ELECTROMAGNETIC RADIATION IN WAVE RANGES OTHER THAN OPTICAL
- H01S5/00—Semiconductor lasers
- H01S5/02—Structural details or components not essential to laser action
- H01S5/0201—Separation of the wafer into individual elements, e.g. by dicing, cleaving, etching or directly during growth
-
- H—ELECTRICITY
- H01—ELECTRIC ELEMENTS
- H01S—DEVICES USING THE PROCESS OF LIGHT AMPLIFICATION BY STIMULATED EMISSION OF RADIATION [LASER] TO AMPLIFY OR GENERATE LIGHT; DEVICES USING STIMULATED EMISSION OF ELECTROMAGNETIC RADIATION IN WAVE RANGES OTHER THAN OPTICAL
- H01S5/00—Semiconductor lasers
- H01S5/02—Structural details or components not essential to laser action
- H01S5/0201—Separation of the wafer into individual elements, e.g. by dicing, cleaving, etching or directly during growth
- H01S5/0202—Cleaving
-
- H—ELECTRICITY
- H01—ELECTRIC ELEMENTS
- H01S—DEVICES USING THE PROCESS OF LIGHT AMPLIFICATION BY STIMULATED EMISSION OF RADIATION [LASER] TO AMPLIFY OR GENERATE LIGHT; DEVICES USING STIMULATED EMISSION OF ELECTROMAGNETIC RADIATION IN WAVE RANGES OTHER THAN OPTICAL
- H01S5/00—Semiconductor lasers
- H01S5/30—Structure or shape of the active region; Materials used for the active region
- H01S5/32—Structure or shape of the active region; Materials used for the active region comprising PN junctions, e.g. hetero- or double- heterostructures
- H01S5/323—Structure or shape of the active region; Materials used for the active region comprising PN junctions, e.g. hetero- or double- heterostructures in AIIIBV compounds, e.g. AlGaAs-laser, InP-based laser
- H01S5/32308—Structure or shape of the active region; Materials used for the active region comprising PN junctions, e.g. hetero- or double- heterostructures in AIIIBV compounds, e.g. AlGaAs-laser, InP-based laser emitting light at a wavelength less than 900 nm
- H01S5/32341—Structure or shape of the active region; Materials used for the active region comprising PN junctions, e.g. hetero- or double- heterostructures in AIIIBV compounds, e.g. AlGaAs-laser, InP-based laser emitting light at a wavelength less than 900 nm blue laser based on GaN or GaP
Landscapes
- Dicing (AREA)
- Led Devices (AREA)
Abstract
Description
【０００１】[0001]
【産業上の利用分野】本発明は青色発光ダイオード、青
色レーザーダイオード等の発光デバイスに使用される窒
化ガリウム系化合物半導体チップの製造方法に係り、特
に、サファイア基板上に積層された窒化ガリウム系化合
物半導体の結晶性を損ねること無くチップ状に分離する
方法に関する。BACKGROUND OF THE INVENTION 1. Field of the Invention The present invention relates to a method for manufacturing a gallium nitride compound semiconductor chip used in a light emitting device such as a blue light emitting diode or a blue laser diode, and more particularly to a gallium nitride compound compound laminated on a sapphire substrate. The present invention relates to a method for separating a semiconductor into chips without damaging the crystallinity.
【０００２】[0002]
【従来の技術】一般に発光ダイオード、レーザダイオー
ド等の発光デバイスはステム上に発光源である半導体チ
ップが設置されている。その半導体チップを構成する材
料として、例えば赤色、橙色、黄色、緑色発光ダイオー
ドではＧａＡｓ、ＧａＡｌＡｓ、ＧａＰ等が知られてい
る。青色ダイオード、青色レーザーダイオードについて
は、数々の半導体材料が研究されているが、未だ実験段
階であり実用化には至っていない。しかし、実用的な青
色発光材料として、ＧａＮ、ＩｎＧａＮ、ＧａＡｌＮ等
の窒化ガリウム系化合物半導体が注目されている。2. Description of the Related Art Generally, in a light emitting device such as a light emitting diode or a laser diode, a semiconductor chip as a light emitting source is installed on a stem. Known materials for forming the semiconductor chip include GaAs, GaAlAs, and GaP for red, orange, yellow, and green light-emitting diodes. Although various semiconductor materials have been studied for blue diodes and blue laser diodes, they are still in the experimental stage and have not been put to practical use. However, gallium nitride-based compound semiconductors such as GaN, InGaN, and GaAlN are receiving attention as practical blue light emitting materials.
【０００３】従来、半導体材料が積層されたウエハーを
チップに分離する方法としては一般にダイサー、または
スクライバーが使用されている。ダイサーとは通常ダイ
シングソーとも呼ばれ、刃先をダイヤモンドとする円盤
の回転運動により、ウエハーをフルカットするか、また
は刃先巾よりも広い巾の溝を切り込んだ後、外力によっ
てカットする装置である。一方、スクライバーとは先端
をダイヤモンドとする針の往復直線運動によりウエハー
に極めて細いスクライブライン（罫書線）を、例えば碁
盤目状に引いた後、外力によってカットする装置であ
る。Conventionally, a dicer or a scriber is generally used as a method for separating a wafer in which semiconductor materials are laminated into chips. A dicer is usually called a dicing saw, and is a device that cuts a wafer by an external force after the wafer is fully cut by a rotary motion of a disk having a diamond edge, or a groove having a width wider than the edge width is cut. On the other hand, the scriber is a device that draws an extremely thin scribe line (scoring line) on the wafer by reciprocating linear motion of a needle having a diamond tip, for example, in a grid pattern, and then cuts by an external force.
【０００４】[0004]
【発明が解決しようとする課題】前記ＧａＰ、ＧａＡｓ
等のせん亜鉛構造の結晶はへき開性が「１１０」方向に
あるため、この性質を利用してスクライバーで、この方
向にスクライブラインを入れることによりチップ状に簡
単に分離できる。しかしながら、窒化ガリウム系化合物
半導体はサファイア基板の上に積層されるいわゆるヘテ
ロエピ構造であり、窒化ガリウム系化合物半導体とサフ
ァイアとは格子定数不整が大きい。さらに、サファイア
は六方晶系という結晶の性質上、へき開性を有していな
い。従って、スクライバーで切断することは不可能であ
った。また、サファイア、窒化ガリウム系化合物半導体
ともモース硬度がほぼ９と非常に硬い物質であるため、
ダイサーでフルカットすると、その切断面にクラック、
チッピングが発生しやすくなり、綺麗に切断できなかっ
た。さらに、ダイサーの刃が長時間ウエハー切断面に接
することにより、ウエハーの横方向に応力（ストレス）
が生じる。このため、特にｎ型層とｐ型層との界面にク
ラック、チッピング等が発生しやすくなり、肝心の窒化
ガリウム系化合物半導体の結晶性を損ねてしまうため、
輝度が低下したり、寿命が非常に短くなってしまうとい
う問題点があった。The above GaP, GaAs
Since a crystal having a zinc-zinc structure such as Cleavage has a cleavage property in the “110” direction, it can be easily separated into chips by using a scriber by inserting a scribe line in this direction. However, the gallium nitride-based compound semiconductor has a so-called heteroepitaxial structure stacked on the sapphire substrate, and the lattice constant of the gallium nitride-based compound semiconductor and sapphire is large. Furthermore, sapphire does not have cleavage due to the crystal property of hexagonal system. Therefore, it was impossible to cut with a scriber. In addition, since sapphire and gallium nitride-based compound semiconductors are very hard materials with a Mohs hardness of about 9,
When full cut with a dicer, cracks on the cut surface,
Chipping was likely to occur and it was not possible to cut it neatly. In addition, the blade of the dicer is in contact with the cut surface of the wafer for a long time, which causes stress in the lateral direction of the wafer.
Occurs. For this reason, cracks, chippings and the like are likely to occur particularly at the interface between the n-type layer and the p-type layer, and the crystallinity of the gallium nitride-based compound semiconductor, which is essential, is impaired.
There are problems that the brightness is lowered and the life is extremely shortened.
【０００５】従って、本発明はサファイアを基板とする
窒化ガリウム系化合物半導体ウエハーをチップ状にカッ
トするに際し、切断面、界面のクラック、チッピングの
発生を防止し、窒化ガリウム系化合物半導体の結晶性を
損なうことなく優れた発光性能を有する窒化ガリウム系
化合物半導体チップを得ると共に、歩留良く所望の形、
サイズに切断する方法を提供することを目的とするもの
である。Therefore, according to the present invention, when a gallium nitride-based compound semiconductor wafer using sapphire as a substrate is cut into chips, cracks at the cut surface, interfaces, and chipping are prevented, and the crystallinity of the gallium nitride-based compound semiconductor is improved. In addition to obtaining a gallium nitride-based compound semiconductor chip having excellent light emission performance without loss, a desired shape with good yield,
It is intended to provide a method of cutting to size.
【０００６】[0006]
【課題を解決するための手段】本発明の窒化ガリウム系
化合物半導体チップの製造方法は、サファイア基板上に
ｎ型およびｐ型の窒化ガリウム系化合物半導体が順に積
層されたウエハーをチップ状に分離する方法であって、
サファイア基板を研磨して薄くする工程と、ｐ型層
の一部をｎ型層までエッチングする工程と、ｎ型層を
サファイア基板までエッチング、またはダイシングする
工程と、サファイア基板をダイシング、またはスクラ
イビングにより切断する工程と、を具備することを特徴
とするものである。According to the method of manufacturing a gallium nitride compound semiconductor chip of the present invention, a wafer in which n-type and p-type gallium nitride compound semiconductors are sequentially stacked on a sapphire substrate is separated into chips. Method,
By polishing and thinning the sapphire substrate, etching a part of the p-type layer to the n-type layer, etching or dicing the n-type layer to the sapphire substrate, and dicing or scribing the sapphire substrate. And a step of cutting.
【０００７】以下、本発明の一実施例の製造方法を図面
を参照しながら詳説する。図１〜図６は窒化ガリウム系
化合物半導体ウエハー、および素子の構造を示す断面図
であり、１はサファイア基板、２はｎ型窒化ガリウム系
化合物半導体層（以下ｎ型層という。）、３はｐ型窒化
ガリウム系化合物半導体層（以下ｐ型層という。）であ
る。但し、本発明の方法は、図面の構造の窒化ガリウム
系化合物半導体ウエハーにのみ適用されるものではな
い。A manufacturing method according to an embodiment of the present invention will be described below in detail with reference to the drawings. 1 to 6 are cross-sectional views showing the structures of gallium nitride-based compound semiconductor wafers and devices, 1 is a sapphire substrate, 2 is an n-type gallium nitride-based compound semiconductor layer (hereinafter referred to as n-type layer), and 3 is. It is a p-type gallium nitride-based compound semiconductor layer (hereinafter referred to as p-type layer). However, the method of the present invention is not applied only to the gallium nitride-based compound semiconductor wafer having the structure shown in the drawing.
【０００８】通常、窒化ガリウム系化合物半導体ウエハ
ーの厚さは、サファイア基板１で４００〜８００μｍ、
その上に積層されたｎ型層２、およびｐ型層３の厚さは
多くても十数μｍであり、そのほとんどがサファイア基
板１の厚さで占められている。従って、の工程におい
て、サファイア基板１を研磨して、その厚さを５０〜３
００μｍに調整することが好ましい。５０μｍよりも薄
いと、ウエハー全体が割れ易くなったり、またウエハー
に反りが生じる傾向にある。また、３００μｍよりも厚
いと、の工程において、ダイシング、またはスクライ
ビングによる切断の際にサファイア基板にチッピング、
クラックが発生しやすくなる。またスクライビングする
場合は、スクライブラインを深くしなければならないた
め、細かいチップができにくくなり、チップ分離が困難
になる傾向がある。研磨された基板のさらに好ましい厚
さとしては１００〜２００μｍである。なお、の工程
は、の工程の後に行ってもよい。Generally, the gallium nitride compound semiconductor wafer has a thickness of 400 to 800 μm on the sapphire substrate 1.
The thickness of the n-type layer 2 and the p-type layer 3 laminated thereon is at most tens of μm, and most of them are occupied by the thickness of the sapphire substrate 1. Therefore, in the step of, the sapphire substrate 1 is polished to a thickness of 50 to 3
It is preferably adjusted to 00 μm. If the thickness is less than 50 μm, the entire wafer tends to be cracked or the wafer tends to warp. Further, when the thickness is thicker than 300 μm, chipping on the sapphire substrate during dicing or cutting by scribing in the step of
Cracks are likely to occur. In addition, when scribing, since the scribe line must be deep, it is difficult to form fine chips, and chip separation tends to be difficult. A more preferable thickness of the polished substrate is 100 to 200 μm. The step of may be performed after the step of.
【０００９】まず、サファイア基板１上に、ｎ型層２、
およびｐ型層３が順に積層されたウエハーの、最上層で
あるｐ型層３上に、図１に示すように保護膜４を設け
る。保護膜４はｐ型層３がエッチングにより侵食される
のを防ぐと共に、パターンエッチングを行うために設け
るものであって、フォトレジストでパターニングした
後、例えばＳｉＯ2等の材料でプラズマＣＶＤ法を用い
て形成することができる。なお、この図においてサファ
イア基板１は予め研磨して薄くしてある。First, on the sapphire substrate 1, the n-type layer 2,
As shown in FIG. 1, a protective film 4 is provided on the uppermost p-type layer 3 of the wafer in which the and p-type layers 3 are sequentially stacked. The protective film 4 is provided to prevent the p-type layer 3 from being corroded by etching and to perform pattern etching. After patterning with a photoresist, a plasma CVD method using a material such as SiO 2 is used. Can be formed. In this figure, the sapphire substrate 1 has been thinned by polishing in advance.
【００１０】次に、保護膜４が設けられたｐ型層３を、
ｎ型層２までエッチングする（の工程）。エッチング
方法はドライ、ウエットいずれの方法でもよい。エッチ
ング終了後、図２に示すように、酸により保護膜４を除
去する。Next, the p-type layer 3 provided with the protective film 4 is
Etching is performed up to the n-type layer 2 (step of). The etching method may be either dry or wet. After the etching is completed, as shown in FIG. 2, the protective film 4 is removed with acid.
【００１１】さらに、図３に示すように、ｎ型層２の表
面にｎ型電極を設けられるスペースを残して、ｎ型層２
をサファイア基板１までエッチング、またはダイシング
する（の工程）。ｎ型層２とサファイア基板１の界面
にできるだけストレスをかけないようにするには、エッ
チングが好ましい。エッチングする場合には、前述した
ように保護膜をエッチング面以外（ｐ型層３とｎ型層２
の電極形成部分）に形成する必要がある。Further, as shown in FIG. 3, the n-type layer 2 is left on the surface of the n-type layer 2 leaving a space for providing an n-type electrode.
Is etched or diced up to the sapphire substrate 1 (step of). Etching is preferred in order to minimize stress on the interface between the n-type layer 2 and the sapphire substrate 1. In the case of etching, as described above, the protective film is formed on the surface other than the etching surface (p-type layer 3 and n-type layer 2).
Electrode forming part).
【００１２】次に、図４に示すように、の工程により
露出されたサファイア基板をスクライビングして、スク
ライブライン（罫書線）５を入れた後、サファイア基板
側から押し割って分離する（の工程）。の工程によ
りサファイア基板の厚さを薄くしているため、スクライ
ブライン５を入れて押し割ることによって、綺麗にチッ
プ状に分離することができる。スクライブラインの深さ
は特に規定するものではないが、基板の厚さの５％以上
の深さで入れることにより、へき開性の無いサファイア
でも切断面をほぼ平面状とすることができ、好ましく切
断できる。Next, as shown in FIG. 4, the sapphire substrate exposed in the step (1) is scribed, scribe lines (scoring lines) 5 are inserted, and then the sapphire substrate is separated by being crushed. ). Since the thickness of the sapphire substrate is thinned by the step of 3, the chip can be neatly separated by inserting the scribe line 5 and pressing. The depth of the scribe line is not particularly specified, but by inserting it at a depth of 5% or more of the thickness of the substrate, even sapphire without cleavage can make the cut surface into a substantially flat surface, which is preferable. it can.
【００１３】また、図５に示すように、ダイシングによ
りサファイア基板１を直接フルカットしてもよい。この
場合においても、サファイア基板１を予め薄くしてある
ためダイシング時間を短縮でき、ストレスをかけずに綺
麗に切断できる。Further, as shown in FIG. 5, the sapphire substrate 1 may be directly full-cut by dicing. Even in this case, since the sapphire substrate 1 is thinned in advance, the dicing time can be shortened and the cutting can be performed neatly without applying stress.
【００１４】[0014]
【作用】図６は、の工程のスクライビングまたはダイ
シングによって分離された窒化ガリウム系化合物半導体
素子のｎ型層２、およびｐ型層３に電極６を形成した状
態を示す断面図である。FIG. 6 is a cross-sectional view showing a state in which electrodes 6 are formed on the n-type layer 2 and the p-type layer 3 of the gallium nitride-based compound semiconductor device separated by the scribing or dicing in the step of.
【００１５】この図において、ｎ型層２とｐ型層３の界
面、即ち、ｐ−ｎ接合面はエッチングされているため、
この界面には従来のダイシングによるストレスはかかっ
ておらず、窒化ガリウム系化合物半導体結晶の損傷はほ
とんど無い。さらに、サファイア基板１とｎ型層２の界
面においても、予めの工程により、ｎ型層２の途中ま
でエッチングされているため、ダイシングを行うにして
も、その切断深さを短くすることができるため、ストレ
スのかかる割合が従来に比して大幅に減少する。従っ
て、本発明の方法により得られた窒化ガリウム系化合物
半導体チップは、格子不整合に起因する窒化ガリウム系
化合物半導体層のクラック、チッピングが防止されてお
り、半導体結晶を損傷すること無く結晶性が保持されて
いる。また、サファイア基板を研磨して薄くすることに
より、へき開性のないサファイア基板でもスクライブで
綺麗に切断でき、またダイシングにおいても切断時間を
短縮できるという優れた利点がある。In this figure, since the interface between the n-type layer 2 and the p-type layer 3, that is, the pn junction surface is etched,
No stress is applied to this interface by conventional dicing, and the gallium nitride-based compound semiconductor crystal is hardly damaged. Furthermore, even at the interface between the sapphire substrate 1 and the n-type layer 2, the cutting depth can be shortened even if dicing is performed, because the n-type layer 2 is etched halfway through a previous process. Therefore, the rate of stress is significantly reduced compared to the conventional case. Therefore, the gallium nitride-based compound semiconductor chip obtained by the method of the present invention is prevented from cracking and chipping of the gallium nitride-based compound semiconductor layer due to lattice mismatch, and has crystallinity without damaging the semiconductor crystal. Is held. Further, by polishing and thinning the sapphire substrate, even a sapphire substrate having no cleavage property can be cut beautifully by scribing, and the cutting time can be shortened in dicing.
【００１６】[0016]
【実施例】以下、本発明の窒化ガリウム系化合物半導体
チップの製造方法を実施例で説明する。EXAMPLES Hereinafter, a method for manufacturing a gallium nitride-based compound semiconductor chip of the present invention will be described with reference to examples.
【００１７】［実施例１］厚さ４５０μｍ、大きさ２イ
ンチφのサファイア基板上に、順にｎ型ＧａＮ層とｐ型
ＧａＮ層を合わせて５μｍの厚みで成長させた発光ダイ
オード用のＧａＮエピタキシャルウエハーのｐ型ＧａＮ
層に、フォトレジストでパターンを形成する。[Example 1] A GaN epitaxial wafer for a light-emitting diode, in which an n-type GaN layer and a p-type GaN layer were sequentially grown to a thickness of 5 μm on a sapphire substrate having a thickness of 450 μm and a size of 2 inches φ. P-type GaN
The layer is patterned with photoresist.
【００１８】フォトレジストの上からプラズマＣＶＤ法
により保護膜としてＳｉＯ2膜を０．１μｍの膜厚で形
成した後、溶剤によりフォトレジストを剥離して、パタ
ーニングされたＳｉＯ2膜を残す。A SiO 2 film having a film thickness of 0.1 μm is formed as a protective film on the photoresist by a plasma CVD method, and then the photoresist is removed by a solvent to leave the patterned SiO 2 film.
【００１９】ウエハーをリン酸と硫酸の混酸に浸漬し、
ｐ型ＧａＮ層をｎ型ＧａＮ層までエッチングする。The wafer is immersed in a mixed acid of phosphoric acid and sulfuric acid,
Etch the p-type GaN layer to the n-type GaN layer.
【００２０】エッチング後、研磨機にてサファイア基板
を１５０μｍまで研磨する。After etching, the sapphire substrate is polished to 150 μm with a polishing machine.
【００２１】研磨後、ウエハーをダイシングソーに設置
し、ブレード回転数３０,０００ｒｐｍ、切断速度０．
３ｍｍ/secの条件で、ダイヤモンドブレードにて、所定
のカットライン（３５０μｍ角）上を２０μｍの深さで
ダイシングする。After polishing, the wafer was placed on a dicing saw, the blade rotation speed was 30,000 rpm, and the cutting speed was 0.
Under a condition of 3 mm / sec, a diamond blade is used to perform dicing at a depth of 20 μm on a predetermined cut line (350 μm square).
【００２２】次に、基板側に粘着テープを貼付し、スク
ライバーのテーブル上に張り付け、真空チャックで固定
する。テーブルはｘ軸（左右）、ｙ軸（前後）に動き、
１８０度水平に回転可能な構造となっている。固定後、
スクライバーのダイヤモンド刃でダイシングの跡をスク
ライブしてラインを引く。ダイヤモンド刃が設けられた
バーはｚ軸（上下）、ｙ軸（前後）方向に移動可能な構
造となっている。ダイヤモンド刃の刃先への加重は１０
０ｇとし、スクライブラインの深さを深くするため、同
一のラインを２回スクライブすることにより深さ１０μ
ｍとする。Next, an adhesive tape is attached to the substrate side, stuck on the table of the scriber, and fixed with a vacuum chuck. The table moves on the x-axis (left and right) and the y-axis (front and back),
It has a structure that can be horizontally rotated 180 degrees. After fixing
Use the diamond blade of the scribe to scribe the dicing marks and draw a line. The bar provided with the diamond blade has a structure that can move in the z-axis (up and down) and y-axis (back and forth) directions. The weight of the diamond blade is 10
In order to increase the depth of the scribe line to 0 g, the same line is scribed twice to obtain a depth of 10 μm.
m.
【００２３】スクライブラインを引いたＧａＮウエハー
をテーブルから剥し取り、サファイア基板側からローラ
ーにより圧力を加えて、押し割ることによりＧａＮチッ
プを得た。A GaN wafer with a scribe line was peeled off from the table, pressure was applied from the sapphire substrate side by a roller, and the wafer was pressed to obtain a GaN chip.
【００２４】このようにして得られたＧａＮチップより
外形不良によるものを取り除いたところ、歩留は９５％
以上であった。また、このＧａＮチップのｐ型ＧａＮ
層、およびｎ型ＧａＮ層にＡｕ電極を取り付けた後、常
法に従い発光ダイオードとしたところ、順方向電圧４．
０Ｖにおいて、発光出力は５０μＷ、発光寿命は５００
０時間以上であった。From the GaN chips thus obtained, the defects due to the outer shape were removed, and the yield was 95%.
That was all. In addition, p-type GaN of this GaN chip
After the Au electrode was attached to the layer and the n-type GaN layer, a light emitting diode was formed by a conventional method.
At 0 V, the emission output is 50 μW and the emission life is 500
It was over 0 hours.
【００２５】［比較例１］実施例１と同一のＧａＮエピ
タキシャルウエハーを、同様にしてｎ型ＧａＮ層までエ
ッチングした後、サファイア基板を研磨せずに、直接ダ
イサーを用い、同じくブレード回転数３０,０００ｒｐ
ｍ、切断速度０．３ｍｍ／ｓｅｃの条件で、３５０μｍ
角のチップにフルカットしたところ、切断線に対し無数
のクラックが生じ、歩留は３０％以下であった。また、
残ったＧａＮチップのｐ型層およびｎ型層に同じくＡｕ
電極を取り付け、発光ダイオードとしたところ、順方向
電圧４．０Ｖにおいて、発光出力２０μＷ、発光寿命は
５０〜７０時間であった。[Comparative Example 1] The same GaN epitaxial wafer as in Example 1 was similarly etched to the n-type GaN layer, and then the sapphire substrate was not polished but a direct dicer was used and the blade rotation speed was 30, 000rp
m, cutting speed 0.3 mm / sec, 350 μm
When full-cut into square chips, countless cracks were generated on the cutting line, and the yield was 30% or less. Also,
Au was also used for the p-type layer and the n-type layer of the remaining GaN chip.
When an electrode was attached to form a light emitting diode, the emission output was 20 μW and the emission life was 50 to 70 hours at a forward voltage of 4.0 V.
【００２６】[0026]
【発明の効果】以上述べたように、本発明の方法による
と、ｐｎ接合部はストレス無く分離できることで、従来
問題となっていた特性劣化、特に発光寿命、発光出力に
おいて大幅な改善が認められた。また、窒化ガリウム系
化合物半導体とサファイア基板との格子定数不整から生
じる、結晶面のクラック、チッピング等を防止でき、窒
化ガリウム系化合物半導体チップを歩留良く製造でき、
その産業上の利用価値は大きい。As described above, according to the method of the present invention, the pn junction can be separated without stress, so that the characteristic deterioration which has been a problem in the related art, in particular, the emission life and the emission output are significantly improved. It was Further, cracks on the crystal plane, which may be caused by the lattice constant mismatch between the gallium nitride compound semiconductor and the sapphire substrate, chipping, etc. can be prevented, and gallium nitride compound semiconductor chips can be manufactured with high yield.
Its industrial utility value is great.
【図１】 本発明の一実施例の工程において得られる窒
化ガリウム系化合物半導体ウエハーの構造を示す断面
図。FIG. 1 is a cross-sectional view showing the structure of a gallium nitride-based compound semiconductor wafer obtained in the process of one embodiment of the present invention.
【図２】 本発明の一実施例の工程において得られる窒
化ガリウム系化合物半導体ウエハーの構造を示す断面
図。FIG. 2 is a sectional view showing the structure of a gallium nitride-based compound semiconductor wafer obtained in the process of one embodiment of the present invention.
【図３】 本発明の一実施例の工程において得られる窒
化ガリウム系化合物半導体ウエハーの構造を示す断面
図。FIG. 3 is a cross-sectional view showing the structure of a gallium nitride-based compound semiconductor wafer obtained in the process of one example of the present invention.
【図４】 本発明の一実施例の工程において得られる窒
化ガリウム系化合物半導体ウエハーの構造を示す断面
図。FIG. 4 is a cross-sectional view showing the structure of a gallium nitride-based compound semiconductor wafer obtained in the process of one example of the present invention.
【図５】 本発明の一実施例の工程において得られる窒
化ガリウム系化合物半導体ウエハーの構造を示す断面
図。FIG. 5 is a sectional view showing the structure of a gallium nitride-based compound semiconductor wafer obtained in the process of one example of the present invention.
【図６】 本発明の一実施例の工程において得られる窒
化ガリウム系化合物半導体チップの構造を示す断面図。FIG. 6 is a sectional view showing the structure of a gallium nitride-based compound semiconductor chip obtained in the process of one example of the present invention.
１・・・・・・サファイア基板 ２・・・・・・ｎ型窒化ガリウム系化合物半導体層 ３・・・・・・ｐ型窒化ガリウム系化合物半導体層 ４・・・・・・保護膜 ５・・・・・・スクライブライン ６・・・・・・電極 1 --- Sapphire substrate 2--n-type gallium nitride-based compound semiconductor layer 3--p-type gallium nitride-based compound semiconductor layer 4--protective film 5-・ ・ ・ ・ ・ Scribe line 6 ・ ・ ・ Electrode
Claims (1)
化ガリウム系化合物半導体が順に積層されたウエハーを
チップ状に分離する方法であって、 サファイア基板を研磨して薄くする工程と、 ｐ型層の一部をｎ型層までエッチングする工程と、 ｎ型層をサファイア基板までエッチング、またはダイシ
ングする工程と、 サファイア基板をダイシング、またはスクライビングに
より切断する工程と、を具備することを特徴とする窒化
ガリウム系化合物半導体チップの製造方法。1. A method of separating a wafer in which n-type and p-type gallium nitride-based compound semiconductors are sequentially stacked on a sapphire substrate into chips, the method comprising polishing a sapphire substrate to make it thin, and p-type A step of etching a part of the layer to the n-type layer; a step of etching or dicing the n-type layer to the sapphire substrate; and a step of cutting the sapphire substrate by dicing or scribing. Method of manufacturing gallium nitride compound semiconductor chip.
Priority Applications (2)
| Application Number | Priority Date | Filing Date | Title |
|---|---|---|---|
| JP17204292A JP2914014B2 (en) | 1992-06-05 | 1992-06-05 | Method of manufacturing gallium nitride based compound semiconductor chip |
| JP27938698A JP3679626B2 (en) | 1992-06-05 | 1998-09-14 | Gallium nitride compound semiconductor chip |
Applications Claiming Priority (1)
| Application Number | Priority Date | Filing Date | Title |
|---|---|---|---|
| JP17204292A JP2914014B2 (en) | 1992-06-05 | 1992-06-05 | Method of manufacturing gallium nitride based compound semiconductor chip |
Related Child Applications (1)
| Application Number | Title | Priority Date | Filing Date |
|---|---|---|---|
| JP27938698A Division JP3679626B2 (en) | 1992-06-05 | 1998-09-14 | Gallium nitride compound semiconductor chip |
Publications (2)
| Publication Number | Publication Date |
|---|---|
| JPH05343742A true JPH05343742A (en) | 1993-12-24 |
| JP2914014B2 JP2914014B2 (en) | 1999-06-28 |
Family
ID=15934458
Family Applications (1)
| Application Number | Title | Priority Date | Filing Date |
|---|---|---|---|
| JP17204292A Expired - Fee Related JP2914014B2 (en) | 1992-06-05 | 1992-06-05 | Method of manufacturing gallium nitride based compound semiconductor chip |
Country Status (1)
| Country | Link |
|---|---|
| JP (1) | JP2914014B2 (en) |
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|---|---|---|---|---|
| US5627109A (en) * | 1994-09-16 | 1997-05-06 | Sassa; Michinari | Method of manufacturing a semiconductor device that uses a sapphire substrate |
| JPH09129924A (en) * | 1995-10-27 | 1997-05-16 | Toyoda Gosei Co Ltd | Iii group nitride semiconductor etching method and light emitting element manufacturing method |
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| US6033927A (en) * | 1996-09-20 | 2000-03-07 | Toyoda Gosei Co., Ltd. | Method for separating a substrate of a group III nitride semiconductor light-emitting device |
| JP2002151740A (en) * | 2000-11-09 | 2002-05-24 | Seiwa Electric Mfg Co Ltd | Gallium nitride compound semiconductor device and its manufacturing method |
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| US7121925B2 (en) | 2000-03-31 | 2006-10-17 | Toyoda Gosei Co., Ltd. | Method for dicing semiconductor wafer into chips |
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| US5627109A (en) * | 1994-09-16 | 1997-05-06 | Sassa; Michinari | Method of manufacturing a semiconductor device that uses a sapphire substrate |
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| EP0926784A3 (en) * | 1997-12-27 | 2000-06-14 | Hewlett-Packard Company | Method of fabricating opto-electronic devices |
| US7121925B2 (en) | 2000-03-31 | 2006-10-17 | Toyoda Gosei Co., Ltd. | Method for dicing semiconductor wafer into chips |
| JP2002151740A (en) * | 2000-11-09 | 2002-05-24 | Seiwa Electric Mfg Co Ltd | Gallium nitride compound semiconductor device and its manufacturing method |
| US6940099B2 (en) | 2001-09-14 | 2005-09-06 | Sharp Kabushiki Kaisha | Semiconductor light emitting element and semiconductor light emitting device |
| JP2007511105A (en) * | 2003-11-12 | 2007-04-26 | クリー インコーポレイテッド | Method for processing the back side of a semiconductor wafer having a light emitting device (LED) thereon, and an LED formed by the method |
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| US7572657B2 (en) | 2004-08-20 | 2009-08-11 | Showa Denko K.K. | Method for fabrication of semiconductor light-emitting device and the device fabricated by the method |
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