CN102637640A - Method and system for minimizing edge defects of chips - Google Patents
Method and system for minimizing edge defects of chips Download PDFInfo
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- CN102637640A CN102637640A CN2011100394391A CN201110039439A CN102637640A CN 102637640 A CN102637640 A CN 102637640A CN 2011100394391 A CN2011100394391 A CN 2011100394391A CN 201110039439 A CN201110039439 A CN 201110039439A CN 102637640 A CN102637640 A CN 102637640A
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Abstract
Disclosed is a method for configuring adjacent chip edges of adjacent chips. The adjacent chips are positioned in a semiconductor chip array formed on a semiconductor substrate layer. Each chip consists of a circuit layer positioned on the substrate layer. Each circuit layer has a circuit layer thickness, and the substrate layer has a substrate layer thickness. The method includes etching along the adjacent chip edges to form trenches with the depths larger than the circuit layer thicknesses; and scribing through the substrate layer to form grooves which are scribing along the etched trenches in an aligned manner and partially contain the trenches.
Description
Technical field
The present invention relates generally to the semiconductor core chip arrays made, comprise image sensor array and " video camera on the sheet " imager chip array.
Background technology
Imageing sensor contains usually and has semiconductor chip photosensitive or optical detection device matrix or array, and this photosensitive or optical detection device can convert light into electric charge, curtage.The photosensitive region of a given chip has been represented the picture catching zone, also can be called imaging region.These chips can be manufactured on a slice semiconductor wafer with array format simultaneously.After making completion, handle through scribing, for example in the ground scribing of adjacent chips room machine, chip independent in the chip array can be separated into independently unit, and the chip separating treatment that is otherwise known as is handled in this scribing.
In existing imaging array chip, between adjacent chips, mark groove through adopting mechanical sawing or laser processing, the independent chip separation that is achieved in the chip array.When for example using the machine saw butt formula separating chips of spark saw; Ubiquitous adverse effect is; Can form fragment and the mechanical deformation that causes by the cutting of chip material at chip edge, and then cause along the mechanical stress of the chip edge accumulation of line of cut.When adopting the laser scribing separating chips, high-intensity laser beam can form thermal stress in the chip edge material, and this thermal stress can be accumulated at local edge equally.For each chip in the chip array, no matter said stress originates from mechanical stress or thermal stress, and all can on the chip periphery edge of approaching line, accumulate also residual be residual stress.
At said chip is under the situation of a multi-chip image sensor part; This multi-chip image sensor be otherwise known as " mosaic array (mosaic array) "; The physical edge of each identical chips can be near the photosensitive region of this individual chips; Because can making, the residual stress of said accumulation has higher " dark signal " generation rate or dark current, the operate as normal of the residual stress meeting interfering picture transducer of said accumulation near light-sensitive element (pixel) position of ruling.Therefore, although chip edge is said the photosensitive region that still is positioned at imager chip technically, compared to other zones of imager chip, that said chip edge possibly show is unpredictably different, or higher dark signal generation rate.Therefore photoelectric characteristic becomes inconsistent at chip edge, and in imaging system, produces ill effect.
Therefore, a solution is to adopt bigger street through the distance that increases between adjacent chips, thus between the photosensitive imaging edge of chip and separating cut or line the bigger marginal gap of permission.Yet, be the size that realizes given function or use required chip array owing to correspondingly increased, and the cost that thereupon produces increase, this can cause the other result who does not expect.
More specifically in the example, contain the charge-coupled device (CCD) image-forming component that is useful on focal-plane imaging array at another, this focal-plane imaging array is used for astronomy, medical digital X-ray, and other application.In this example, possibly require to have minimum " dead band ", perhaps adjacent segment, the distance in the array that promptly forms images between the photosensitive region of any two adjacent chips.Another requirement possibly be that the imaging region aforementioned dark signal generation rate everywhere of given chip is minimum, and more broadly, guarantees that whole imaging regions of CCD imager chip have consistent dark signal generation rate and other photoelectric characteristics.
For addressing the above problem; A kind of material fragment and the distortion that can in the chip separation process of chip array, avoid chip edge need be provided; And avoid or minimize at least the machinery of generation and/or the technology of thermal stress; Form the imaging region of that strengthen, the consistent chip edge that includes imager chip thus, make " dead band " or the adjacent spaces of adjacent chips minimize simultaneously.
Summary of the invention
According to one embodiment of present invention, a kind of method that disposes the chip by chip limit of adjacent chips is provided, this adjacent chips is arranged in the semiconductor core chip arrays that is formed on the semiconductor substrate layer.Each chip in the said chip array contains the circuit layer that is positioned on the said substrate layer.Said circuit layer has circuit layer thickness, and said substrate layer has substrate layer thickness.Said method comprises: the etching raceway groove is to the degree of depth that surpasses circuit layer thickness along the chip by chip limit, and draws groove to the degree of depth that penetrates substrate layer thickness, and this groove is aimed at ground along the etching raceway groove and drawn and carve, and partly comprises said raceway groove.
In one embodiment, said semiconductor core chip arrays contains the imager chip array.
In another embodiment, the imager chip in the said imager chip array comprises the ccd image sensor array.
In another embodiment, the imager chip in the said imager chip array comprises the cmos image sensor array.
In the embodiment of another variation, said semiconductor core chip arrays comprises the element of selecting in the element group that is made up of memory, processor, micromechanical component and optical element.
Said etch step can comprise chemical etching.
Carve step for said stroke and can comprise drawing quarter through the mechanical type sawing.
In another embodiment, draw and carve step and comprise and draw groove so that the distance at 2 to 8 microns at the interval, chip by chip limit of groove and raceway groove.
A pair of adjacent chips also is provided; Be arranged in the semiconductor core chip arrays of imaging device; Said a pair of adjacent chips comprises first chip with first adjacent edge and second chip with second adjacent edge, and said first and second chip by chip limit is aimed in the adjacent position, and each chip that said adjacent chips is right has the circuit layer that is positioned on the substrate layer; Said circuit layer has circuit layer thickness, and said substrate layer has substrate layer thickness.Said adjacent chips is to comprising: first raceway groove separately and second raceway groove, and said first raceway groove and second raceway groove are etched into the degree of depth above circuit layer thickness, and this raceway groove is to overlap with separately the first adjacent chip limit and the second chip limit substantially; And separately first stroke of ditch cell wall and second stroke of ditch cell wall of adjacent setting; Wherein, First etching shoulder shape being formed with along separately the first chip limit and the second chip limit separately is residual residual with second etching shoulder shape, and said first and second etching shoulder shape is residual to be provided by first stroke of ditch cell wall and the transition of second stroke of ditch groove arm extremely separately of etching raceway groove.
In one embodiment, the adjacent chips of imaging device chip is to comprising the ccd image sensor array.
In another embodiment, the adjacent chips of imaging device chip is to comprising the cmos image sensor array.
Description of drawings
Only exemplarily present invention is described in conjunction with following accompanying drawing, wherein:
Fig. 1 is the cutaway view that the semiconductor core chip arrays of normally relevant with chip characteristic is shown;
Fig. 2 a shows, in an example, and the details on chip by chip limit after the etching operation of chip limit collocation method;
Fig. 2 b shows, in an example, in the details of drawing the chip by chip limit of carving operation back Fig. 2 a;
Fig. 3 is the flow chart that shows the sequence of operations among the embodiment of chip edge collocation method;
Fig. 4 a and 4b show an example through adopting chip described here limit configuring technical obtainable " dark signal " production rate to reduce.
Embodiment
Be meant to have according to providing at this and the chip on the chip limit of the technical configuration described at this employed noun " adjacent chips ", no matter and whether actual arrangement is adjacent with another chip limit on said chip limit.For example, the chip limit can be arranged to adjacent, but possibly when actual arrangement, not be set at yet adjacent, for example in having single-row imager chip array.In the layout of for example single-row chip array; Although chip limit not actual arrangement is adjacent with another chip limit; The chip limit is configured to adjacent edge can minimizes bad chip side effect, this bad chip side effect maybe with the there residual stress relevant (as aforementioned).
Fig. 1 is the cutaway view that the semiconductor core chip arrays of normally relevant with chip characteristic is shown.
Be formed with semiconductor core chip arrays 101 on the semiconductor substrate layer 102, this semiconductor substrate layer 102 body silicon layer 102 that is otherwise known as with a pair of adjacent chips 103 and 105.In the adjacent position, chip 103 has limit 104, and chip 105 has limit 106.Epitaxial loayer or circuit layer 108 are uniformly distributed in whole semiconductor wafer, and said semiconductor wafer has wafer top surface 110.The functional circuit of the individual chips of chip 103,105 for example is formed at the end face 110 of epitaxial loayer 108.Epitaxial loayer 108 is depicted as has epitaxy layer thickness 109, and substrate layer 102 has substrate layer thickness 111.In the chip separation process of prior art, chip 103 can separate along drawing cutting 107 through mechanical sawing or laser cutting with 105.
Semiconductor core chip arrays 101 can be the imager chip array, for example ccd image sensor array or complementary metal oxide semiconductors (CMOS) (CMOS) sensor array.For imaging device described here field; It should be appreciated by those skilled in the art that the technology here and embodiment also can be applicable to other field and device (includes but not limited to memory (SRAM, DRAM; Flash memory); Processor, micromechanical component and optical element), semiconductor chip edge effect that do not expect or bad maybe be relevant with mechanical stress or caused by mechanical stress in these fields or the device.
Fig. 2 a shows the chip 103 after the etching operation of chip by chip limit collocation method.
Raceway groove 201 is etched to the degree of depth 203 above epitaxy layer thickness 109.Perpendicular to wafer surface 110, and said sidewall 204 is positioned as close to the limit of chip 103 to the sidewall 204 of the raceway groove 201 that etching forms in rational accuracy rating.In one embodiment, raceway groove 201 is etched to such an extent that overlap with chip limit 104 substantially, makes sidewall 204 and chip limit 104 0 to 2 micron distance at interval.
The raceway groove 201 that etching forms can be etched to the degree of depth that significantly surpasses epitaxial loayer 108 thickness.Body silicon layer or substrate layer 102 have extremely low minority carrier lifetime, even therefore have mechanical stress, it does not cause the generation dark signal yet.
Fig. 2 b shows the chip 103 after carving operation of drawing at chip limit collocation method, and said stroke is carved operation is what after the etching operation shown in the earlier figures 2a, to carry out.
Consider adopted specific stroke operational tolerance of carving operation, for example mechanical sawing or similar techniques are drawn cutting or are drawn quarter road 206 and can be drawn and be carved into most actual capabilities ground near raceway groove end 204.In one embodiment, groove 206 can draw be carved to the raceway groove end of etching raceway groove 201 at interval 204 about 2 to 8 microns.
Groove 206 is drawn to carve penetrates substrate layer thickness 111.Apparently, groove 206 is aimed at along etching raceway groove 201 substantially, and partially overlaps this etching raceway groove 201.Aiming at substantially among this paper is meant in the scope of positive and negative 5 degree and aims at abreast.Profile according to Fig. 2 b finds out that more apparently through partly being overlapped in raceway groove 201, groove 206 partly comprises etching raceway groove 201.
Be positioned at outside the image sensitizing range of adjacent edge 104 of chip 103 owing to draw ditch groove 206, the signal quality that ditch groove 206 to semiconductor substrate layer 102 can't damage imager chip is drawn in cutting.
The characteristic of chip by chip described here limit collocation method is obvious from Fig. 2 b, and it is residual 205 wherein to be formed with the etching shoulder shape of etching raceway groove 201, and this etching shoulder shape residual 205 shows by etching raceway groove 201 to the physics transition of carving sidewall 207 of drawing of drawing ditch groove 206.
Fig. 3 shows the flow chart of an embodiment of the sequence of operations step of chip by chip limit collocation method 300.Said method comprises that in step 301, etching raceway groove 201 is to the degree of depth 203 that surpasses epitaxy layer thickness 108.Etching raceway groove 201 parallels with wafer surface 110 substantially and is approaching perpendicular to sidewall 104.Etch step 301 adopts the traditional chemical etching usually, and for example plasma etching carries out.
Then, in step 302, groove 206 is drawn the degree of depth of carving to the thickness that is deeper than etching raceway groove 201 203, to substrate layer thickness 111.Groove 206 drawn be carved into substantially in alignment with and partly comprise etching raceway groove 201.Can adopt spark saw or similar techniques mechanically to carry out drawing in this step and carve operation.
Fig. 4 a and 4b show an example through adopting chip limit configuring technical obtainable usually " dark signal " production rate to reduce.Fig. 4 a, the longitudinal axis 401 among the 4b show the sensor signal that numeral is read under the different light intensity level.Fig. 4 a, the transverse axis 402 among the 4b shows along the variation of the row of chip pixel array.Fig. 4 a is a measured curve on the chip that separates through the existing machinery scribing mode that adopts the spark saw, and Fig. 4 b is through measured curve on the chip of etching described here-draw carving method 300 configurations.
Contrasting this two pictures can find out, chip by chip described here limit collocation method greatly reduces from the dark signal peak value 403 near the sensor column 404 of score path.
Apparently, chip by chip described here limit collocation method makes it possible to make big imaging area sensor array, and this array does not have; Perhaps only there is antipode low; The dark current peak value relevant with the peripheral edge pixel of imager chip, thereby avoided the potential sensing data loss relevant with the dark current peak value, in addition; Also minimize " dead band " or adjacent spaces in the aforesaid chip mosaic array, made adjacent chip more closely to arrange.
It should be noted that chip by chip described here limit collocation method can also be applied to other semiconductor core chip arrays except that the imager chip array.Though the preferred embodiments of the present invention are that example is described with the imager chip array; But it should be understood that and in fact also can be understood, can be applied to the semiconductor core chip arrays of other types in the scheme of this proposition by those skilled in the art; For example comprise manufacturing device and element on it; These devices and element are such as but not limited to the combination in any of memory component (SRAM, DRAM, flash memory), processor device, micromechanical component and optical element.Correspondingly, one of ordinary skill in the art will appreciate that specific embodiment described here is exemplary and need not to be comprehensively, and can under the situation of the spirit and scope of the present invention that do not deviate from claim and limited, can make various changes.
Claims (12)
1. method that disposes the chip by chip limit of adjacent chips; Said adjacent chips is arranged in the semiconductor core chip arrays that is formed on the semiconductor substrate layer; Each chip in the said chip array comprises the circuit layer that is arranged on the said substrate layer; Said circuit layer has circuit layer thickness, and said substrate layer has substrate layer thickness, and said method comprises:
The etching raceway groove is to the degree of depth that surpasses said circuit layer thickness along the chip by chip limit; And
Draw groove to the degree of depth that penetrates said substrate layer thickness, said groove is drawn along said etching raceway groove with aiming at and is carved, and partly comprises said raceway groove.
2. method according to claim 1, wherein said semiconductor core chip arrays comprises the imager chip array.
3. method according to claim 2, the imager chip in the wherein said imager chip array comprises the ccd image sensor array.
4. method according to claim 2, the imager chip in the wherein said imager chip array comprises the cmos image sensor array.
5. method according to claim 1, wherein said semiconductor core chip arrays comprises the element of selecting in the element group of being made up of memory, processor, micromechanical component and optical element.
6. method according to claim 1, wherein said etching comprises chemical etching.
7. method according to claim 1, comprise through drawing of mechanical type sawing wherein said stroke of quarter carves.
8. method according to claim 1 comprises and draw carving so that the distance at 2 to 8 microns at the interval, said chip by chip limit of said groove and said raceway groove.
9. a pair of adjacent chips; Be arranged in the semiconductor core chip arrays of imaging device, said a pair of adjacent chips comprises first chip with first adjacent edge and second chip with second adjacent edge, and said first and second chip by chip limit is adjacent to be aimed at; Each chip of said a pair of adjacent chips has the circuit layer that is positioned on the substrate layer; Said circuit layer has circuit layer thickness, and said substrate layer has substrate layer thickness, and said a pair of adjacent chips comprises:
First and second raceway groove separately, said first and second raceway groove are etched to the degree of depth that surpasses said circuit layer thickness, and said raceway groove is to overlap with separately said first adjacent edge and said second adjacent edge substantially; And
Separately first and second stroke ditch cell wall, said first and second stroke ditch cell wall are adjacent to be provided with;
Wherein, first and second etching shoulder shape that said first and second adjacent edge separately is formed with separately on the edge is residual, the residual transition that provides by said etching raceway groove said first and second stroke ditch cell wall extremely separately of said first and second etching shoulder shape.
10. a pair of adjacent chips according to claim 9, the chip of wherein said imaging device comprises the ccd image sensor array.
11. a pair of adjacent chips according to claim 9, the chip of wherein said imaging device comprises the cmos image sensor array.
12. a pair of adjacent chips according to claim 9, wherein said adjacent chips is to comprising the element of selecting in the element group of being made up of memory, processor, micromechanical component and optical element.
Priority Applications (1)
| Application Number | Priority Date | Filing Date | Title |
|---|---|---|---|
| CN2011100394391A CN102637640A (en) | 2011-02-09 | 2011-02-09 | Method and system for minimizing edge defects of chips |
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| Application Number | Priority Date | Filing Date | Title |
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| CN2011100394391A CN102637640A (en) | 2011-02-09 | 2011-02-09 | Method and system for minimizing edge defects of chips |
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| CN102637640A true CN102637640A (en) | 2012-08-15 |
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| CN2011100394391A Pending CN102637640A (en) | 2011-02-09 | 2011-02-09 | Method and system for minimizing edge defects of chips |
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Cited By (1)
| Publication number | Priority date | Publication date | Assignee | Title |
|---|---|---|---|---|
| CN109449120A (en) * | 2018-09-29 | 2019-03-08 | 中国电子科技集团公司第十研究所 | A method of optimization scribing quality |
Citations (3)
| Publication number | Priority date | Publication date | Assignee | Title |
|---|---|---|---|---|
| US5219796A (en) * | 1991-11-04 | 1993-06-15 | Xerox Corporation | Method of fabricating image sensor dies and the like for use in assembling arrays |
| JPH05343742A (en) * | 1992-06-05 | 1993-12-24 | Nichia Chem Ind Ltd | Manufacture of gallium nitride series compound semiconductor chip |
| JPH06268060A (en) * | 1993-03-10 | 1994-09-22 | Toshiba Corp | Manufacture of semiconductor device |
-
2011
- 2011-02-09 CN CN2011100394391A patent/CN102637640A/en active Pending
Patent Citations (3)
| Publication number | Priority date | Publication date | Assignee | Title |
|---|---|---|---|---|
| US5219796A (en) * | 1991-11-04 | 1993-06-15 | Xerox Corporation | Method of fabricating image sensor dies and the like for use in assembling arrays |
| JPH05343742A (en) * | 1992-06-05 | 1993-12-24 | Nichia Chem Ind Ltd | Manufacture of gallium nitride series compound semiconductor chip |
| JPH06268060A (en) * | 1993-03-10 | 1994-09-22 | Toshiba Corp | Manufacture of semiconductor device |
Cited By (1)
| Publication number | Priority date | Publication date | Assignee | Title |
|---|---|---|---|---|
| CN109449120A (en) * | 2018-09-29 | 2019-03-08 | 中国电子科技集团公司第十研究所 | A method of optimization scribing quality |
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Application publication date: 20120815 |