JPH05343679A - Semiconductor device and manufacturing method thereof - Google Patents

Abstract

PURPOSE:To enhance the transistor characteristics by a method wherein the second conductivity type impurities are to be implanted in the substrate surface between element formation parts. CONSTITUTION:The impurities in the different conductivity type from that of the impurities implanted in a drain region 22 and a source region 24 are implanted in the substrate 10 surface existing between element formation parts. Accordingly, when an oblique ion implanting step is performed, the impurities are partly reflected on the sidewalls of protrusions 20 wherein the impurities are ion-implanted so that a parasitic MOS transistor may not be formed on the substrate 10 surface existing between the protrusions 20 even if the partly reflected impurities are implanted in the substrate 10 surface existing between the protrusions 20. Through these procedures, the excellent transistor characteristics can be displayed when the miniaturized semiconductor device is to be manufactured.

Description

Detailed Description of the Invention

[0001]

BACKGROUND OF THE INVENTION The present invention relates to a MOS on a semiconductor substrate.
The present invention relates to a semiconductor device which forms an element such as a transistor and a manufacturing method thereof.

[0002]

2. Description of the Related Art Conventionally, various types of semiconductor devices have been proposed, and in particular, those having a built-in MOS transistor are widely used. In such a semiconductor device, the element structure is being miniaturized in order to increase the degree of integration.

Here, in a typical semiconductor device, a plurality of M's are provided in a predetermined area of a flat semiconductor substrate (eg, Si substrate).
In many cases, OS transistors are formed. In this case, the gate region is covered with a gate electrode through a thin insulating layer, and regions on both sides of the gate region are doped with ions to form a source region and a drain region, and a MOS transistor is formed in a predetermined region of a semiconductor substrate. ing. When the MOS transistor of such a semiconductor device is miniaturized, various problems occur. That is, a short channel effect occurs such that the drain depletion layer extends near the potential barrier near the source and a punch through current occurs as the electric field near the drain increases, and the carrier energy increases as the electric field strength increases in the channel. A hot carrier effect is generated in which electron-hole pairs are generated due to collision ionization, the electric field in the vertical direction of the channel is increased, and the carrier mobility is reduced, and element isolation from an adjacent element cannot be performed sufficiently. Problems such as occur. Therefore, the conventional semiconductor device has a problem that sufficient performance and reliability cannot be maintained if the gate length is set to submicron or less.

On the other hand, as to improve these problems, SOI (S ilicon O n I nsulato
r) Ultra thin film transistors have been proposed. This SOI
The ultra-thin film transistor is formed by forming an oxide insulating film on a semiconductor substrate, and forming source, gate, and drain regions on the oxide insulating film. According to this super thin film transistor, since the transistor is formed on the insulating film, the occurrence of short channel effect and hot carrier effect can be suppressed, and since a voltage can be applied to the entire channel, the electric field in the vertical direction is reduced to reduce carrier mobility. It is possible to maintain a large value, and further, it is possible to obtain an effect that the element isolation property is excellent.

However, because of the structure of this ultra-thin film transistor, it is necessary to form a Si substrate for forming the transistor on an insulating film. However, it is technically very difficult to form a Si single crystal layer on an insulating film (eg, SiO ₂ ). In particular, it is impossible at present to form a high-quality Si epitaxial film, and it has been difficult to manufacture an ultrathin film transistor having suitable performance.

On the other hand, as a semiconductor device capable of obtaining an effect similar to that of a super thin film transistor, a vertical type super thin film transistor in which an extremely thin protrusion is provided on a Si substrate and a source, channel and drain regions are provided in the protrusion has been proposed. .. And in this vertical type super thin film transistor,
A protrusion is formed on the Si substrate by anisotropic etching,
After that, the protruding portion is field-oxidized in a state of being covered with silicon nitride, and the Si substrate and the protruding portion are separated by a field oxide layer. As described above, since a part of the substrate is used as the protruding portion, the protruding portion can be formed as a Si single crystal, and an SOI super thin film transistor can be realized. Further, since the transistors are formed in the protrusions, there is an effect that the integration rate can be further increased. Note that such a device is disclosed in, for example, Japanese Patent Application Laid-Open No. 2-263473.

[0007]

However, in the above-described vertical type super thin film transistor, as described above, the protrusion is covered with the oxidation resistant film (for example, Si ₃ N ₄ ),
It is necessary to form a field oxide layer down to the lower part of the projecting portion by the step of performing field oxidation to perform insulation separation between the channel portion and the substrate. Therefore, in this field oxidation step, the crystallinity in the channel portion may be impaired, and there is a problem that the performance of the transistor cannot be made sufficient.

In this vertical type super thin film transistor, the channel portion is completely separated from other portions by the field oxide film. Therefore, when impact ionization occurs in the channel portion, surplus carriers of the same polarity are accumulated here, and there is a problem that the potential shifts and various problems occur.

Further, since the field oxide layer has a low thermal conductivity, there is a problem that heat cannot be sufficiently dissipated in the channel portion. In addition, since the oxide layer obtained by field oxidation has different properties from the gate oxide film,
There is a problem that the residual stress here becomes large.

Therefore, the inventors of the present application have proposed the semiconductor device and the manufacturing method thereof described in Japanese Patent Application No. 4-17176 and Japanese Patent Application No. 4-17177 shown below. In the semiconductor device, a protrusion is formed on a substrate by anisotropic etching, and a transistor is built in the protrusion. That is, the central portion of the protrusion covered with the gate electrode is used as a channel region, and both sides thereof are used as a drain region and a source region. Then, in the manufacturing method, when forming the drain region and the source region, impurities are implanted by oblique ion implantation using the gate electrode as a mask, and the composition of the substrate remains under the drain region, the source region, and the channel region. The element isolation portion is formed.

Therefore, an oxide insulator layer is not required below the transistor, which not only facilitates manufacturing, but also
Carriers generated in the channel region by impact ionization can escape to the substrate.

However, in such a semiconductor device, when the drain region and the source region are formed by performing oblique ion implantation using the gate electrode as a mask, impurities are partially reflected by the side wall of the projecting portion to be ion-implanted. May be done. And in this case,
The partially reflected impurities are injected near the substrate surface existing between the protrusions. When such ion implantation is performed, there is a problem that element isolation between the element formed on the protrusion and the element in the adjacent protrusion is not sufficient.

Further, since ion implantation is performed on the surface of the substrate existing between the protrusions, if a gate electrode is present there, a parasitic MOS transistor is generated there, and good transistor characteristics cannot be obtained. It was

The present invention has been made to solve the above problems, and a semiconductor device and a semiconductor device thereof which can obtain good transistor characteristics when manufacturing a miniaturized semiconductor device. It is intended to provide a manufacturing method.

[0015]

According to another aspect of the present invention, there is provided a semiconductor device having a plate-shaped semiconductor substrate portion, a plurality of element forming portions formed on the semiconductor substrate portion so as to project therefrom, and the element forming portion. An element operating region in which an impurity of the first conductivity type is implanted, and an element isolation part having a same composition as the semiconductor substrate part, which is provided below the element operating region in the element forming part, An impurity of the second conductivity type is implanted in the vicinity of the substrate surface existing between the element formation portions.

According to a second aspect of the present invention, there is provided a method of manufacturing a semiconductor device, wherein a plurality of grooves are formed in a semiconductor substrate by anisotropic etching, a protruding portion forming step of forming a protruding portion, and a bottom portion of the formed groove. A first impurity introducing step of injecting an impurity of a second conductivity type different from an impurity of a first conductivity type injected into the device operation region formed in the protrusion, and a first impurity introducing step below the formed protrusion. And a second impurity introducing step of leaving an impurity non-injection region of the second conductivity type and injecting an impurity of the first conductivity type into an upper portion to form an impurity injection region to be an element operating region. Characterize.

[0017]

In the semiconductor device according to the present invention, since an impurity having a conductivity type different from the impurities injected into the drain region and the source region is injected in the vicinity of the substrate surface existing between the element formation portions, oblique ion injection is performed. As a result, when the drain region and the source region are formed, impurities are partially reflected by the sidewalls of the protrusions to be ion-implanted, and the partially reflected impurities are implanted near the substrate surface existing between the protrusions. Even if it is done, a parasitic MOS transistor does not occur near the surface of the substrate existing between the protruding portions.

In the method of manufacturing a semiconductor device according to the present invention, oblique ion implantation is performed to form a drain region,
Prior to the impurity introduction step of forming the source region, the impurities implanted in the drain region and the source region are formed in the vicinity of the substrate surface between the element formation portions, that is, in the plurality of grooves formed in the semiconductor substrate by anisotropic etching. Since an impurity of a different conductivity type is implanted, the impurity is partially reflected by the side wall of the protrusion to be ion-implanted, and the partially reflected impurity is implanted in the drain region or the like even if implanted in the groove. Since the impurity concentration of the conductivity type different from the impurity concentration is higher, the charge is neutralized and no parasitic MOS transistor is generated in that portion.

[0019]

DESCRIPTION OF THE PREFERRED EMBODIMENTS A semiconductor device according to the present invention will be described below with reference to the drawings.

FIG. 1 is a perspective view for explaining the structure of the semiconductor device manufactured as described above. In this figure, only one of the plurality of protrusions is shown. The protrusion 20 is formed on the p-type Si substrate 10. Then, on both sides of this protruding portion 20, n ⁺
-Type drain region 22 and n ⁺ -type source region 24 are formed, and in the region sandwiched by the drain region 22 and the source region 24, the same p-type channel region 26 as the substrate 10 is formed.
Are formed. Then, these drain regions 22,
The lower ends of the source region 24 and the channel region 26 are contained in the protruding portion 20, and the substrate 10 is provided below the protruding portion 20.
The element isolation portion 28, which is a part of

The surfaces of the substrate 10 and the protrusions 20 are all covered with an oxide film 30 made of SiO ₂ , and a gate electrode 32 is formed on the surface of the channel region 26. Therefore, this oxide film 30 functions as a gate oxide film. Further, the gate electrode 32 is routed to a predetermined end portion of the substrate 10 for electrical connection with the outside.

Further, in the vicinity of the surface of the substrate 10 existing between the protrusions 20, an opposite conductivity type impurity layer 18 into which impurities of the opposite conductivity type are implanted is formed. That is, when the drain region 22 and the source region 24 are n-channel, p
^The opposite conductivity type impurity layer 18 in which ⁺ type impurities, for example, boron (B) or the like, or when the drain region 22 and the source region 24 are used as p-channels is doped with n ⁺ type impurities, phosphorus (P), is projected. It is formed near the surface of the substrate 10 existing between the portions 20.

In such a semiconductor device, one MOS transistor is formed in the protruding portion 20. Therefore, if a drain electrode and a source electrode are connected to the drain region 22 and the source region 24, respectively, the potential of the channel region 26 is controlled by applying a voltage to the gate electrode 32 to control the current between the drain region 22 and the source region 24. Can be controlled. In this example, since the formed MOS transistor is an n-channel, a current flows by applying a positive voltage to the gate electrode.

Particularly, according to the apparatus of this embodiment, the protrusion 2
In the lower portion of 0, an element isolation portion 28 is formed, and the reverse conductivity is obtained by implanting an impurity of a conductivity type different from the impurities implanted in the drain region 22 and the source region 24 into the surface of the substrate 10 between the protrusions 20. Since the type impurity layer 18 is formed, element isolation from an adjacent element can be performed almost completely. The element isolation portion 28 is a part of the substrate 10. Therefore, surplus carriers (holes in the case of the present example) having the same polarity as the substrate generated by impact ionization are discharged to the substrate 10 and are not accumulated in the channel region 26. Therefore, the kink (Kin
k) The phenomenon does not occur, and the pseudo short channel effect due to excess holes does not occur. In addition, since the heat generated by the power consumption easily diffuses to the substrate 10, the channel region 2
6 can be prevented from being heated.

Further, since the transistor is of a vertical type and the channel region 26 is surrounded by the gate electrode 32, the voltage of the entire channel region can be controlled to a predetermined value, and the operating performance is extremely high. You can

A method of manufacturing a semiconductor device according to the present invention will be described with reference to the drawings.

A method of manufacturing the semiconductor device of this embodiment will be described with reference to FIG. First, a linear pattern having a line width of about 0.1 μm made of a SiO ₂ film (or a SiN film) is formed on the surface of the substrate 10 made of Si single crystal (S).
1). The formation of this linear pattern is performed by an ultrafine patterning technique using an electron (EB) beam drawing exposure device and a multilayer resist exposure technique. Then, using the SiO ₂ (or SiN) linear pattern as a mask, the substrate 10 is anisotropically etched by RIE or the like to form a predetermined recess 40 to form the protrusion 20 (S2). Next, without removing the SiO ₂ pattern, the entire surface of the substrate 10 is thermally oxidized to form the SiO ₂ oxide film 30 (S3). Next, an impurity of a conductivity type different from the impurities injected into the drain region and the source region at the bottom of the groove between the protrusions 20 (in this embodiment, for example, p ⁺ type impurity such as boron (B) is used as the groove). Then, the impurities are injected vertically to form an opposite conductivity type impurity layer 18 (S4), and a polysilicon layer Poly-Si is formed on the entire surface (S5).
After that, the gate electrode 32 is formed by a normal mask and etching process (S6). To form the gate electrode 32, a highly anisotropic and highly selective etching technique such as an ECR etching device or neutral radical beam etching is used.

In this way, when the formation of the protrusion 20 and the formation of the gate electrode 32 via the gate oxide film on this surface are completed, the drain region 2 is formed by ion implantation.
2. A source region 24 is formed (in this embodiment, for example, an n ⁺ region is formed by implanting phosphorus). Here, this ion implantation is performed by an oblique incidence ion implantation apparatus in which the irradiation direction of the impurities is limited to only the oblique direction by masking, voltage application, etc. (S7).

At this time, some of the impurities may be reflected by the side wall of the protruding portions 20 to be ion-implanted and may be injected into the bottom of the groove between the protruding portions 20. However, in the present embodiment, before the n ⁺ type ion implantation step, p is formed at the bottom of the groove.
^{A +} type opposite conductivity type impurity layer 18 is formed. Therefore, even if the n ⁺ type ions are reflected, the charges can be neutralized by the p ⁺ type opposite conductivity type impurity layer 18, an n channel is not formed at the bottom of the groove, and the parasitic MOS transistor is Does not happen. The n ⁺ -type impurity concentration reflected is
When thinner than the p ⁺ -type impurity concentration of the opposite conductivity type impurity layer 18, opposite conductivity type impurity layer 18 of p ⁺ -type after the substrate 10 terminates all processes but remain, and the impurity concentration of the n ⁺ -type reflected If the p ⁺ type reverse conductivity type impurity layer 18 having the same or higher concentration is formed, the reverse conductivity type impurity layer 18 does not remain in the manufactured semiconductor device, but the n channel is formed at the bottom of the groove. Is not formed and a parasitic MOS transistor does not occur.

Further, as shown in FIG. 3, the irradiation angle α of the impurities and the width w of the recess 40 are such that the relationship of tan α> w / h is maintained when the height of the protrusion 20 is h. decide. Therefore, the sidewall of the recess 40 functions as a mask,
The element isolation portion 28 having the same composition as that of the p substrate, in which impurities are not implanted, remains on the substrate side of the protrusion 20. In addition,
After the ion implantation step, there is a thermal diffusion step by heating, in which the drain region 22 and the source region 2 are
4 expands a little. Therefore, the size of the element isolation portion 28 is determined in consideration of this.

In this way, the element isolation portion 28 can form a MOS transistor element-isolated from the substrate 10 inside the protruding portion 20. In order to actually operate the MOS transistor, a source electrode, a drain electrode, an interlayer insulating layer, an Al wiring layer, a protective layer, etc. are required. These are formed by a general method and then formed. The semiconductor device is made operable by this.

According to the present embodiment, the element isolation portion 28 is formed by simply leaving the substrate 10 as it is. Therefore, unlike the SOI, it is not necessary to form an oxide layer for element isolation between the MOS transistor and the substrate 10, and the manufacturing process thereof can be simplified. Therefore, the protruding portion 20 can be formed of a high-quality Si single crystal, and since there are no harsh conditions such as a field oxidation step in which the volume and structure change significantly, the gate oxide film and the field oxide film are not formed. It is possible to prevent formation of a portion such as a contact point where large stress remains.

FIG. 4 is a constitutional view of another embodiment of the semiconductor device manufactured by the method of the present invention, in which a large number of protrusions 20 are arranged at predetermined intervals. According to the present embodiment, the effective channel width W can be made larger than the width Tch of the protruding portion 20, so that the effective channel width W per unit width Lsp.
(Area efficiency = W / Lsp) can be made very high. Particularly, in this example, both W and Lsp can be set to approximately 0.1 μm, and the degree of integration of the device can be dramatically increased.
In addition, in this example, one gate electrode 26 is common to the transistors of each protrusion 20.

[0034]

As described above, according to the semiconductor device of the present invention, an impurity of a conductivity type different from the impurities injected into the drain region and the source region is implanted in the vicinity of the substrate surface existing between the element formation portions. Therefore, when the drain region and the source region are formed by performing oblique ion implantation, the impurities are partially reflected by the sidewalls of the protrusions to be ion-implanted, and the partially reflected impurities are
Even if it is injected into the vicinity of the substrate surface existing between the protrusions, the vicinity of the substrate surface existing between the protrusions does not serve as a channel.

Further, since the transistors are vertical type, the degree of integration can be increased, and since the element isolation is performed by the element isolation portion having the same composition as the substrate, the manufacturing can be simplified.
Accumulation of carriers in the channel can be prevented.

On the other hand, in the method of manufacturing a semiconductor device according to the present invention, oblique ion implantation is performed to form a drain region,
Prior to the impurity introduction step of forming the source region, the impurities implanted in the drain region and the source region are formed in the vicinity of the substrate surface between the element formation portions, that is, in the plurality of grooves formed in the semiconductor substrate by anisotropic etching. Since impurities of a different conductivity type are implanted, the impurities are partially reflected by the side wall of the protrusion to be ion-implanted, and even if the partially reflected impurities are implanted in the groove, Since the concentration of the impurity of the conductivity type different from that of the injected impurity is higher, the charge is neutralized and the parasitic MOS
No transistor occurs.

[Brief description of drawings]

FIG. 1 is a perspective view showing a configuration of a semiconductor device.

FIG. 2 is an explanatory diagram of a manufacturing process of a semiconductor device.

FIG. 3 is an explanatory diagram of an oblique ion implantation process.

FIG. 4 is a perspective view showing the configuration of another embodiment of the apparatus.

[Explanation of symbols]

 10 Substrate 20 Projection 22 Drain Region 24 Source Region 26 Channel Region 30 Oxide Film 32 Gate Electrode 40 Recess

Claims (2)

[Claims] 1. A plate-shaped semiconductor substrate portion, a plurality of element formation portions formed to project on the semiconductor substrate portion, and an element provided in the element formation portion and doped with an impurity of a first conductivity type. An operation region and an element isolation portion having a same composition as the semiconductor substrate portion, which is provided below the element operation region in the element formation portion, and has a second conductive layer near a substrate surface existing between the element formation portions. A semiconductor device having a type impurity implanted therein. 2. A step of forming a plurality of grooves on a semiconductor substrate by anisotropic etching to form a protruding portion, and a step of forming a protruding portion on a bottom portion of the formed groove in an element operating region formed on the protruding portion. A first impurity introducing step of injecting a second conductivity type impurity different from the first conductivity type impurity to be injected, and first and second conductivity type impurity non-injection regions remaining under the formed protrusions; And a second impurity introducing step of implanting an impurity of the first conductivity type in the upper portion to form an impurity implanted region serving as an element operating region.