JPH05343609A - Semiconductor integrated circuit device - Google Patents

Semiconductor integrated circuit device

Info

Publication number
JPH05343609A
JPH05343609A JP4170188A JP17018892A JPH05343609A JP H05343609 A JPH05343609 A JP H05343609A JP 4170188 A JP4170188 A JP 4170188A JP 17018892 A JP17018892 A JP 17018892A JP H05343609 A JPH05343609 A JP H05343609A
Authority
JP
Japan
Prior art keywords
chip
integrated circuit
chips
semiconductor integrated
semiconductor
Prior art date
Legal status (The legal status is an assumption and is not a legal conclusion. Google has not performed a legal analysis and makes no representation as to the accuracy of the status listed.)
Pending
Application number
JP4170188A
Other languages
Japanese (ja)
Inventor
Tokujiro Watanabe
徳二郎 渡辺
Current Assignee (The listed assignees may be inaccurate. Google has not performed a legal analysis and makes no representation or warranty as to the accuracy of the list.)
NEC Corp
Original Assignee
NEC Corp
Priority date (The priority date is an assumption and is not a legal conclusion. Google has not performed a legal analysis and makes no representation as to the accuracy of the date listed.)
Filing date
Publication date
Application filed by NEC Corp filed Critical NEC Corp
Priority to JP4170188A priority Critical patent/JPH05343609A/en
Publication of JPH05343609A publication Critical patent/JPH05343609A/en
Pending legal-status Critical Current

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Classifications

    • H—ELECTRICITY
    • H01—ELECTRIC ELEMENTS
    • H01L—SEMICONDUCTOR DEVICES NOT COVERED BY CLASS H10
    • H01L2224/00—Indexing scheme for arrangements for connecting or disconnecting semiconductor or solid-state bodies and methods related thereto as covered by H01L24/00
    • H01L2224/01—Means for bonding being attached to, or being formed on, the surface to be connected, e.g. chip-to-package, die-attach, "first-level" interconnects; Manufacturing methods related thereto
    • H01L2224/02—Bonding areas; Manufacturing methods related thereto
    • H01L2224/04—Structure, shape, material or disposition of the bonding areas prior to the connecting process
    • H01L2224/05—Structure, shape, material or disposition of the bonding areas prior to the connecting process of an individual bonding area
    • H01L2224/0554—External layer
    • H01L2224/0555—Shape
    • H01L2224/05552—Shape in top view
    • H01L2224/05554—Shape in top view being square
    • H—ELECTRICITY
    • H01—ELECTRIC ELEMENTS
    • H01L—SEMICONDUCTOR DEVICES NOT COVERED BY CLASS H10
    • H01L2224/00—Indexing scheme for arrangements for connecting or disconnecting semiconductor or solid-state bodies and methods related thereto as covered by H01L24/00
    • H01L2224/01—Means for bonding being attached to, or being formed on, the surface to be connected, e.g. chip-to-package, die-attach, "first-level" interconnects; Manufacturing methods related thereto
    • H01L2224/26—Layer connectors, e.g. plate connectors, solder or adhesive layers; Manufacturing methods related thereto
    • H01L2224/31—Structure, shape, material or disposition of the layer connectors after the connecting process
    • H01L2224/32—Structure, shape, material or disposition of the layer connectors after the connecting process of an individual layer connector
    • H01L2224/321—Disposition
    • H01L2224/32135—Disposition the layer connector connecting between different semiconductor or solid-state bodies, i.e. chip-to-chip
    • H01L2224/32145—Disposition the layer connector connecting between different semiconductor or solid-state bodies, i.e. chip-to-chip the bodies being stacked
    • H—ELECTRICITY
    • H01—ELECTRIC ELEMENTS
    • H01L—SEMICONDUCTOR DEVICES NOT COVERED BY CLASS H10
    • H01L2224/00—Indexing scheme for arrangements for connecting or disconnecting semiconductor or solid-state bodies and methods related thereto as covered by H01L24/00
    • H01L2224/01—Means for bonding being attached to, or being formed on, the surface to be connected, e.g. chip-to-package, die-attach, "first-level" interconnects; Manufacturing methods related thereto
    • H01L2224/42—Wire connectors; Manufacturing methods related thereto
    • H01L2224/47—Structure, shape, material or disposition of the wire connectors after the connecting process
    • H01L2224/48—Structure, shape, material or disposition of the wire connectors after the connecting process of an individual wire connector
    • H01L2224/4805—Shape
    • H01L2224/4809—Loop shape
    • H01L2224/48091—Arched
    • H—ELECTRICITY
    • H01—ELECTRIC ELEMENTS
    • H01L—SEMICONDUCTOR DEVICES NOT COVERED BY CLASS H10
    • H01L2224/00—Indexing scheme for arrangements for connecting or disconnecting semiconductor or solid-state bodies and methods related thereto as covered by H01L24/00
    • H01L2224/01—Means for bonding being attached to, or being formed on, the surface to be connected, e.g. chip-to-package, die-attach, "first-level" interconnects; Manufacturing methods related thereto
    • H01L2224/42—Wire connectors; Manufacturing methods related thereto
    • H01L2224/47—Structure, shape, material or disposition of the wire connectors after the connecting process
    • H01L2224/48—Structure, shape, material or disposition of the wire connectors after the connecting process of an individual wire connector
    • H01L2224/481—Disposition
    • H01L2224/48135—Connecting between different semiconductor or solid-state bodies, i.e. chip-to-chip
    • H01L2224/48137—Connecting between different semiconductor or solid-state bodies, i.e. chip-to-chip the bodies being arranged next to each other, e.g. on a common substrate
    • H—ELECTRICITY
    • H01—ELECTRIC ELEMENTS
    • H01L—SEMICONDUCTOR DEVICES NOT COVERED BY CLASS H10
    • H01L2224/00—Indexing scheme for arrangements for connecting or disconnecting semiconductor or solid-state bodies and methods related thereto as covered by H01L24/00
    • H01L2224/01—Means for bonding being attached to, or being formed on, the surface to be connected, e.g. chip-to-package, die-attach, "first-level" interconnects; Manufacturing methods related thereto
    • H01L2224/42—Wire connectors; Manufacturing methods related thereto
    • H01L2224/47—Structure, shape, material or disposition of the wire connectors after the connecting process
    • H01L2224/48—Structure, shape, material or disposition of the wire connectors after the connecting process of an individual wire connector
    • H01L2224/481—Disposition
    • H01L2224/48135—Connecting between different semiconductor or solid-state bodies, i.e. chip-to-chip
    • H01L2224/48145—Connecting between different semiconductor or solid-state bodies, i.e. chip-to-chip the bodies being stacked
    • H—ELECTRICITY
    • H01—ELECTRIC ELEMENTS
    • H01L—SEMICONDUCTOR DEVICES NOT COVERED BY CLASS H10
    • H01L2224/00—Indexing scheme for arrangements for connecting or disconnecting semiconductor or solid-state bodies and methods related thereto as covered by H01L24/00
    • H01L2224/01—Means for bonding being attached to, or being formed on, the surface to be connected, e.g. chip-to-package, die-attach, "first-level" interconnects; Manufacturing methods related thereto
    • H01L2224/42—Wire connectors; Manufacturing methods related thereto
    • H01L2224/47—Structure, shape, material or disposition of the wire connectors after the connecting process
    • H01L2224/48—Structure, shape, material or disposition of the wire connectors after the connecting process of an individual wire connector
    • H01L2224/484—Connecting portions
    • H01L2224/48463—Connecting portions the connecting portion on the bonding area of the semiconductor or solid-state body being a ball bond
    • H01L2224/48465—Connecting portions the connecting portion on the bonding area of the semiconductor or solid-state body being a ball bond the other connecting portion not on the bonding area being a wedge bond, i.e. ball-to-wedge, regular stitch
    • H—ELECTRICITY
    • H01—ELECTRIC ELEMENTS
    • H01L—SEMICONDUCTOR DEVICES NOT COVERED BY CLASS H10
    • H01L2224/00—Indexing scheme for arrangements for connecting or disconnecting semiconductor or solid-state bodies and methods related thereto as covered by H01L24/00
    • H01L2224/01—Means for bonding being attached to, or being formed on, the surface to be connected, e.g. chip-to-package, die-attach, "first-level" interconnects; Manufacturing methods related thereto
    • H01L2224/42—Wire connectors; Manufacturing methods related thereto
    • H01L2224/47—Structure, shape, material or disposition of the wire connectors after the connecting process
    • H01L2224/49—Structure, shape, material or disposition of the wire connectors after the connecting process of a plurality of wire connectors
    • H01L2224/491—Disposition
    • H01L2224/4912—Layout
    • H01L2224/49175—Parallel arrangements

Landscapes

  • Semiconductor Integrated Circuits (AREA)

Abstract

PURPOSE:To eliminate restriction on signal transfer between two chips and restriction on bonding wires. CONSTITUTION:On one chip 3', another chip 4' is bonded. After the chip 3' is mounted on an island 5 of a lead frame, the chip 3' is connected with the chip 4', and the chips 3', 4' are connected with inner leads 7 of a lead frame, by using bonding wires 6.

Description

【発明の詳細な説明】Detailed Description of the Invention

【０００１】[0001]

【産業上の利用分野】本発明は、機能等が異なる二以上
の半導体チップを集積してなる半導体集積回路に関す
る。BACKGROUND OF THE INVENTION 1. Field of the Invention The present invention relates to a semiconductor integrated circuit in which two or more semiconductor chips having different functions are integrated.

【０００２】[0002]

【従来の技術】半導体集積回路装置の高集積化，高速
化，多機能化に伴い、ＬＳＩチップ面積の増加，ウェー
ハ製造工程数の増大、及びＬＳＩチップから端子を取り
出すピン数の増加が進んでいる。2. Description of the Related Art As semiconductor integrated circuit devices have become more highly integrated, faster, and more multifunctional, the area of LSI chips has increased, the number of wafer manufacturing processes has increased, and the number of pins for extracting terminals from LSI chips has increased. There is.

【０００３】たとえば、バイポーラトランジスタとＣＭ
ＯＳトランジスタとを同一基板上に形成したＢｉ−ＣＭ
ＯＳプロセスにおいて、高速動作が要求されるプリスケ
ーラ部あるいはアナログ部をバイポーラトランジスタで
構成し、論理回路部等をＣＭＯＳトランジスタで構成し
ている。For example, a bipolar transistor and a CM
Bi-CM with OS transistor formed on the same substrate
In the OS process, a prescaler portion or an analog portion, which is required to operate at high speed, is composed of bipolar transistors, and a logic circuit portion is composed of CMOS transistors.

【０００４】またＤＴＳ’Ｄｉｇｉｔａｌ Ｔｕｎｉｎ
ｇ Ｓｙｓｔｅｍ），マイコン，リモコン用のＬＳＩ
は、従来のマスクＲＯＭ（Ｒｅａｄ Ｏｎｌｙ Ｍｅｍ
ｏｒｙ）部をＥＰＲＯＭ（Ｅｒａｓａｂｌｅ Ｐｒｏｇ
ｒａｍｍａｂｌｅ ＲＯＭ）にすることでＲＯＭへのデ
ータ書込みがＬＳＩパッケージ上から電気的に行えるよ
うになった。DTS 'Digital Tunin
g System), microcomputer, LSI for remote control
Is a conventional mask ROM (Read Only Mem).
ory) part to EPROM (Erasable Program)
It has become possible to electrically write data to the ROM from the LSI package by using the RAM ROM.

【０００５】図３は、ＬＳＩチップ１の平面図であり、
チップ周辺には外部への端子を引きだすためのパッド電
極２，破線内が論理回路を構成するＣＭＯＳ部３，さら
に一点破線内が例えばバイポーラ部あるいはＥＰＲＯＭ
部４を表わしており、ＣＭＯＳ部３と、バイポーラ部あ
るいはＥＰＲＯＭ部４とが一体に集積されている。FIG. 3 is a plan view of the LSI chip 1.
A pad electrode 2 for drawing out a terminal to the outside of the periphery of the chip 2, a CMOS portion in the broken line constitutes a logic circuit 3, and a portion in a dashed line is, for example, a bipolar portion or an EPROM.
This represents the portion 4, in which the CMOS portion 3 and the bipolar portion or the EPROM portion 4 are integrated together.

【０００６】[0006]

【発明が解決しようとする課題】バイポーラトランジス
タとＣＭＯＳトランジスタが混在したＢｉ−ＣＭＯＳ，
ＥＰＲＯＭを内蔵した図３に示すＣＭＯＳＬＳＩチップ
は、集積化という意味で大きな利点を有しているが、通
常のＣＭＯＳプロセスに比べ、ウェーハ製造工数が大幅
に増加する、あるいは要求される種々の特性を単一プロ
セスから引き出すといった複雑さから、しばしばウェー
ハ上の歩留り（有効チップ数中の良品チップ数）が低下
することがある。Bi-CMOS in which bipolar transistors and CMOS transistors are mixed,
The CMOS LSI chip shown in FIG. 3 having the built-in EPROM has a great advantage in terms of integration, but the number of wafer manufacturing steps is significantly increased or various required characteristics are required as compared with a normal CMOS process. Due to the complexity of drawing from a single process, the yield on the wafer (the number of non-defective chips out of the number of effective chips) often decreases.

【０００７】そこで、一つの対策としてＣＭＯＳ部はＣ
ＭＯＳプロセスで１チップに納め、バイポーラ部あるい
はＥＰＲＯＭ部は、また別のプロセスで１チップに納め
るといった方法が採られている。それぞれ個別のプロセ
スから得られるチップの歩留りは比較的安定だからであ
る。Therefore, as one countermeasure, the CMOS portion is C
A method is adopted in which the MOS process is put into one chip and the bipolar part or the EPROM part is put into one chip by another process. This is because the yield of chips obtained from each individual process is relatively stable.

【０００８】図４は、上記のようにして得られた個別の
チップ、すなわちＣＭＯＳ部チップ３′、およびバイポ
ーラ部あるいはＥＰＲＯＭ部チップ４′を１つのパッケ
ージに搭載した平面図である。FIG. 4 is a plan view in which the individual chips obtained as described above, that is, the CMOS part chip 3'and the bipolar part or EPROM part chip 4'are mounted in one package.

【０００９】チップ３′およびチップ４′をリードフレ
ームのアイランド５上にマウントし、チップ３′とチッ
プ４′のパッド電極２，２′間をボンディングワイヤ６
で結線し、さらにチップ３′，４′のパッド電極２，
２′とリードフレームのインナーリード７との間をボン
ディングワイヤ６′で結線している。The chip 3'and the chip 4'are mounted on the island 5 of the lead frame, and the bonding wire 6 is provided between the pad electrodes 2 and 2'of the chip 3'and the chip 4 '.
And the pad electrodes 2 of the chips 3 ', 4'.
A bonding wire 6'is connected between 2'and the inner lead 7 of the lead frame.

【００１０】しかしながら、以上の結線方法では、チッ
プ３′とチップ４′とを結ぶ結線数に制約があり、チッ
プ間の信号の授受に制限が生じる。またチップとインナ
ーリード間の結線も部分的に長く、ワイヤ間ショートの
危険もあり、信頼性上問題がある。However, in the above wiring method, there is a limitation in the number of wirings that connect the chips 3'and 4 ', and there is a limitation in the transmission and reception of signals between the chips. Further, the connection between the chip and the inner lead is partly long, and there is a risk of short circuit between wires, which is a reliability problem.

【００１１】さらに、チップ間，チップとリード間を含
めた全体的な設計に制約が多く、多ピンに不向きであ
り、かつチップサイズが大きくなってしまうという欠点
がある。Further, there are many restrictions on the overall design including the space between chips and the space between chips and leads, which is unsuitable for a large number of pins and has a drawback that the chip size becomes large.

【００１２】本発明の目的は、信頼性が高く、かつ多ピ
ン化に対応した半導体集積回路装置を提供することにあ
る。An object of the present invention is to provide a semiconductor integrated circuit device which has high reliability and is compatible with a large number of pins.

【００１３】[0013]

【課題を解決するための手段】前記目的を達成するた
め、本発明に係る半導体集積回路装置は、機能等が異な
る二以上の半導体チップを上下に積層してなる半導体集
積回路であって、相対的に下層の半導体チップは、上層
の半導体チップの外周縁に沿うパッド電極を有し、該パ
ッド電極に上層の半導体チップのパッド電極を電気的に
接続したものである。To achieve the above object, a semiconductor integrated circuit device according to the present invention is a semiconductor integrated circuit in which two or more semiconductor chips having different functions and the like are vertically stacked, The lower semiconductor chip has a pad electrode along the outer peripheral edge of the upper semiconductor chip, and the pad electrode of the upper semiconductor chip is electrically connected to the pad electrode.

【００１４】また、本発明に係る半導体集積回路装置
は、機能等が異なる二以上の半導体チップを上下に積層
してなる半導体集積回路であって、相対的に上層と下層
の半導体チップは、金属バンプが形成されたパッド電極
を有しており、上層と下層の半導体チップは、金属バン
プ同士を接合して搭載されたものである。Further, the semiconductor integrated circuit device according to the present invention is a semiconductor integrated circuit in which two or more semiconductor chips having different functions and the like are vertically stacked, and the relatively upper and lower semiconductor chips are made of metal. It has pad electrodes on which bumps are formed, and the upper and lower semiconductor chips are mounted by bonding metal bumps to each other.

【００１５】[0015]

【作用】集積すべき二以上の半導体チップのうち、上層
の半導体チップを下層の半導体チップの表面に搭載し、
かつ、その半導体チップのパッド電極相互間を配線す
る。[Function] Of the two or more semiconductor chips to be integrated, the upper semiconductor chip is mounted on the surface of the lower semiconductor chip,
Moreover, wiring is provided between the pad electrodes of the semiconductor chip.

【００１６】これにより、チップ同士間の配線数の制約
を解消し、チップとインナーリード間の配線をも整理す
る。As a result, the restriction on the number of wires between the chips is eliminated, and the wires between the chips and the inner leads are also organized.

【００１７】[0017]

【実施例】次に本発明について図面を参照して説明す
る。The present invention will be described below with reference to the drawings.

【００１８】（実施例１）図１（ａ）は、本発明の実施
例１に係る半導体集積回路装置を示す平面図、（ｂ）
は、同断面図である。(Embodiment 1) FIG. 1A is a plan view showing a semiconductor integrated circuit device according to Embodiment 1 of the present invention, and FIG.
FIG. 4 is a sectional view of the same.

【００１９】図において、ＣＭＯＳ部チップ３′は、表
面保護膜が例えばプラズマ窒化膜０．１〜１．０μｍ、
およびポリイミド膜２〜１０μｍの厚さで覆われてお
り、所定のパッド電極２上の表面保護膜は開口されてい
る。In the figure, the surface protection film of the CMOS chip 3'is, for example, a plasma nitride film of 0.1 to 1.0 .mu.m,
The polyimide film 2 is covered with a thickness of 2 to 10 μm, and the surface protection film on the predetermined pad electrode 2 is opened.

【００２０】バイポーラ部あるいはＥＰＲＯＭ部チップ
４′は、表面保護膜が例えば低濃度ＰＳＧ膜０．１〜
１．０μｍおよびプラズマ窒化膜０．１〜０．５μｍの
厚さで覆われており、パッド電極２′上は開口されてい
る。The bipolar portion or EPROM portion chip 4'has a surface protective film of, for example, a low-concentration PSG film 0.1 to 0.1.
It is covered with a thickness of 1.0 μm and a plasma nitride film of 0.1 to 0.5 μm, and has an opening on the pad electrode 2 ′.

【００２１】チップ４′の裏面にたとえばエポキシ樹脂
を塗り、チップ３′の表面に接着する。次にチップ３′
をリードフレームのアイランド５上にマウントさせる。An epoxy resin, for example, is applied to the back surface of the chip 4'and adhered to the front surface of the chip 3 '. Then tip 3 '
Are mounted on the island 5 of the lead frame.

【００２２】次にチップ４′のパッド電極２′とチップ
４′の外周縁に沿うチップ３′のパッド電極２との間を
ポンディングワイヤ６′で結線し、さらにチップ３′の
外周縁に沿うパッド電極２とリードフレームのインナー
リード７との間をボンディングワイヤ６で結線する。最
後にモールド樹脂で封入を行い、組立工数が完了する。Next, a padding wire 6'is connected between the pad electrode 2'of the chip 4'and the pad electrode 2 of the chip 3'along the outer peripheral edge of the chip 4 ', and further on the outer peripheral edge of the chip 3'. A bonding wire 6 connects between the pad electrode 2 and the inner lead 7 of the lead frame. Finally, it is sealed with mold resin, and the assembly man-hour is completed.

【００２３】（実施例２）図２（ａ）は、本発明の実施
例２に係る半導体集積回路装置を示す平面図、（ｂ）は
同断面図である。(Second Embodiment) FIG. 2A is a plan view showing a semiconductor integrated circuit device according to a second embodiment of the present invention, and FIG.

【００２４】ＣＭＯＳ部チップ３′、およびバイポーラ
部あるいはＥＰＲＯＭ部チップ４′のパッド電極２，
２′上に、金属バンプとして例えばＡｕバンプ８を形成
し、チップ３′の表面上にチップ４′の表面を向合わ
せ、互いのバンプ８，８同士を熱圧着等で接続する。次
にチップ３′の周辺バンプ８にＴＡＢのインナーリード
７を合わせて接続し、封止樹脂にてチップとＴＡＢ（Ｔ
ａｐｅ Ａｕｔｏｍａｔｅｄ Ｂｏｎｄｉｎｇ）を固定
して組立工程が完了する。Pads 2 of the CMOS chip 3'and the bipolar or EPROM chip 4 '
For example, Au bumps 8 are formed as metal bumps on 2 ′, the surface of the chip 4 ′ is faced to the surface of the chip 3 ′, and the bumps 8 and 8 are connected by thermocompression bonding or the like. Then, the inner leads 7 of the TAB are aligned and connected to the peripheral bumps 8 of the chip 3 ', and the chip and the TAB (T
Ape Automated Bonding) is fixed and the assembly process is completed.

【００２５】実施例においては、ＣＭＯＳチップとバイ
ポーラチップあるいはＥＰＲＯＭチップの例について説
明したが、製造方法あるいは製造工程数の異なる半導体
集積回路装置例えばＥ2ＰＲＯＭ，ＧａＡｓ、その他の
能動素子に適用できることは言うまでもない。[0025] In the embodiment, an example has been described of the CMOS chip and bipolar chip or EPROM chip, the manufacturing method or manufacturing process a different number of semiconductor integrated circuit devices, such as E 2 PROM, GaAs, may be applicable to other active elements Needless to say.

【００２６】[0026]

【発明の効果】以上説明したように本発明は、１つのチ
ップ上に別のチップをのせることで、チップ同士の間の
結線数の制約を解消し、またチップとインナーリード間
の結線も整理され、信頼性の高い、他ピン化に対応した
ＬＳＩを提供できる。As described above, according to the present invention, by mounting another chip on one chip, the restriction on the number of connections between the chips can be eliminated, and the connection between the chips and the inner leads can also be achieved. It is possible to provide an organized and highly reliable LSI compatible with other pins.

【図面の簡単な説明】[Brief description of drawings]

【図１】（ａ）は、本発明の実施例１に係る半導体集積
回路装置を示す平面図、（ｂ）は同断面図である。1A is a plan view showing a semiconductor integrated circuit device according to a first embodiment of the present invention, and FIG. 1B is a sectional view of the same.

【図２】（ａ）は、本発明の実施例２に係る半導体集積
回路装置を示す平面図、（ｂ）は同断面図である。2A is a plan view showing a semiconductor integrated circuit device according to a second embodiment of the present invention, and FIG. 2B is a sectional view of the same.

【図３】ＬＳＩチップの平面図である。FIG. 3 is a plan view of an LSI chip.

【図４】２つのチップを１つのアイランドに載せボンデ
ィングを実施した時の従来の方法を示す平面図である。FIG. 4 is a plan view showing a conventional method when two chips are placed on one island and bonding is performed.

【符号の説明】[Explanation of symbols]

１ ＬＳＩチップ ２，２′ パッド電極 ３′ ＣＭＯＳ部チップ ４′ バイポーラ部あるいはＥＰＲＯＭ部チップ ５ アイランド ６，６′ ボンディングワイヤ ７ インナーリード ８ バンプ 1 LSI chip 2, 2'Pad electrode 3'CMOS section chip 4'Bipolar section or EPROM section chip 5 Island 6,6 'Bonding wire 7 Inner lead 8 Bump

───────────────────────────────────────────────────── フロントページの続き (51)Int.Cl.5 識別記号 庁内整理番号 ＦＩ 技術表示箇所 Ｈ０１Ｌ 23/538 ─────────────────────────────────────────────────── ─── Continuation of the front page (51) Int.Cl. 5 Identification code Internal reference number FI technical display location H01L 23/538

Claims (2)

【特許請求の範囲】[Claims] 【請求項１】 機能等が異なる二以上の半導体チップを
上下に積層してなる半導体集積回路であって、 相対的に下層の半導体チップは、上層の半導体チップの
外周縁に沿うパッド電極を有し、該パッド電極に上層の
半導体チップのパッド電極を電気的に接続したものであ
ることを特徴とする半導体集積回路装置。1. A semiconductor integrated circuit in which two or more semiconductor chips having different functions and the like are vertically stacked, wherein a relatively lower semiconductor chip has a pad electrode along the outer peripheral edge of the upper semiconductor chip. The semiconductor integrated circuit device is characterized in that the pad electrode of an upper semiconductor chip is electrically connected to the pad electrode. 【請求項２】 機能等が異なる二以上の半導体チップを
上下に積層してなる半導体集積回路であって、 相対的に上層と下層の半導体チップは、金属バンプが形
成されたパッド電極を有しており、 上層と下層の半導体チップは、金属バンプ同士を接合し
て搭載されたものであることを特徴とする半導体集積回
路装置。2. A semiconductor integrated circuit in which two or more semiconductor chips having different functions and the like are vertically stacked, wherein the upper and lower semiconductor chips have pad electrodes with metal bumps formed thereon. In the semiconductor integrated circuit device, the upper and lower semiconductor chips are mounted by bonding metal bumps to each other.
JP4170188A 1992-06-04 1992-06-04 Semiconductor integrated circuit device Pending JPH05343609A (en)

Priority Applications (1)

Application Number Priority Date Filing Date Title
JP4170188A JPH05343609A (en) 1992-06-04 1992-06-04 Semiconductor integrated circuit device

Applications Claiming Priority (1)

Application Number Priority Date Filing Date Title
JP4170188A JPH05343609A (en) 1992-06-04 1992-06-04 Semiconductor integrated circuit device

Publications (1)

Publication Number Publication Date
JPH05343609A true JPH05343609A (en) 1993-12-24

Family

ID=15900318

Family Applications (1)

Application Number Title Priority Date Filing Date
JP4170188A Pending JPH05343609A (en) 1992-06-04 1992-06-04 Semiconductor integrated circuit device

Country Status (1)

Country Link
JP (1) JPH05343609A (en)

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US6353263B1 (en) * 1999-04-14 2002-03-05 Sharp Kabushiki Kaisha Semiconductor device and manufacturing method thereof
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US7148567B2 (en) 2001-12-03 2006-12-12 Renesas Technology Corp. Semiconductor integrated circuit device
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