JPH053434A - Signal processing circuit - Google Patents

Abstract

PURPOSE:To obtain a signal with small effect of sampling pulse crosstalk by a sample-and-hold circuit in the signal processing circuit for a CCD or the like. CONSTITUTION:An output signal of a CCD 1 is sampled by a 1st sample-and- hold circuit 2 and the output signal is amplified by a gain amplifier 3. The amplified signal is sampled again by a 2nd sample-and-hold circuit 4 and its output is inputted to an A/D conversion circuit 5.

Description

Detailed Description of the Invention

[0001]

BACKGROUND OF THE INVENTION 1. Field of the Invention The present invention relates to an improvement in the structure of a signal processing circuit of a device such as CCD.

[0002]

2. Description of the Related Art FIG. 3 is a block diagram of a conventional signal processing circuit, for example. In the figure, 1 is a CCD and 6 is the C
Sample-and-hold circuit for inputting CD1 output signal, 3
Is a gain amplifier for inputting the output signal of the sample and hold circuit 6, and 5 is an A / D conversion circuit for inputting the output signal of the gain amplifier 3.

FIG. 4 is a time chart of the waveform of each part of the block diagram shown in FIG. 3, with the CCD 1 at the top of the diagram.
Of the sample hold circuit, the next stage is the sample hold circuit sampling pulse, the next stage is the output signal of the sample hold circuit 6, and the bottom stage is the time chart of the output signal of the gain amplifier 3.

Next, the operation will be described. The output signal of the CCD 1 is input to the sample hold circuit 6, the image signal of the input signal is sampled at the timing of the sample hold circuit sampling pulse, and the sample hold circuit 6 outputs the image signal. The sampled image signal is input to the next gain amplifier 3, amplified by the gain amplifier 3, and input to the input terminal of the A / D conversion circuit 5.

[0005]

Since the conventional signal processing circuit is constructed as described above, if only the image signal is sampled and taken out from the output signal of the CCD, the output signal of the sample and hold circuit shown in FIG. 4 is obtained. As indicated by the dotted circle in the waveform of,
(Referred to as sampling pulse crosstalk) occurs, and the image signal extracted in this way is amplified by the gain amplifier of the next stage, so that the sampling pulse crosstalk is also amplified when amplification by the gain amplifier,
There is a problem that the signal including the amplified sampling pulse crosstalk is input to the A / D conversion circuit.

The present invention has been made to solve the above problems, and it is an object of the present invention to obtain a signal processing circuit capable of inputting a signal having a small influence of sampling pulse crosstalk to an A / D conversion circuit. To aim.

[0007]

In a signal processing circuit according to the present invention, an output signal of a device such as a CCD is sample-held by a first sample-hold circuit and amplified by a gain amplifier, and then a second sample is sampled. The hold circuit performs sample and hold, and the output signal of the second sample and hold circuit is input to the A / D conversion circuit.

[0008]

In the present invention, after the signal from the device is sample-held and amplified by the gain amplifier,
Since the second sample and hold circuit performs sample and hold and the output signal of the second sample and hold circuit is input to the A / D conversion circuit, the influence of sampling pulse crosstalk can be reduced. ..

[0009]

1 is a block diagram of a signal processing circuit such as a CCD according to an embodiment of the present invention. In the figure,
The same reference numerals as those in FIG. 3 denote the same or corresponding portions, and 2 denotes a CCD
1 is a first sample-hold circuit that inputs the output signal from 1 and outputs it to the gain amplifier 3. Reference numeral 4 is a second sample-hold circuit that receives the output signal of the gain amplifier 3 and outputs it to the A / D conversion circuit 5.

FIG. 2 is a time chart of the waveform of each part of the block configuration diagram shown in FIG. 1. The uppermost stage of the diagram is the CCD 1
Output signal, the next stage is the first sample and hold circuit sampling pulse, the next stage is the output signal of the first sample and hold circuit 2, the next stage is the output signal of the gain amplifier 3, and the next stage is the second stage. Sample hold circuit sampling pulse, the bottom is a time chart of the output signal of the second sample hold circuit 4.

Next, the operation will be described. The image signal of the output signal of the CCD 1 is taken out to the first sample and hold circuit 2 at the timing of the first sample and hold circuit sampling pulse, and the taken out signal is inputted to the gain amplifier 3 to be amplified. Next, a portion of the amplified signal which is not affected by the sampling pulse crosstalk of the first sample and hold circuit 2 is converted by the second sample and hold circuit 4 into the second sample and hold circuit sampling pulse. The output of the second sample hold circuit 4 is sampled at the timing A /
Input to the D conversion circuit 5.

In this embodiment, since the signal from the CCD 1 is sampled and held, amplified, and then sampled and held again, the signal having a small influence of the sampling pulse crosstalk is A / D conversion circuit 5.
Can be entered.

[0013]

As described above, according to the signal processing circuit of the present invention, the signal from the device is sampled by the first sample and hold circuit, amplified by the gain amplifier, and then again the second sample and hold circuit. Since it was sampled at and input to the A / D conversion circuit,
The sampling pulse crosstalk carried on the signal input to the A / D conversion circuit is not amplified, and as a result, a signal having a small influence of the sampling pulse crosstalk can be input to the A / D conversion circuit. is there.

[Brief description of drawings]

FIG. 1 is a block configuration diagram of a signal processing circuit according to an embodiment of the present invention.

FIG. 2 is a time chart diagram of the waveform of each part in FIG.

FIG. 3 is a block configuration diagram of a conventional signal processing circuit.

FIG. 4 is a time chart diagram of the waveform of each part in FIG.

[Explanation of symbols]

 1 CCD 2 1st sample hold circuit 3 gain amplifier 4 2nd sample hold circuit 5 A / D conversion circuit

Claims (1)

Claim: What is claimed is: 1. A sample-hold circuit for inputting a signal from a device, a gain amplifier for inputting and amplifying an output signal of the sample-hold circuit, and an input signal for output from the gain amplifier. A signal processing circuit including an A / D conversion circuit includes a second sample and hold circuit that samples and holds the output signal from the gain amplifier, and outputs the signal from the second sample and hold circuit to the A
A signal processing circuit characterized by inputting to a D / D conversion circuit.