JPH05343434A - Mesfet and device utilizing the same - Google Patents

Mesfet and device utilizing the same

Info

Publication number
JPH05343434A
JPH05343434A JP3304888A JP30488891A JPH05343434A JP H05343434 A JPH05343434 A JP H05343434A JP 3304888 A JP3304888 A JP 3304888A JP 30488891 A JP30488891 A JP 30488891A JP H05343434 A JPH05343434 A JP H05343434A
Authority
JP
Japan
Prior art keywords
layer
mesfet
source
drain
gate
Prior art date
Legal status (The legal status is an assumption and is not a legal conclusion. Google has not performed a legal analysis and makes no representation as to the accuracy of the status listed.)
Granted
Application number
JP3304888A
Other languages
Japanese (ja)
Other versions
JP3047052B2 (en
Inventor
Atsushi Nonoyama
淳 野々山
Akira Uchida
暁 内田
Sadaji Oka
貞治 岡
Takeshi Yagihara
剛 八木原
Akira Miura
明 三浦
Current Assignee (The listed assignees may be inaccurate. Google has not performed a legal analysis and makes no representation or warranty as to the accuracy of the list.)
Yokogawa Electric Corp
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Yokogawa Electric Corp
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Publication of JPH05343434A publication Critical patent/JPH05343434A/en
Application granted granted Critical
Publication of JP3047052B2 publication Critical patent/JP3047052B2/en
Anticipated expiration legal-status Critical
Expired - Fee Related legal-status Critical Current

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Abstract

PURPOSE:To obtain MESFET which does not show change of temperature and of current flowing between drain and source due to radiation of light, etc., by setting the lower part of an N type GaAs layer including drain, source and gate electrode forming positions as the P<-> layer, forming the P<++> type layer at the lower part of the P<-> layer and then forming a leadout electrode to the P<++> type layer. CONSTITUTION:An N type GaAs layer 3 is formed on a half-insulated GaAs substrate 1 and drain, source and gate electrodes 10, 5 are formed on such N type GaAs layer 3. In such MESFET, the lower part of the N type GaAs layer 3 including the electrodes 10, 5 forming region is set to the P<-> type layer 7, the P<++> type layer 8 is formed in the region under the P<-> type layer 7 and a leadout electrode 12 is formed to such P<++> type layer 8. For example, the P<++> type layer 8 is formed on the substrate 1 and the P<-> type layer 7 is formed thereon. Next, a buffer layer 2 and an operation layer 3 are formed, an InGaAs layer 9 is formed as a contact layer to the region which will become the source, drain and an electrode to is formed on the contact layer 9.

Description

【発明の詳細な説明】Detailed Description of the Invention

【0001】[0001]

【産業上の利用分野】本発明は,GaAs MESFE
Tの性能向上に関し,更に詳しくはバックゲ―ト効果の
低減をはかったMESFET及びこれを用いた装置に関
する。
BACKGROUND OF THE INVENTION The present invention relates to GaAs MESFE.
More specifically, the present invention relates to an improvement in the performance of T, and more particularly to a MESFET and a device using the same, in which the backgate effect is reduced.

【0002】[0002]

【従来の技術】図9はMESFETの一般的な構成を示
す断面図である。図において1は半絶縁性GaAs基板
であり,この基板1の上にバッファ層2および動作層3
が形成されている。4はソ―ス,5はゲ―ト,6はドレ
インである。上記の構成において,ドレイン6にソ―ス
4に対して正の電位Vd を印加すると,動作層3内で電
子がソ―スからドレインに向かって流れる。ゲ―ト電極
はショットキ―障壁であるから第1空乏層Aが動作領域
内に伸びており,ゲ―ト電圧Vg を変化させることによ
り第1空乏層Aの深さが変り,チャネルの断面積が変化
して,ドレイン・ソ―ス間電流Id が変化する。
2. Description of the Related Art FIG. 9 is a sectional view showing a general structure of a MESFET. In the figure, 1 is a semi-insulating GaAs substrate, on which a buffer layer 2 and an operating layer 3 are provided.
Are formed. 4 is a source, 5 is a gate, and 6 is a drain. In the above structure, when a positive potential Vd is applied to the drain 6 with respect to the source 4, electrons flow from the source to the drain in the operating layer 3. Since the gate electrode is a Schottky barrier, the first depletion layer A extends in the operating region. By changing the gate voltage Vg, the depth of the first depletion layer A changes and the cross-sectional area of the channel. Changes, and the drain-source current Id changes.

【0003】図10は上記従来のMESFETを用いて
高周波オシロスコ―プのアクティブプロ―ブを構成した
一例を示す回路構成図である。図10においてQ1 ,Q
2 は第1,第2のMESFETであり,Q1 のソ―スと
Q2 のドレインが接続され,その接続点に第3MESF
ETQ3 のゲ―トを接続し,前記Q1 のドレイン側にド
レイン電源VDDが,前記Q2 のソ―スにソ―ス電源VSS
が接続され,Q2 のゲートはQ2 のソースに接続されて
いる。そして,前記Q1 のゲ―トには入力端子が,前記
Q3 のソ―スには出力端子が設けられている。上記の構
成においてQ1 ,Q2 は入力インピ―ダンスを高める為
のバッファ段であり,Q2 はQ1 の定電流負荷として機
能する。Q3 は電流利得を得るための出力段である。
FIG. 10 is a circuit diagram showing an example in which an active probe of a high frequency oscilloscope is constructed by using the above-mentioned conventional MESFET. In FIG. 10, Q1, Q
2 is a first and a second MESFET, the source of Q1 and the drain of Q2 are connected, and the third MESF is connected to the connection point.
The gate of ETQ3 is connected, the drain power source VDD is connected to the drain side of Q1 and the source power source VSS is connected to the source of Q2.
Are connected, and the gate of Q2 is connected to the source of Q2. The gate of Q1 is provided with an input terminal, and the source of Q3 is provided with an output terminal. In the above structure, Q1 and Q2 are buffer stages for increasing the input impedance, and Q2 functions as a constant current load of Q1. Q3 is an output stage for obtaining a current gain.

【0004】図11はミキサの従来例を示すもので,4
0はGaAsからなるデュアルゲ―トMESFETであ
り,RF入力端子40a及び第1局部発振入力端子40
bを有している。41はドレイン電源VDDに接続される
とともにデュアルゲ―トMESFET40に接続された
第1インピ―ダンス整合回路であり,42は整合回路4
1の後段に接続された第1バンドパスフィルタである。
45はSiトランジスタであり,ベ―スにバンドパスフ
ィルタ42の出力が入力され,エミッタには抵抗R1,R
2 の接続点を介して第2局部発振が入力する。46は第
2インピ―ダンス整合回路であり,入力側にはSiトラ
ンジスタ45のコレクタが接続され,この整合回路46
の後段に第2バンドパスフィルタ47が接続されて所定
の周波数を出力する。上記の構成において,デュアルゲ
―トFET40を含むAで囲った部分は高周波用であ
り,Siトランジスタ45を含むBで囲った部分は低周
波用として機能する。なお,ミキシング素子としてはこ
れらのほかにアラログ乗算器やバイポ―ラトランジスタ
等も用いられる。
FIG. 11 shows a conventional example of a mixer.
Reference numeral 0 denotes a dual gate MESFET made of GaAs, which has an RF input terminal 40a and a first local oscillation input terminal 40.
b. Reference numeral 41 is a first impedance matching circuit connected to the drain power source VDD and also connected to the dual gate MESFET 40, and 42 is a matching circuit 4
2 is a first bandpass filter connected to the latter stage of the first band.
Reference numeral 45 is a Si transistor, the output of the bandpass filter 42 is input to the base, and resistors R1 and R are connected to the emitter.
The second local oscillation is input via the connection point of 2. The second impedance matching circuit 46 is connected to the collector of the Si transistor 45 on the input side.
A second bandpass filter 47 is connected in the subsequent stage to output a predetermined frequency. In the above structure, the portion surrounded by A including the dual gate FET 40 is for high frequency, and the portion surrounded by B including the Si transistor 45 functions for low frequency. In addition to these, an analog multiplier, bipolar transistor, etc. are also used as the mixing element.

【0005】[0005]

【発明が解決しようとする課題】ところで,上記従来の
MESFETにおいては半絶縁性基板1の漏れ電流を原
因とする縦方向のチャネル長変調によりドレイン電流が
変動する。この漏れ電流は深いトラップの電荷の出入り
によって起こり,チャネルと基板間に空間電荷領域を形
成し,ゲ―ト直下の速度飽和領域に基板1側から蓄積し
た空間電荷の為にゲ―トと同じ様にチャネルを空乏化し
第2空乏層Bが形成される(この現象はバックゲ―ト効
果と呼ばれている)。そして,このバックゲ―ト効果に
は,深いトラップが関係している為温度,光照射等によ
り特性が著しく変化する。そのために,MESFETを
測定器等のアナログおよびディジタル回路に応用した場
合には本質的な問題となる。特に直流結合の線系アンプ
を形成したときに低周波領域でゲインの異常変動が見ら
れ,更に光照射の有無によりその特性も大きく変化す
る。従来バックゲ―ト効果の抑制法としては基板1の裏
側に直接メタルをつける方法(バックゲ―ト)や動作層
の下部を高抵抗化する方法(低温成長等)が知られてい
るが,いずれも満足できる効果が得られていない。
By the way, in the above-mentioned conventional MESFET, the drain current fluctuates due to the channel length modulation in the vertical direction caused by the leakage current of the semi-insulating substrate 1. This leakage current is caused by the charge trap in and out of the deep trap, forms a space charge region between the channel and the substrate, and is the same as the gate because of the space charge accumulated from the substrate 1 side in the velocity saturation region immediately below the gate. Similarly, the channel is depleted and the second depletion layer B is formed (this phenomenon is called the backgate effect). Since the back gate effect is related to deep traps, the characteristics change remarkably depending on temperature, light irradiation, and the like. Therefore, when the MESFET is applied to an analog and digital circuit such as a measuring instrument, it becomes an essential problem. In particular, when a DC-coupled line-type amplifier is formed, an abnormal change in gain is seen in the low-frequency region, and its characteristics also change significantly depending on the presence or absence of light irradiation. Conventionally, as a method of suppressing the backgate effect, a method of directly attaching a metal to the back side of the substrate 1 (backgate) and a method of increasing the resistance of the lower part of the operating layer (low temperature growth, etc.) are known. Satisfactory effect is not obtained.

【0006】そして,上記従来のGaAs MESFE
Tを用いて図10に示すようなアクティブプロ―ブを構
成した場合は,バックゲ―ト効果によりDCドリフトが
大きく低周波特性が安定しないという問題がある。ま
た,このGaAs MESFETを用いて図11に示す
ミキサ回路を構成した場合,高周波〜低周波までの広い
範囲に渡る周波数を得たい場合は各素子の使用周波数帯
域は限られている為,高周波用と低周波用の2つの素子
が必要となる。 一般に高周波用としてはGaAs基
板,低周波用としてはSi基板上に素子が形成される。
従ってこれらを同一基板上にモノリシックに作製するこ
とはできないという問題がある。本発明は上記従来のM
ESFET及びそれを用いた装置における問題点を解決
するためになされたもので,図9に示す第2空乏層Bの
電位を零にすることにより温度変化や,光照射等により
ドレイン・ソ―ス間電流の変化のないMESFETを実
現するとともに,これを用いた装置を提供することを目
的とする。
The above-mentioned conventional GaAs MESFE is used.
When an active probe as shown in FIG. 10 is constructed using T, there is a problem that the DC drift is large due to the backgate effect and the low frequency characteristic is not stable. Further, when the mixer circuit shown in FIG. 11 is configured by using this GaAs MESFET, when it is desired to obtain frequencies over a wide range from high frequency to low frequency, the use frequency band of each element is limited. And two elements for low frequency are required. Generally, elements are formed on a GaAs substrate for high frequencies and on a Si substrate for low frequencies.
Therefore, there is a problem that these cannot be monolithically manufactured on the same substrate. The present invention is based on the conventional M
This was done in order to solve the problems in the ESFET and the device using the same, and the potential of the second depletion layer B shown in FIG. It is an object of the present invention to realize a MESFET with no change in the current flow and to provide a device using the MESFET.

【0007】[0007]

【課題を解決するための手段】上記課題を解決する為に
本発明は,請求項1においては半絶縁性GaAs基板上
にn形GaAs層が形成され,該n形GaAs層上にド
レイン,ソ―ス,およびゲ―ト電極を形成したMESF
ETにおいて,前記電極形成箇所を含む前記n形GaA
s層の下部をp- 層とし,該p- 層の下部にp++層を形
成するとともに該p++層に取出し電極を形成したことを
特徴とするものであり,請求項2においては第1,第2
MESFETのソ―スとドレインが接続され,その接続
点に第3MESFETのゲ―トを接続し,前記第1FE
Tのドレイン側にドレイン電源が,前記第2MESFE
Tのソ―スにソ―ス電源が接続され,前記第1MESF
ETのゲ―トに入力端子を,前記第3MESFETのソ
―スに出力端子を設けたアクティブプロ―ブにおいて,
前記MESFETとして請求項1記載のMESFETを
用い,前記第1,第3MESFETの取出し電極をそれ
ぞれのソ―スに接続し,前記第2MESFETの取出し
電極に電圧補正用入力端子を設けたことを特徴とするも
のであり,請求項3においては第1,第2の2つの周波
数を入力してミキシングするミキサにおいて,ミキシン
グ素子として請求項1記載のMESFETを用い,該M
ESFETのゲ―トに第1の周波数を入力し,取出し電
極に第2の周波数を入力するとともにドレイン側に出力
端子を設けたことを特徴とするものである。
In order to solve the above-mentioned problems, according to the present invention, in claim 1, an n-type GaAs layer is formed on a semi-insulating GaAs substrate, and a drain and a semiconductor are formed on the n-type GaAs layer. -MESF with gate and gate electrodes
In ET, the n-type GaA including the electrode formation portion
The lower part of the s layer is a p layer, the p + + layer is formed under the p layer, and the extraction electrode is formed on the p + + layer. First and second
The source and the drain of the MESFET are connected, and the gate of the third MESFET is connected to the connection point, and the first FE is connected.
The drain power source is connected to the drain side of T and is connected to the second MESFE.
A source of power is connected to the source of T, and the first MESF is connected.
In an active probe having an input terminal at the gate of ET and an output terminal at the source of the third MESFET,
The MESFET according to claim 1 is used as the MESFET, the extraction electrodes of the first and third MESFETs are connected to respective sources, and the extraction electrode of the second MESFET is provided with a voltage correction input terminal. In the mixer for inputting and mixing the first and second frequencies, the MESFET according to claim 1 is used as a mixing element, and the M
It is characterized in that the first frequency is input to the gate of the ESFET, the second frequency is input to the extraction electrode, and an output terminal is provided on the drain side.

【0008】[0008]

【作用】請求項1に関し,第2空乏層の電位はp- ,p
++層を介して取出し電極により取出される。その電極を
任意の電位に固定する。このことにより温度変化や光照
射等によるドレイン・ソ―ス間電流の変化を低減させ
る。請求項2に関し,請求項1記載のMESFETを用
いている為,DC特性が極めて安定し,高周波特性も有
しているので広帯域にわたる電気信号を伝送することが
できる。請求項3に関し,広帯域にわたって同一の素子
で設計することができるので,設計が容易となり,モノ
リシック化が可能となり高周波回路としての性能が向上
する。
With respect to claim 1, the potential of the second depletion layer is p , p
It is taken out by the take-out electrode through the ++ layer. The electrode is fixed at an arbitrary potential. This reduces changes in the drain-source current due to temperature changes and light irradiation. With respect to the second aspect, since the MESFET according to the first aspect is used, the DC characteristic is extremely stable and the high frequency characteristic is also provided, so that the electric signal can be transmitted over a wide band. With respect to the third aspect, since the same element can be designed over a wide band, the design is facilitated, monolithicization is possible, and the performance as a high frequency circuit is improved.

【0009】[0009]

【実施例】図1は本発明の一実施例を示す構成断面図で
ある。図1において図9と同一要素には同一符号を付し
て重複する説明は省略し,配線部分も省略する。本実施
例においては,はじめに基板1上に0.5〜1μm程度
の厚さのp++層8を形成し,その上にp- 層7を例えば
1〜2μm程度の厚さに形成する。次にバッファ層2お
よび動作層3を形成し,ソ―ス,ドレインとなる部分に
コンタクト層としてのInGaAs層9を形成するとと
もに,そのコンタクト層の上に例えばWSi/Auから
なる電極を形成する。なお,ゲ―ト電極5としては動作
層3に直接W/WSiを形成する。次に,MESFET
の近傍に穴11を形成し,その穴11に基板表面に達す
る取出し電極12を形成する。
DESCRIPTION OF THE PREFERRED EMBODIMENTS FIG. 1 is a sectional view showing the construction of an embodiment of the present invention. In FIG. 1, the same elements as those in FIG. 9 are designated by the same reference numerals, duplicate description is omitted, and wiring portions are also omitted. In this embodiment, first, a p + + layer 8 having a thickness of about 0.5 to 1 μm is formed on the substrate 1, and a p layer 7 is formed thereon to a thickness of, for example, about 1 to 2 μm. Next, the buffer layer 2 and the operation layer 3 are formed, the InGaAs layer 9 as a contact layer is formed in the portions to be the source and drain, and the electrode made of, for example, WSi / Au is formed on the contact layer. .. As the gate electrode 5, W / WSi is directly formed on the operating layer 3. Next, MESFET
A hole 11 is formed in the vicinity of, and an extraction electrode 12 reaching the surface of the substrate is formed in the hole 11.

【0010】上記の構成によれば,取出し電極12を例
えば接地することにより第2空乏層の電位を零電位とし
たり,適当な安定電位を有する箇所に接続することによ
り固定することができ,温度変化や,光照射等によるド
レイン・ソ―ス間の電流(Id )の変化を抑制すること
ができる。図2,図3は本発明者等が作製した取出し電
極付きGaAs MESFET(以下,PG−FETと
いう)と取出し電極なしの場合の各FETの特性を示す
比較図である。図2はFETに光を照射した場合のバッ
クゲート電圧とドレイン−ソース間電流の変化率の関係
を示す図であり,(a)は取出し電極付き,(b)は取
出し電極なしの場合である。なお,バックゲート電圧は
ソースを基準にした時の基板の裏側の電位を表し,PG
−FETの測定時には取出し電極はソ−ス電極に接続し
た。光照射(タングステンランプ)によりディ−プレベ
ルトラップ(Deeplevel trap)やその他
の欠陥(defect)は強力に活性化され,更に半絶
縁性GaAs基板の漏れ電流の増大をあおり絶縁性を著
しく低下させる。 図2によれば取出し電極付きの場合
は光照射の有無にかかわらず極めて安定であり,バック
ゲート電位の影響を全くうけていないことが分る。図3
はゲインが10dB程度の直流アンプを形成し,低周波
領域における周波数とドレイン出力電圧の変化率の関係
を示すもので,(a)は取出し電極付き,(b)は取出
し電極なしの場合である。図によれば,取出し電極なし
の場合は周波数の変化に対して出力電圧が30〜40%
程度変化するが,取出し電極付きの場合は2%程度の範
囲であり,極めて精度よく安定していることが分る。図
4は本発明の他の実施例を示す構成断面図である。図1
の実施例とはp++層の長さが異なる。即ち,p++層を挿
入したことによりドレイン−ソ―ス間の容量増大が問題
となる場合はp++層の長さをゲ―トの空乏層付近までと
する。
According to the above structure, the potential of the second depletion layer can be set to zero potential by grounding the extraction electrode 12, for example, or can be fixed by connecting it to a place having an appropriate stable potential. It is possible to suppress changes and changes in the current (Id) between the drain and the source due to light irradiation or the like. 2 and 3 are comparative diagrams showing the characteristics of the GaAs MESFET with extraction electrode (hereinafter referred to as PG-FET) manufactured by the present inventors and the respective FETs without extraction electrode. 2A and 2B are diagrams showing the relationship between the back gate voltage and the rate of change in the drain-source current when the FET is irradiated with light. FIG. 2A is a case with an extraction electrode, and FIG. .. The back gate voltage represents the potential on the back side of the substrate when the source is used as a reference, and PG
-When measuring the FET, the extraction electrode was connected to the source electrode. The light irradiation (tungsten lamp) strongly activates deep level traps and other defects, which further increases the leakage current of the semi-insulating GaAs substrate and significantly lowers the insulating property. According to FIG. 2, it can be seen that the case with the extraction electrode is extremely stable regardless of the presence or absence of light irradiation, and is not affected by the back gate potential at all. Figure 3
Shows the relationship between the frequency and the rate of change of the drain output voltage in the low frequency region, which forms a DC amplifier with a gain of about 10 dB. (A) is the case with an extraction electrode, (b) is the case without an extraction electrode . According to the figure, the output voltage is 30 to 40% with respect to the change in frequency without the extraction electrode.
Although it varies to some extent, it is found to be extremely accurate and stable in the range of about 2% for the case with the extraction electrode. FIG. 4 is a sectional view showing the construction of another embodiment of the present invention. Figure 1
The length of the p ++ layer is different from that of the above embodiment. That is, the drain by inserting the p ++ layer - source - if increased capacitance between the scan is a problem the length of the p ++ layer gate - and to the vicinity of bets of the depletion layer.

【0011】図5は本発明の請求項2に関する一実施例
を示す回路構成図である。図5において,従来のアクテ
ィブプロ―ブ(図8)と異なる点は第1〜第3MESF
ETとして請求項1記載のPG−FETを用い,第1,
第3PG−FETQ1´,Q2´の取出し電極をそれぞれ
のソ―スに接続し,第3PG−FETQ3´の取出し電
極に電圧補正用入力端子を接続している。上記の構成に
おいてQ2´はQ1´の定電流負荷として機能し,Q2´
のバックゲ―トに接続された補正用端子30に所定の電
圧を印加することによりQ1´の動作点の変動を押える
ことができる。その結果,ノイズの少ないアクティブプ
ロ―ブをを実現することができる。
FIG. 5 is a circuit configuration diagram showing an embodiment according to claim 2 of the present invention. 5 is different from the conventional active probe (FIG. 8) in the first to third MESFs.
The PG-FET according to claim 1 is used as ET, and
The extraction electrodes of the third PG-FETs Q1 'and Q2' are connected to their respective sources, and the extraction electrodes of the third PG-FET Q3 'are connected to voltage correction input terminals. In the above configuration, Q2 'functions as a constant current load for Q1', and Q2 '
The fluctuation of the operating point of Q1 'can be suppressed by applying a predetermined voltage to the correction terminal 30 connected to the back gate. As a result, an active probe with less noise can be realized.

【0012】図6は本発明の請求項3に関する一実施例
を示す回路構成図である。図6において50は入力信号
(RF)が入力する第1バンドパスフィルタ,51はそ
の後段に接続された第1インピ―ダンス整合回路であ
る。この整合回路51の出力はコンデンサC1 及び抵抗
R1 ,R2 の接続点を介して線形動作を行う様にバイア
スされてPG−FETのゲ―トに接続されている。
FIG. 6 is a circuit configuration diagram showing an embodiment according to claim 3 of the present invention. In FIG. 6, reference numeral 50 is a first bandpass filter to which an input signal (RF) is input, and 51 is a first impedance matching circuit connected to the subsequent stage. The output of the matching circuit 51 is biased so as to perform a linear operation via the connection point of the capacitor C1 and the resistors R1 and R2, and is connected to the gate of the PG-FET.

【0013】52は局部発振信号(LO)が入力する第
2バンドパスフィルタ,53はその後段に接続された第
2インピ―ダンス整合回路である。この整合回路52の
出力はコンデンサC2 及び抵抗R3 ,R4 の接続点を介
して非線形動作を行う様にバイアスされてPG−FET
60の取出し電極に接続されている。56はドレイン電
源VDD及びPG−FET60のドレイン側に接続された
第3インピ―ダンス整合回路,57は整合回路56の後
段に接続された第3バンドパスフィルタである。
Reference numeral 52 is a second bandpass filter to which the local oscillation signal (LO) is input, and reference numeral 53 is a second impedance matching circuit connected to the subsequent stage. The output of the matching circuit 52 is biased so as to perform a non-linear operation via the connection point of the capacitor C2 and the resistors R3 and R4, and the PG-FET.
It is connected to 60 extraction electrodes. 56 is a third impedance matching circuit connected to the drain power source VDD and the drain side of the PG-FET 60, and 57 is a third bandpass filter connected to the subsequent stage of the matching circuit 56.

【0014】図7は上記回路におけるPG−FETの空
乏層の変化を示すもので,PG−FETのドレイン−ソ
―ス間に流れる電流は第1空乏層およぴ第2空乏層の拡
がりによって決定される。これらの空乏層はゲ―ト―ソ
―ス間電圧およびバックゲ―ト−ソ―ス間電圧によって
その拡がりを制御することが出来る。従ってゲ―ト―ソ
―ス間およびバックゲ―ト−ソ―ス間に図に示すように
入力信号(RF)および局部発振信号(LO)を接続す
れば第1空乏層およぴ第2空乏層が矢印で示すように変
化し,その変化によってドレイン−ソ―ス間電流が変化
する。つまり,第1空乏層の変化に比例して変化してい
るドレイン−ソ―ス間電流が第2空乏層の変化によって
変調を受けることになる。このドレイン−ソ―ス間電流
はRF信号の定数倍の周波数およびLO信号の定数倍の
周波数の和と差の成分を含んでおり,この中から必要な
成分を取り出すことができる。
FIG. 7 shows changes in the depletion layer of the PG-FET in the above circuit. The current flowing between the drain and source of the PG-FET depends on the spread of the first depletion layer and the second depletion layer. It is determined. The spread of these depletion layers can be controlled by the gate-source voltage and the back-gate-source voltage. Therefore, if the input signal (RF) and the local oscillation signal (LO) are connected between the gate and the source and between the back gate and the source as shown in the figure, the first depletion layer and the second depletion layer are depleted. The layer changes as shown by the arrow, and the change changes the drain-source current. That is, the drain-source current, which changes in proportion to the change in the first depletion layer, is modulated by the change in the second depletion layer. The drain-source current includes the sum and difference components of the frequency that is a constant multiple of the RF signal and the frequency of a constant multiple of the LO signal, and the necessary component can be extracted from this.

【0015】[0015]

【発明の効果】以上実施例とともに具体的に説明した様
に,本発明のMESFETによれば,電極形成箇所を含
む前記n形GaAs層の下部をp- 層とし,該p- 層の
下部にp++層を形成するとともに該p++層に取出し電極
を形成したので,温度変化や,光照射等によりドレイン
・ソ―ス間電流の変化を低減させることができ,例えば
IC化した場合にすべての取出し電極を固定電位にした
り,回路的な面で独立したい場合(フィ―ドバックを掛
ける場合など)にも容易に分離独立して配線することが
可能なMESFETを実現することができる。また,こ
のPG−FETを用いたアクティブプロ―ブは広帯域に
わたる正確な信号伝達が実現でき,ミキサを構成した場
合は広帯域におけるミキシング素子を同一基板上に形成
することができるので設計が容易となり,高周波回路と
しての性能を向上させることができる。
As described above in detail with reference to the embodiments, according to the MESFET of the present invention, the lower portion of the n-type GaAs layer including the electrode forming portion is a p layer, and the p layer is formed below the p layer. Since the p + + layer is formed and the extraction electrode is formed on the p + + layer, it is possible to reduce the change in the drain-source current due to temperature change or light irradiation. In addition, it is possible to realize a MESFET in which all the extraction electrodes can be set to a fixed potential or can be easily separated and independently wired even when it is desired to be independent in terms of a circuit (for example, when feedback is applied). Also, the active probe using this PG-FET can realize accurate signal transmission over a wide band, and when a mixer is configured, a wide band mixing element can be formed on the same substrate, which facilitates design, The performance as a high frequency circuit can be improved.

【図面の簡単な説明】[Brief description of drawings]

【図1】本発明のMESFETの一実施例を示す構成断
面図である。
FIG. 1 is a configuration cross-sectional view showing one embodiment of a MESFET of the present invention.

【図2】本発明のMESFETと従来のMESFETに
光を照射した場合のバックゲート電圧とドレイン−ソー
ス間電流の変化率の関係を示す図である。
FIG. 2 is a diagram showing a relationship between a back gate voltage and a change rate of a drain-source current when a MESFET of the present invention and a conventional MESFET are irradiated with light.

【図3】本発明のMESFETと従来のMESFETの
低周波領域における周波数とドレイン出力電圧の変化率
の関係を示す図である。
FIG. 3 is a diagram showing a relationship between a frequency and a change rate of a drain output voltage in a low frequency region of the MESFET of the present invention and the conventional MESFET.

【図4】本発明のMESFETの他の実施例を示す構成
断面図である。
FIG. 4 is a sectional view showing the configuration of another embodiment of the MESFET of the present invention.

【図5】本発明のMESFETをアクティブフイルタに
用いた一実施例を示す回路構成図である。
FIG. 5 is a circuit configuration diagram showing an embodiment in which the MESFET of the present invention is used for an active filter.

【図6】本発明のMESFETをミキサとして用いた一
実施例を示す回路構成図である。
FIG. 6 is a circuit configuration diagram showing an embodiment using the MESFET of the present invention as a mixer.

【図7】本発明のMESFETをミキサに用いた場合の
空乏層の変化を示す図である。
FIG. 7 is a diagram showing changes in the depletion layer when the MESFET of the present invention is used in a mixer.

【図8】本発明のMESFETをミキサとして用いた他
の実施例を示す回路構成図である。
FIG. 8 is a circuit configuration diagram showing another embodiment using the MESFET of the present invention as a mixer.

【図9】MESFETの一般的な構成を示す断面図であ
る。
FIG. 9 is a cross-sectional view showing a general configuration of MESFET.

【図10】アクティブフィルタの従来例を示す回路構成
図である。
FIG. 10 is a circuit configuration diagram showing a conventional example of an active filter.

【図11】ミキサの従来例を示す回路構成図である。FIG. 11 is a circuit configuration diagram showing a conventional example of a mixer.

【符号の説明】[Explanation of symbols]

1 半絶縁性GaAs基板 2 バッファ層 3 動作層 4 ソ―ス 5 ゲ―ト 6 ドレイン 7 p- 層 8 p++層 9 InGaAs層 10 電極 11 穴 12 取出し電極 50 第1バンドパスフィルタ 51 第1インピ―ダンス整合回路 52 第2バンドパスフィルタ 53 第2インピ―ダンス整合回路 56 第3バンドパスフィルタ 57 第3インピ―ダンス整合回路 60 PG−FET(取出し電極付GaAs MESF
ET) 61 モノリシックIC
1 semi-insulating GaAs substrate 2 buffer layer 3 operating layer 4 source 5 gate 6 drain 7 p layer 8 p ++ layer 9 InGaAs layer 10 electrode 11 hole 12 extraction electrode 50 first bandpass filter 51 1st Impedance matching circuit 52 Second bandpass filter 53 Second impedance matching circuit 56 Third bandpass filter 57 Third impedance matching circuit 60 PG-FET (GaAs MESF with extraction electrode)
ET) 61 Monolithic IC

───────────────────────────────────────────────────── フロントページの続き (51)Int.Cl.5 識別記号 庁内整理番号 FI 技術表示箇所 // H03K 17/687 (72)発明者 八木原 剛 東京都武蔵野市中町2丁目9番32号 横河 電機株式会社内 (72)発明者 三浦 明 東京都武蔵野市中町2丁目9番32号 横河 電機株式会社内─────────────────────────────────────────────────── ─── Continuation of the front page (51) Int.Cl. 5 Identification number Internal reference number FI Technical display location // H03K 17/687 (72) Inventor Tsuyoshi Yagihara 2-932 Nakamachi, Musashino City, Tokyo Horizontal Kawa Electric Co., Ltd. (72) Inventor Akira Miura 2-9-32 Nakamachi, Musashino-shi, Tokyo Yokogawa Electric Co., Ltd.

Claims (3)

【特許請求の範囲】[Claims] 【請求項1】 半絶縁性GaAs基板上にn形GaAs
層が形成され,該n形GaAs層上にドレイン,ソ―
ス,およびゲ―ト電極を形成したMESFETにおい
て,前記電極形成箇所を含む前記n形GaAs層の下部
をp- 層とし,該p- 層の下部にp++層を形成するとと
もに該p++層に取出し電極を形成したことを特徴とする
MESFET。
1. N-type GaAs on a semi-insulating GaAs substrate
A layer is formed, and a drain and a source are formed on the n-type GaAs layer.
Scan, and gate - in MESFET forming the gate electrode, the lower portion of the n-type GaAs layer including the electrode forming portion p - a layer, the p - said to form a p ++ layer in the lower layer p + A MESFET having an extraction electrode formed on the + layer.
【請求項2】 第1,第2MESFETのソ―スとドレ
インが接続され,その接続点に第3MESFETのゲ―
トを接続し,前記第1FETのドレイン側にドレイン電
源が,前記第2MESFETのソ―スにソ―ス電源が接
続され,前記第1MESFETのゲ―トに入力端子を,
前記第3MESFETのソ―スに出力端子を設けたアク
ティブプロ―ブにおいて,前記MESFETとして請求
項1記載のMESFETを用い,前記第1,第3MES
FETの取出し電極をそれぞれのソ―スに接続し,前記
第2MESFETの取出し電極に電圧補正用入力端子を
設けたことを特徴とするアクティブプロ―ブ。
2. The source and drain of the first and second MESFETs are connected, and the gate of the third MESFET is connected to the connection point.
A drain power source is connected to the drain side of the first FET, a source power source is connected to the source of the second MESFET, and an input terminal is connected to the gate of the first MESFET.
The MESFET according to claim 1 is used as the MESFET in an active probe in which an output terminal is provided on the source of the third MESFET, and the first and third MES are used.
An active probe characterized in that the extraction electrode of the FET is connected to each source, and the extraction electrode of the second MESFET is provided with a voltage correction input terminal.
【請求項3】 第1,第2の2つの周波数を入力してミ
キシングするミキサにおいて,ミキシング素子として請
求項1記載のMESFETを用い,該MESFETのゲ
―トに第1の周波数を入力し,取出し電極に第2の周波
数を入力するとともにドレイン側に出力端子を設けたこ
とを特徴とするミキサ。
3. A mixer for inputting and mixing two first and second frequencies, wherein the MESFET according to claim 1 is used as a mixing element, and the first frequency is input to the gate of the MESFET. A mixer characterized in that a second frequency is inputted to an extraction electrode and an output terminal is provided on a drain side.
JP03304888A 1991-06-27 1991-11-20 Apparatus using MESFET Expired - Fee Related JP3047052B2 (en)

Applications Claiming Priority (2)

Application Number Priority Date Filing Date Title
JP3-156712 1991-06-27
JP15671291 1991-06-27

Publications (2)

Publication Number Publication Date
JPH05343434A true JPH05343434A (en) 1993-12-24
JP3047052B2 JP3047052B2 (en) 2000-05-29

Family

ID=15633690

Family Applications (1)

Application Number Title Priority Date Filing Date
JP03304888A Expired - Fee Related JP3047052B2 (en) 1991-06-27 1991-11-20 Apparatus using MESFET

Country Status (1)

Country Link
JP (1) JP3047052B2 (en)

Cited By (1)

* Cited by examiner, † Cited by third party
Publication number Priority date Publication date Assignee Title
JPH08148672A (en) * 1994-11-17 1996-06-07 Nec Corp Hetero junction type of field effect transistor, and its manufacture

Cited By (1)

* Cited by examiner, † Cited by third party
Publication number Priority date Publication date Assignee Title
JPH08148672A (en) * 1994-11-17 1996-06-07 Nec Corp Hetero junction type of field effect transistor, and its manufacture

Also Published As

Publication number Publication date
JP3047052B2 (en) 2000-05-29

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