JP3044904B2 - Compound semiconductor device - Google Patents

Description

DETAILED DESCRIPTION OF THE INVENTION

[0001]

The present invention relates to a semi-insulating GaAs substrate.
The present invention relates to a compound semiconductor device for reducing distortion in a low frequency region of an integrated circuit using an s substrate.

[0002]

2. Description of the Related Art In recent years, GaAs devices have been mainly used in the high frequency field, but their distortion becomes a problem in a low frequency region of about 10 (kHz) or less. FIG. 5 (a),
(C) shows a configuration diagram of a GaAs Schottky gate field effect transistor (hereinafter referred to as GaAs MESFET). FIG. 1A shows a case without a high resistance buffer layer, and FIG. 2C shows a case with a high resistance buffer layer below a channel. GaAs having a high resistance buffer layer shown in FIG.
no hysteresis V _DS -I _D characteristic as the sMESFET (d). On the other hand, the GaAsMESFET no high-resistance buffer layer shown in FIG. 6 (a), in the low frequency region due to the lattice defect or the like, to have a hysteresis in V _DS -I _D characteristic as shown in (b) Are known. Therefore, the signal frequency band is D like a sample-and-hold circuit (hereinafter referred to as an S / H circuit) or a wideband amplifier.
In the case of wide band from C to high frequency, Ga shown in (a)
In the circuit constituted by the AsMESFET, the input / output characteristics of the circuit have a hysteresis in a low frequency region, and the distortion increases due to the hysteresis, so that good characteristics cannot be obtained.

An example of a circuit using a GaAs MESFET according to the prior art will be described below with reference to the drawings.

FIG. 6 shows a source follower circuit using an FET. 6, reference numeral 61 denotes a signal input terminal, 62 denotes a signal output terminal, 63 denotes a power supply terminal, and Q61 denotes an n-channel FE.
T and R61 are resistors. The signal input terminal 61 is FETQ
61 is connected to the gate. The signal output terminal 62 is an FET
Connected to source of Q61. Power supply terminal 63 is FETQ
61 is connected to the drain. The resistance R61 is FE
It is connected between the source of TQ61 and the ground.

The operation of the FET source follower circuit configured as described above will be described below.

In FIG. 6, when the input signal is V_INFrom positive to negative
V in the direction_IN ^-, V_IN ⁺Consider the case where it changes to However,
At this time, | V_IN ^--V_IN| = | V_IN ⁺-V_IN|
You. V in this circuit_GSー I_DCharacteristics and load curves and
V_DSー I_DThe characteristics and the load curve are shown in FIGS.
As shown in FIG._INV_GSIs V _GS
^-, V_GS ⁺Changes to At this time, the V_GSー I_DCharacteristic
Is a quadratic curve, so | V_GS ^--V_GS｜ ≠ ｜ V_GS ⁺-V
_GS|. Also, the drain current I of the FET Q61_D Also
I_D To I_D ^-, I_D ⁺Changes to | I_D ^- -I_D｜ ≠ ｜ I_D ⁺
 -I_D|. This drain current I_D Figure of change
V in (b)_DSー I_DWhen plotted on the characteristic, | I_D ^-−
I_D｜ ≠ ｜ I_D ⁺-I_D| So output V_O | V_O ^-
-V_O｜ ≠ ｜ V_O ⁺-V_O|. Therefore, as an input signal
V_INIf you give the center sine wave, it will be obtained as output
The signal is V_O The waveform becomes asymmetrical up and down around
That is, the output waveform is distorted. Also, the amplitude of the input signal is large.
Indeed, V_GS-I_D Wide nonlinear region in characteristics
Because of the use, the distortion of the output waveform increases.

FIG. 8 shows a source follower circuit which solves the problem of the circuit of FIG. 6 and suppresses distortion even when the amplitude of the input signal is large. 8, 81 is a signal input terminal,
82 is a signal output terminal, 83 is a power supply terminal (positive), 84 is a power supply terminal (negative), Q81 and Q82 are n-channel FETs, D
81 and D82 are diodes, and I81 and I82 are constant current sources. FET Q81 and FET Q82 are connected in series, and the drain of FET Q81 and the source of FET Q82 are connected. The diode D81 and the diode D82 are connected in series, and the anode of the diode D81 is connected to the FET Q
The gate of the diode 82 and the cathode of the diode D82
Connected to source of Q81. Power supply terminal 83 is FETQ
82 is connected to the drain. The signal input terminal 81 is FE
Connected to the gate of TQ81. The signal output terminal 82 is
Connected to the source of ETQ81. The constant current source I81 is connected between the power supply terminal 83 and the gate of the FET Q82.
The constant current source I82 is connected to the source of the FET Q81 and the power terminal 84.
Connected between

The operation of the FET source follower circuit configured as described above will be described below.

The constant current source I81 includes diodes D81 and D8.
A constant current is passed through 2. As a result, the diodes D81 and D81
The voltage across the terminal 82 becomes constant, and the voltage between the source of the FET Q81 and the gate of the FET Q82 is kept constant.
When the input voltage V _IN changes, small variations in V _GS of FETQ82 compared to the variation of V _DS of FETQ82. FETQ
Since 81 the voltage between the gate of the source and FETQ82 of constant, variations in the V _DS of FETQ81 be kept small,
Fluctuations in the V _GS of FETQ81 is further reduced. By the way, the output voltage is V _O = V _IN −V _GS . That is, in the circuit of FIG. 8, the variation of V _GS is suppressed as compared with FIG. 6, and only a small area near the operating point is used. Therefore, the V _GS -I _D characteristic can be regarded as almost linear, and the distortion is improved. .

[0010]

In the case where a circuit as shown in FIG. 8 is formed using GaAs MESFETs, as a conventional technique, the back potential of the GaAs substrate is usually kept at the same potential as the ground. At this time, FIG.
GaAsME having no high resistance buffer layer shown in FIG.
In SFET, with hysteresis in V _DS -I _D characteristic as shown in FIG. (B). Therefore, even when the circuit configuration as shown in FIG. 8 is used, there is a problem that the distortion increases in the lower frequency region due to the hysteresis.

[0011] The present invention has been made in view of the above problems, in the GaAs integrated circuit without the high-resistance buffer layer, to improve the hysteresis of V _DS -I _D characteristic in a low frequency region of the element,
An object of the present invention is to provide a compound semiconductor device having less distortion in a low frequency region.

[0012]

According to the present invention, there is provided a compound semiconductor device comprising: a GaAs substrate; an integrated circuit formed on the GaAs substrate; an electrode on a back surface of the GaAs substrate;
Either a circuit for applying a voltage proportional to the input signal voltage of the integrated circuit to an electrode on the back surface of the GaAs substrate is provided on or outside the As substrate, or the input of the integrated circuit is branched and directly connected to the back surface of the GaAs substrate. This problem is solved by applying the voltage to the electrodes.

[0013]

[Action] cause of distortion in the low frequency region of the circuit using GaAsMESFET by a hysteresis of the V _DS -I _D characteristic. According to the present invention, by applying a voltage proportional to the input signal voltage to the back surface of the GaAs substrate by the above configuration, the V _{DS in the} GaAs MESFET having no high resistance buffer layer is realized.
Improved hysteresis -I _D characteristic, and suppresses the distortion of the circuit in the low frequency region of GaAs integrated circuits.

[0014]

(Embodiment 1) In this embodiment, GaAs is used.
A silver paste was applied to the back surface of the substrate to form a back electrode, and a voltage was applied to the back surface.

FIG. 1 shows an S-type semiconductor device using a GaAs MESFET.
/ H is an embodiment of an integrated circuit. In FIG. 1, reference numeral 11 denotes an analog signal input terminal (input voltage: 0 (V) to -2.0
(V)) and 12 are analog signal output terminals (output voltage: 0
(V) to -2.0 (V)), 13 is a clock input terminal (ECL level), 14a, 14b, 14c, and 16 are buffer circuits, and 15 is an analog switch using a diode bridge and a hold capacitor. It is a sampler. Reference numeral 17 denotes a GaAs substrate, and reference numeral 18 denotes an amplifier circuit having a gain of 1 constituted by an operational amplifier and having a function of converting a center voltage from -1.0 (V) to 0 (V) (shifting a DC bias). It was configured outside the GaAs substrate. Here, the analog signal input terminal 11 is connected to the buffer 14
Connected to input of a. The analog signal output terminal 12 is connected to the output of the buffer 14c. Clock input terminal 1
3 is connected to the input of the buffer 16. Buffer 14a
Is connected to the input of the sampler 15. Buffer 1
The output of 6 is connected to the clock input of sampler 15.
The output of sampler 15 is connected to the input of buffer 14b. The output of buffer 14b is connected to the input of buffer 14c. The input of the operational amplifier 18 is connected to the analog signal input terminal 11. The output of the operational amplifier circuit 18 is connected to the back surface of the GaAs substrate 17.

The operation principle of the S / H circuit thus configured will be described. The input signal is input to the sampler 15 through the buffer 14a. The sampler 15 holds the input value when the clock input terminal voltage is high (−0.7 (V) because of the ECL level), and is low (E
At the time of -1.7 (V) because of the CL level, the input signal is output as it is. The output of the sampler 15 is further output through buffers 14b and 14c. The buffer 16
Shaping the clock waveform for driving the sampler.
Here, the buffers 14a, 14b, and 14c and the sampler 15 directly contribute to the distortion between input and output. Among them, the influence of the distortion by the sampler 15 is small, and the buffer 1
4a, 14b, and 14c are mostly affected. By the way, the buffers 14a, 14b, 1
All the circuit configurations 4c use the source follower circuit shown in FIG.

S / H using this GaAs MESFET
In the conventional technology of the integrated circuit, the back surface potential of the GaAs substrate is set to 0 (V) (connected to the circuit ground).
In this case, the following problems are observed. That is, the voltage of the clock input terminal is set to low and the analog signal input terminal 1
If a sine wave is input to 1, the output should be a sine wave. However, the lower the frequency, the more the output waveform was distorted. Usually, such a phenomenon is not observed in a MOSFET using a Si substrate. This is because, in the prior art, GaAs MESF is so large that it is in a low frequency region.
The hysteresis V _DS -I _D characteristic of ET increases is caused.

However, when the input signal voltage is applied to the operational amplifier circuit 1
8, the center voltage is converted from -1.0 (V) to 0 (V),
By inputting data on the backside of the wafer, each GaAsME
Since the hysteresis of the V _DS -I _D characteristic of SFET is improved, output characteristics of the source follower circuit is closer to a straight line,
The distortion at low frequencies was improved.

Here, GaAs was used to confirm the effect.
The V _DS -I _D static characteristics of a single unit of MESFET were measured. Figure 2 is a V _DS -I _D static characteristic measurement circuit of GaAs MESFET. In FIG. 2, 21 is an oscillator, 22 and 23 are amplifiers, 24 is a GaAs substrate, 25 is an operational amplifier circuit, 26
Is an oscilloscope, and Q21 is a GaAs MESFET formed on a GaAs substrate. Amplifier 22, Amplifier 23
Is connected to the output of the oscillator 21. The output of the amplifier 22 is connected to the drain of the GaAs MESFET Q21 and the input V _IN1 of the operational amplifier circuit 25. The output of the amplifier 23 is connected to the back surface of the GaAs substrate 24. GaAs
The gate and source of the MESFET Q21 are both the input V _{IN2 of} the operational amplifier circuit 25, the resistor R21, and the oscilloscope 2.
6 Y inputs. The other end of the resistor R21 is connected to the ground. The output of the operational amplifier circuit 25 is connected to the X input of the oscilloscope 26.

V _DS- of the GaAs MESFET having the above structure
The operation principle of the _ID static characteristic measuring circuit will be described.

The sine wave output from the oscillator 21 is converted to a sine wave of 2.5 through an amplifier 22 peak-to-peak value (V) center 5 (V) (hereinafter, referred to as V _pp) , GaAs MESFET Q21. Similarly, a sine wave is also input to the amplifier 23,
(V) It is output as a sine wave with a center of 5 V _pp and input to the back surface of the GaAs substrate 24. GaAs MESFET Q2
Since the source and gate of 1 are short-circuited, V _GS = 0
(V). Since the gain of the operational amplifier 25 is 1, V _{DS of} the GaAs MESFET Q 21 is input to X of the oscilloscope 26. The drain current at this time was obtained by inputting the voltage between both ends of the resistor R21 to Y of the oscilloscope 26 and converting the voltage into a current value. Thus, by operating the oscilloscope 26 in the XY operation,
The V _DS -I _D static characteristics of GaAsMESFET was measured.

FIG. 3 (a) shows 0 (V) on the back of the GaAs substrate.
V _DS -I _D characteristic of GaAsMESFET upon application of, (b) the GaAs substrate back surface 0 (V) center 5V _pp
GaAsMESFET of V _DS at the time of applying a sine wave
-I _D characteristic. The frequency of the applied sine wave is 10 (H
z). The threshold voltage V _TH of the measured GaAsFET is -1.0 (V), the gate width W _G 50
(Μm). The hysteresis observed when the potential on the back surface of the GaAs substrate is 0 (V) is shown in FIG.
Is small when the back surface potential is 5 V _pp sine wave. That is, the V _{DS of} the GaAs MESFET is changed by changing the back potential of the GaAs substrate in proportion to the input voltage.
Hysteresis -I _D characteristic is confirmed to be improved.

[0023]

[Table 1]

Table 1 shows a comparison between the conventional case in the S / H circuit and the distortion improvement effect according to the present invention. In the case of the embodiment of the present invention as compared with the conventional case, the frequency range is 10 (Hz).
At ~ 1 (kHz), a distortion improvement effect of 13 (dB) to 18 (dB) is observed.

In the above embodiment, the DC bias of the input signal is shifted by the operational amplifier circuit outside the GaAs substrate, but the DC bias of the voltage is shifted by the capacitor on the GaAs substrate.
The same effect can be obtained by cutting the components.

Although the silver paste is applied to the back surface of the GaAs substrate this time, a metal electrode may be deposited on the back surface of the GaAs substrate to apply a voltage.

(Embodiment 2) In this embodiment, GaAs
A silver paste was applied to the back of the s substrate to form a back electrode, and a voltage was applied to the back.

FIG. 4 shows an example in which the input voltage is branched and
This is an example in which the information is input on the back surface of the s substrate. The circuit configuration and circuit operation are exactly the same as in the first embodiment. In this case, the potential of the rear surface of the GaAs substrate is 0 (V), which is lower than that of the first embodiment.
The distortion is improved as compared with the case of.

[0029]

As described above, according to the present invention, by inputting a voltage proportional to an input signal to the back surface of a GaAs substrate,
The distortion in the low frequency region of the integrated circuit on the aAs substrate can be suppressed.

[Brief description of the drawings]

FIG. 1 shows an S / S using the GaAs MESFET of Example 1.
Block diagram of H integrated circuit

[2] V _DS -I _D static characteristic measurement circuit diagram of GaAsMESFET

Figure 3 (a) shows V _DS -I _D characteristic shows a view (b) in the GaAs substrate back surface 0 (V) center 5V _pp sinusoidal GaAsMESFET when formed into a zero GaAs substrate rear side potential (V) V _DS -I _D of GaAsMESFET at the time of applying
Diagram showing characteristics

FIG. 4 shows an S / S ratio using the GaAs MESFET of Example 2.
Block diagram of H integrated circuit

FIG. 5A shows GaAsME without a high-resistance buffer layer.
(B) GaAs MESFET without high resistance buffer layer
Shows the V _DS -I _D characteristic (c) is a high-resistance buffer layer GaAsMESFET
(D) is a GaAs MESFET having a high resistance buffer layer.
Shows the V _DS -I _D characteristic

FIG. 6 is a diagram showing a source follower circuit using an FET.

7 (a) is V _DS -I _D of the source follower circuit using the (b) shows FET showing the V _GS -I _D characteristic and the load curve of the source follower circuit using a FET
Diagram showing characteristics and load curve

FIG. 8 is a source follower circuit with small distortion using an FET.

[Explanation of symbols]

11 Analog signal input terminal (0 (V) to -2.0
(V)) 12 analog signal output terminals (0 (V) to -2.0
(V)) 13 clock input terminal (ECL level) 14a buffer 14b buffer 14c buffer 15 sampler 16 buffer 17 GaAs substrate 18 operational amplifier circuit 21 oscillator 22 amplifier 23 amplifier 24 GaAs substrate 25 operational amplifier circuit 26 oscilloscope Q21 GaAs MESFET 61 signal input terminal Output terminal 63 Power supply terminal Q61 FET R61 Resistance 81 Signal input terminal 82 Signal output terminal 83 Power supply terminal (positive) 84 Power supply terminal (negative) Q81 FET Q82 FET D81 Diode D82 Diode I81 Constant current source I82 Constant current source

(56) References JP-A-5-198746 (JP, A) (58) Fields investigated (Int. Cl. ⁷ , DB name) H03F 1/30-1/40 H03F 3/34-3 / 50 H01L 21/335-21/338

Claims (2)

(57) [Claims] An integrated circuit formed on a GaAs substrate, an electrode on a back surface of the GaAs substrate, and a voltage proportional to an input signal voltage of the integrated circuit on or outside the GaAs substrate. A circuit for applying a voltage to an electrode on the back surface of the GaAs substrate, wherein the distortion of the integrated circuit in a low frequency region is reduced. 2. The method according to claim 1, wherein an input signal is branched and input directly to an electrode on the back surface of the GaAs substrate without using a circuit for applying a voltage proportional to an input signal voltage of the integrated circuit to the back surface of the GaAs substrate. The compound semiconductor device according to claim 1.