JPH05336146A - Cell abort mis-delivery detector - Google Patents

Abstract

PURPOSE:To output a dummy cell to an output line in a correct timing for cell abort compensation. CONSTITUTION:The detector consists of a pre-stage buffering circuit 106 receiving a cell from an input line 101, a post stage buffering circuit 107 for a cell from the pre-stage, a cell counter 122 counted up every buffering by the pre- stage circuit 106, a cell abort detection circuit 124 in the post-stage circuit 107 and a dummy cell transmission circuit 126 outputting a dummy cell. When the SN of each cell in the pre-stage circuit 106 and the post-stage circuit 107 is not equal to a count by the cell counter 122 or a value incremented by one from the count at a point of time of buffering by the pre-stage circuit 106, the cell abort detection circuit 124 discriminates the occurrence of cell abort as the detection of discontinuity of the SN of each cell and outputs the SN or the count difference which is smaller to an output line 102 by using the dummy cell transmission circuit 126 and the post-stage circuit 107 outputs the cell to the output line 102.

Description

Detailed Description of the Invention

[0001]

BACKGROUND OF THE INVENTION 1. Field of the Invention The present invention relates to a cell discard / mis-delivery detecting device for detecting information loss due to cell discard and erroneous information insertion due to erroneous cell distribution and performing dummy information insertion and erroneous information removal processing.

[0002]

2. Description of the Related Art In recent years, there has been a demand for a technique for correcting an erroneous information signal by improving a technique for transmitting a digital information signal by wire.

A conventional cell discard / mis-delivery detection device will be described below with reference to the drawings. As shown in FIG. 5, in the conventional cell discard / mis-delivery detection device, a signal is input to an input interface circuit 503 through an input line 501, an input side buffer 504, an SN reading circuit 505, a pre-stage buffering circuit 506, The data is transmitted to the post-stage buffering circuit 507. A write cell 508 and a write signal 509 from the input interface circuit 503 to the input side buffer 504, an SN read circuit 505 to the input side buffer 5
04 read signal 510, input side buffer 504 to SN read circuit 505 and pre-stage buffering circuit 5
06, a read cell 511, an empty signal 512 from the input side buffer 504 to the SN read circuit 505,
SN read circuit 505 to pre-stage buffering circuit 5
06, write signal 513 to front stage buffering circuit 506, empty signal 514 from front stage buffering circuit 506 to SN read circuit 505, write signal 515 and write cell 516 from front stage buffering circuit 506 to rear stage buffering circuit 507, rear stage buffering circuit 507. Empty signal 517, S from the first-stage buffering circuit 506 to
The SN output signal 518 of the N read circuit 505, the cell reception signal 519, and the initial state notification signal 520 are output.

Further, it has an SN storage circuit 521, a cell counter 522, an erroneously distributed cell detection circuit 523, a cell discard detection circuit 524, a normal cell detection circuit 525, and a dummy cell transmission circuit 526, and the SN storage circuit 521 outputs a stored SN output. The signal 527 outputs the count value output signal 528 from the cell counter 522, the count value setting signal 529 inputs to the cell counter 522, and the mis-distributed cell detection circuit 523.
And the cell discard detection circuit 524 uses the count value setting signal 52
9 is wired or connected. From the mis-distributed cell detection circuit 523 to the subsequent buffering circuit 507,
The 1-cell removal signal 530 is input. A cell read signal 531 to the subsequent buffering circuit 507, a dummy cell output number notification signal 532 from the cell discard detection circuit 524 to the dummy cell transmission circuit 526, and a dummy cell output signal 533 from the dummy cell transmission circuit 526 to the output line 502 are output. Cell discard detection circuit 524 and normal cell detection circuit 525
Are connected to the cell read signal 531 by wired OR.

SN storage circuit 521, cell counter 52
2. Mis-distributed cell detection circuit 523, cell discard detection circuit 524
The SN output signal 518 and the cell reception signal 519 are input to the normal cell detection circuit 525. Cell counter 5
22, misdelivery cell detection circuit 523, cell discard detection circuit 52
4 and the normal cell detection circuit 525.
0 is entered. The count value output signal 528 is input to the mis-distributed cell detection circuit 523, the cell discard detection circuit 524, and the normal cell detection circuit 525. The accumulated SN output signal 527 is input to the cell discard detection circuit 524.

Next, as shown in FIG. 6, the cell discard detection circuit 524 is composed of an SN continuous detection circuit 601, an SN-cell count value difference output circuit 602, and an output control circuit 603, and outputs from the SN continuous detection circuit 601. Control circuit 603
The SN continuous detection signal 604 is input to the output control circuit 603, and the difference output signal 605 is input from the SN-cell count value difference output circuit 602 to the output control circuit 603. SN continuous detection circuit 601 and SN
The SN output signal 518, the accumulated SN value output signal 527, and the count value output signal 528 are input to the cell count value difference output circuit 602. The cell reception signal 519 and the initial state notification signal 520 are input to the output control circuit 603. The output control circuit 603 outputs a count value setting signal 529, a cell read signal 531 and a dummy cell output number notification signal 532.

Next, as shown in FIG. 7, the format of the cell is composed of a data section 71 and a header section 72. The header section 72 has a field 73 indicating whether the cell is valid or invalid and an SN indicating the order between the cells. (Sequence number)
And a field 75 in which a channel identification number is described.

Next, as shown in FIG. 8, the timing diagram of the signals on the read cell 511 and the output line 502 shows a signal 81 indicating a cell break, and signal examples 82 and 85 on the read cell 511. Each cell is a pre-stage buffering circuit 50
Cell counter 522 when buffered to 6
Are shown by count values 83 and 86, and signal examples 84 and 87 on the output line 502. A signal 85 is the result of performing cell discard compensation and erroneous cell removal on the signal 82, and a signal 87 is the result of performing cell discard compensation and erroneous cell removal on the signal 83.

[0009] The conventional cell discard /
The operation of the misdelivery detection device will be described below.

First, as shown in FIG. 7, an SN (sequence number) indicating the order between cells is described in the field 74 of the header portion 72 of each cell input from the input line. The value of 1 to 16 is cyclically used for SN. When cell discard occurs, S between cells
When N misses occur and cell misdelivery occurs, cells with SNs that are not continuous with the SNs of the preceding and following cells are mixed in. Therefore, cell SNs should be checked to detect cell discard and cell misdelivery. You can Taking the signal 82 shown in FIG. 8 as an example, the cell of SN = 10 is a mis-distributed cell, and the cell of SN = 4 between the cell of SN = 3 and the cell of SN = 5 is discarded. I understand. Here, first, the following assumptions are made as a premise.

Since the probability of occurrence of erroneous cell distributions is sufficiently small, it is assumed that erroneous cell distributions are not continuously input from the input line.

Next, the probability that a large amount of cells are discarded is small, and therefore the mis-distributed cells are not considered to be normal cells in which cells are discarded between the cells before and after.

As an example, S in signal 82 of FIG.
In cells with N = 1, SN = 10 and SN = 2, SN =
Considering that 8 cells are discarded between the cell of 1 and the cell of SN = 10 and 7 cells are discarded between the cell of SN = 10 and the cell of SN = 2, It is assumed that the cell with SN = 10 is a mis-distributed cell.

Further, the operation of the above configuration will be described by dividing it into the following two parts with reference to FIGS. 5, 6 and 8. The first operation is a part until the cell input from the input line 501 is buffered in the input side buffer 504 through the input interface circuit 503. The second operation is
A cell is read from the input side buffer 504, and a front stage buffering circuit 506 and a rear stage buffering circuit 507 are read.
This is the operation of the part from the buffering to the output line 502.

Here, the first operation will be described with reference to FIG. The cell is input to the input interface circuit 503 from the input line 501, and the input interface circuit 503 receives the cell.
Determines from the cell field 73 whether the input cell is a valid cell or an invalid cell. If the cell is a valid cell, the write signal 509 is activated and the write cell 50 is activated.
8 to the input side buffer 504. The input side buffer 504 activates the empty signal 512 when no cell is buffered.

Next, the overall operation as the second operation will be described with reference to FIG. Also, the cell discard detection circuit 5
The internal operation of 24 will be described with reference to FIG.

The SN read circuit 505 reads the read signal 5 when the empty signal 512 from the input side buffer 504 is inactive and the empty signal 514 from the preceding buffering circuit 506 is active.
10 is activated to read the cell from the input side buffer 504, and the write signal 513 is activated to read the cell through the read cell 511.
Buffer cells to 6. Read out cell 5 at the same time
The SN of the cell is read from 11 and output as the SN output signal 518, and the cell reception signal 519 is activated.
Further, when the cell is read from the input side buffer 504 for the first time, the initial state notification signal 520 is activated,
When reading from the second cell onward, the initial state notification signal 5
Inactivate 20.

The pre-stage buffering circuit 506 buffers up to one cell. The pre-stage buffering circuit 506 is buffering cells, and further, the empty signal 51 from the post-stage buffering circuit 507.
When 7 is active, the write signal 515 is activated and the cell is buffered in the subsequent buffering circuit 507 through the write cell 516. When the cell is not buffered, the empty signal 514 to the SN read circuit 505 is activated.

The cell counter 522 sets the SN indicated by the SN output signal 518 as the initial value of the count value when the initial state notification signal 520 is active, and the cell reception signal 519 when the initial state notification signal 520 is inactive. Is activated, that is, each time a cell is newly buffered in the pre-stage buffering circuit 506, the counter is incremented by one.

The SN storage circuit 521 is for receiving the cell reception signal 51.
9 is activated, that is, every time a cell is newly buffered in the front-stage buffering circuit 506, the SN of the cell currently buffered in the rear-stage buffering circuit 507 is output as the accumulated SN output signal 527. To do.

The mis-distributed cell detection circuit 523 does not perform the detection operation when the initial state notification signal 520 is active. Whenever the initial state notification signal 520 becomes inactive and the cell reception signal 519 becomes active, the input S
Based on the N output signal 518, the accumulated SN output signal 527 and the count value output signal 528 of the cell counter 522, it is detected whether or not the cell buffered in the subsequent buffering circuit 507 is a mis-distributed cell.

The detection method is as follows. Based on the input SN output signal 518 and the count value output signal 528, when the count value of the cell counter 522 is 1 larger than the SN of the cell buffered in the pre-stage buffering circuit 506, the post-stage buffering circuit 50
The cell buffered in 7 is a mis-distributed cell.
The signal 82 shown in FIG. 8 will be described as an example. When the cell of SN = 2 is buffered in the pre-stage buffering circuit 506 and the cell of SN = 10 is buffered in the post-stage buffering circuit 507, the SN of the cell in the pre-stage buffering circuit 506 is 2. On the other hand,
The corresponding value of the count value 83 is 3. Therefore, since the count value is 1 larger than SN, the cell in the post-stage buffering circuit 507, that is, the cell with SN = 10 is a mis-distributed cell. The signal 84 is a result of the removal of the mis-distributed cell with respect to the signal 82.

When the mis-distributed cell detection circuit 523 detects the mis-distributed cell, the one-cell removal signal 530 to the subsequent buffering circuit 507 is activated. Subsequently, the count value setting signal 529 to the cell counter 522 decrements the count value of the cell counter 522 by one,
The value is made equal to the SN of the cell buffered in the pre-stage buffering circuit 506. Signal 82 shown in FIG.
Then, the value corresponding to the cell of SN = 2 of the count value 83 is set from 3 to 2.

The cell discard detection circuit 524 does not operate when the initial state notification signal 520 is active. Each time the initial state notification signal 520 becomes inactive and the cell reception signal 519 becomes active, the input SN output signal 518, accumulated SN output signal 527, and cell counter 5 are input.
It is detected based on the count value output signal 528 of 22 that whether or not cell discard has occurred before the cell buffered in the subsequent buffering circuit 507.

Next, the cell discard detection method of the cell discard detection circuit 524 will be described with reference to FIG. The SN consecutive detection circuit 601 detects the SN of the cell buffered in the preceding buffering circuit 506 indicated by the SN output signal 518.
Based on the count value indicated by the count value output signal 528, it is checked whether SN is equal to the count value or a value obtained by subtracting 1 from the count value. If they are not equal, this time, the SN of the cell buffered in the rear buffering circuit 507 indicated by the accumulated SN output signal 527 and the SN of the cell buffered in the front buffering circuit 506 are compared, and both are consecutive. That is, the value obtained by adding 1 to the SN of the cell in the post-stage buffering circuit 507 is the S of the cell in the pre-stage buffering circuit 506.
Check if equal to N. When both are continuous, the SN continuous detection signal 604 is activated.

SN-cell count value difference output circuit 602
Outputs a value obtained by subtracting SN from the count value as the difference output signal 605 based on the SN of the cell buffered in the preceding buffering circuit 506 indicated by the SN output signal 518 and the count value indicated by the count value output signal 528. To do.

The output control circuit 603 controls the cell reception signal 51.
The SN continuous detection signal 604 is checked each time 9 becomes active. Cell discard occurs when the SN continuous detection signal 604 is active.

When the SN continuity detection signal 604 is active, the differential output signal 605 is output as it is to the dummy cell output circuit 526 as the dummy cell output number notification signal 532, and the dummy cell output circuit 526 outputs the number of signals indicated by the dummy cell output number notification signal 532. After outputting the dummy cell, the cell read signal 531 is activated. Further, the count value setting signal 529 to the cell counter 522 increments the count value by the number indicated by the dummy cell output number notification signal 532, so that the SN of the cells buffered in the pre-stage buffering circuit 506 is equal to the count value. Let When the SN consecutive detection signal 604 is inactive, the cell read signal 531 is made inactive, and 0 is output to the dummy cell output number notification signal 532. On the other hand, when the cell reception signal 519 is inactive, the cell read signal 53 is irrespective of the input signal.
1 is made inactive, and dummy cell output number notification signal 5
0 is output to 32.

The signal 82 shown in FIG. 8 will be described as an example.
The cell of SN = 6 is buffered in the front stage buffering circuit 506, and the rear stage buffering circuit 507
The cell with SN = 5 is buffered. At this time, the SN of the cell in the pre-stage buffering circuit 506 is 6
However, the count value of the cell counter 522 is 5
Therefore, SN is not equal to the count value or the value obtained by subtracting 1 from the count value. Further, the SNs of both cells are consecutive 6,5. Therefore, cell discard occurs before the cell in the latter-stage buffering circuit 507, that is, the cell with SN = 5, and the discarded cell is SN.
= 4 cells. The signal 84 is the result of cell discard compensation for the signal 82 by inserting a dummy cell.

The dummy cell output circuit 526 outputs the number of dummy cells indicated by the dummy cell output number notification signal 532 to the output line 502 through the dummy cell output signal 533. When the value of the dummy cell output number notification signal 532 is 0, no operation is performed.

The normal cell detection circuit 525 detects the cell read signal 531 when the cell buffered in the subsequent buffering circuit 507 is not an erroneously distributed cell and cell discard has not occurred before the cell. To activate.

The post-stage buffering circuit 507 removes the buffering cell when the 1-cell removal signal 530 is active, and outputs the buffering cell to the output line 502 when the cell read signal 531 is active. To do. When not buffering cells,
Empty signal 51 to the pre-stage buffering circuit 506
Activate 7

The pre-stage buffering circuit 506 buffers cells, and the post-stage buffering circuit 507.
When the empty signal 517 from is active,
The pre-stage buffering circuit 506 buffers the cells in the post-stage buffering circuit 507 and activates the empty signal 514 to the SN read circuit 505. The SN read circuit 505 outputs the empty signal 514.
Is active and the empty signal 512 from the input side buffer 504 is inactive, the cell is read from the input side buffer 504, and the above-described operation is repeated.

As described above, even in the above-described conventional cell discard / mis-delivery detection device, when the cell discard is detected, the SN of the cell buffered in the subsequent buffering circuit 507 is detected.
And a value indicated by the count value output signal 528 of the cell counter 522, dummy cells are inserted, and when a mis-distributed cell is detected, the cell buffered in the post-stage buffering circuit 507 is removed. A cell can be transferred from the input line 501 to the output line 502 without causing cell omission and cell mixture due to cell misdelivery.

[0035]

However, in the above-mentioned conventional configuration, the SN of the cell in the pre-stage buffering circuit and the count value of the cell counter are not equal, and the SN of the cell in the pre-stage buffering circuit and the count value are 1 If the value obtained by subtracting is not equal and the SNs of the cells in the front-stage buffering circuit and the cells in the rear-stage buffering circuit are continuous, cell discard occurs before the cell in the rear-stage buffering circuit. To judge. Then, after the number of dummy cells necessary for discard compensation is output to the output line, the latter-stage buffering circuit outputs the cells to the output line.

Now, the cells in the front-stage buffering circuit are mis-distributed cells, and cell discard occurs before the cells in the rear-stage buffering circuit, and the cells in the rear-stage buffering circuit and the front-stage buffer. Two cases will be considered in which cell discard occurs with the cell in the ring circuit and cell discard occurs before the cell in the subsequent buffering circuit. In both cases, the SNs of both cells buffered by the front-stage buffering circuit and the rear-stage buffering circuit are not continuous. Therefore, the conventional cell discard detection method cannot detect the cell discard in the cases of both cases, and after that, when the SNs of the cells in the pre-stage buffering circuit and the cells in the post-stage buffering circuit are continuous. For the first time, the occurrence of cell discard can be detected.

As described above, the occurrence of cell discard before the cell in the latter-stage buffering circuit may be detected with a time delay, so that the dummy cell is inserted at the timing to be inserted before the cell. However, there is a problem that the timing of outputting the cell to the output line is deviated.

The present invention solves the above-mentioned problems of the prior art by compensating for cell discard and eliminating mis-distributed cells without shifting the timing of outputting each cell to the output line.
It is an object to provide an erroneous distribution detection device.

[0039]

In order to achieve the above object, the cell discard / mis-delivery detection device of the present invention is provided with a discontinuity of SN of each cell buffered in a pre-stage buffering circuit and a post-stage buffering circuit. And a difference between the SN of the cell buffered in the preceding buffering circuit and the count value output from the cell counter at the time when the cell is buffered in the preceding buffering circuit. , The difference between the SN of the cell buffered in the post-stage buffering circuit and the count value output from the cell counter at the time when the cell is buffered in the pre-stage buffering circuit, and the smaller value is output. SN-cell count value difference minimum value output means is provided to prevent cell discard when SN discontinuity is detected. It has been determined that the SN-cell count value difference minimum value output means outputs the number of dummy cells to the output line, and then the subsequent buffering circuit outputs the cells to the output line. There is.

[0040]

According to the present invention, in the above structure, when the SN discontinuity detecting means detects that the SNs of the cells buffered in the rear buffering circuit and the front buffering circuit are discontinuous, cell discard occurs. Then, the dummy cells of the number output by the SN-cell count difference minimum value output means are first output to the output line, and then the cells are output to the output line from the subsequent buffering circuit. It is possible to perform cell discard compensation and erroneous cell distribution removal without shifting the output timing.

[0041]

DETAILED DESCRIPTION OF THE PREFERRED EMBODIMENTS An embodiment of the present invention will be described below with reference to the drawings.

As shown in FIG. 1, in the cell discard / mis-delivery detection device of this embodiment, the signal input through the input line 101 is
Input interface circuit 103, input side buffer 10
4, output from the output line 102 through the SN reading circuit 105, the pre-stage buffering circuit 106, and the post-stage buffering circuit 107. Here, from the input interface circuit 103 to the input side buffer 104, the write cell 1
08 and the write signal 109 are input, and the read signal 11 from the SN read circuit 105 to the input side buffer 104.
Enter 0. A read cell 111 from the input side buffer 104 to the SN read circuit 105 and the pre-stage buffering circuit 106, an empty signal 112 from the input side buffer 104 to the SN read circuit 105, and a pre-stage buffering circuit 106 from the SN read circuit 105. Write signal 113 to the front stage buffering circuit 106 to SN
Empty signal 114 to read circuit 105, front-stage buffering circuit 106 to rear-stage buffering circuit 1
The write signal 115 to the 07 and the write cell 116, the empty signal 117 from the post-stage buffering circuit 107 to the pre-stage buffering circuit 106, the SN output signal 118 of the SN read circuit 105, the cell reception signal 119 and the initial state notification signal 120. Output each.

Further, it has an SN storage circuit 121, a cell counter 122, an erroneously distributed cell detection circuit 123, a cell discard detection circuit 124, a normal cell detection circuit 125, and a dummy cell transmission circuit 126, and outputs an accumulated SN output from the SN storage circuit 121. The signal 127 outputs the count value output signal 128 from the cell counter 122, the count value setting signal 129 inputs to the cell counter 122, and the mis-distributed cell detection circuit 123.
And the cell discard detection circuit 124 displays the count value setting signal 12
9 is wired or connected. From the mis-distributed cell detection circuit 123 to the subsequent buffering circuit 107,
The 1-cell removal signal 130 is input. A cell read signal 131 to the subsequent buffering circuit 107, a dummy cell output number notification signal 132 from the cell discard detection circuit 124 to the dummy cell transmission circuit 126, and a dummy cell output signal 133 to the output line 102 from the dummy cell transmission circuit 126 are output. Cell discard detection circuit 124 and normal cell detection circuit 125
Are connected to the cell read signal 131 in a wired or connection.

SN storage circuit 121, cell counter 12
2. Mis-distributed cell detection circuit 123, cell discard detection circuit 124
The SN output signal 118 and the cell reception signal 119 are input to the normal cell detection circuit 125. Cell counter 1
22, misdelivery cell detection circuit 123, cell discard detection circuit 12
4 and the normal cell detection circuit 125
0 is entered. The count value output signal 128 is input to the mis-distributed cell detection circuit 123, the cell discard detection circuit 124, and the normal cell detection circuit 125. The accumulated SN output signal 127 is input to the cell discard detection circuit 124.

Next, as shown in FIG. 2, the cell discard detection circuit 124 includes an SN consecutive detection circuit 201, an SN-cell count value difference output circuit 202, and an SN discontinuity detection circuit 20.
3, SN-cell count value difference minimum value output circuit 204,
The output control circuit 205 includes the SN continuous detection circuit 20.
1 to the output control circuit 205, the SN continuous detection signal 20
6. The difference output signal 207 is input from the SN-cell count value difference output circuit 202 to the output control circuit 205. S
S from the N discontinuity detection circuit 203 to the output control circuit 205
The N discontinuity detection signal 208 and the SN-cell count value difference minimum value output circuit 204 output a difference minimum value output signal 209 to the output control circuit 205. SN continuous detection circuit 2
01 and SN-cell count value difference output circuit 202 and SN
The discontinuity detection circuit 203 and the SN-cell count value difference minimum value output circuit 204 have an SN output signal 118 and an accumulated SN.
The output signal 127 and the count value output signal 128 are input. The cell control signal 119 is sent to the output control circuit 205.
And the initial state notification signal 120 is input. The output control circuit 205 outputs a count value setting signal 129, a cell read signal 131, and a dummy cell output number notification signal 132.

Next, as shown in FIG. 3, the cell format is made up of a data section 31 and a header section 32. The header section 32 has a field 33 indicating whether the cell is valid or invalid and an SN indicating the order between the cells. (Sequence number)
And a field 35 in which a channel identification number is described.

Next, as shown in FIG. 4, the timing diagram of the signals on the read cell 111 and the output line 102 shows a signal 41 indicating a cell break, and signal examples 42 and 45 on the read cell 111. Each cell is a pre-stage buffering circuit 10
Cell counter 122 when buffered to 6
Count values 43 and 46 of the No. 4, signal example 4 on the output line 102
4, 47. The signal 42 corresponds to the signal 42, and the signal 47 corresponds to the signal 45.

The operation of the cell discard / mis-delivery detecting device configured as described above will be described below. First, the following two parts will be described with reference to FIGS. 1, 2, and 4. The first operation is a part until the cell input from the input line 101 is buffered in the input side buffer 104 through the input interface circuit 103. The second operation is a part of the operation in which cells are read from the input side buffer 104, buffered in the front stage buffering circuit 106 and the rear stage buffering circuit 107, and output to the output line 102.

The first operation will be described with reference to FIG. Cell from input line 101 is input interface circuit 1
03, and the input interface circuit 103 judges from the cell field 33 whether the input cell is a valid cell or an invalid cell. If the cell is a valid cell, the write signal 109 is activated and buffered in the input side buffer 104 through the write cell 108. The input side buffer 104 activates the empty signal 112 when no cell is buffered.

Next, as a second operation, the overall operation will be described with reference to FIG. The internal operation of the cell discard detection circuit 124 will be described with reference to FIG.

The SN read circuit 105 reads the read signal 1 when the empty signal 112 from the input side buffer 104 is inactive and the empty signal 114 from the preceding buffering circuit 106 is active.
10 is activated to read the cell from the input side buffer 104, and the write signal 113 is activated to read the cell 111 through the read cell 111.
Buffer cells to 6. Read out cell 1 at the same time
The SN of the cell is read from 11 and output as the SN output signal 118, and the cell reception signal 119 is activated.
When the cell is read from the input side buffer 104 for the first time, the initial state notification signal 120 is activated,
Initial state notification signal 1 when reading from the second cell onward
Inactivate 20.

The pre-stage buffering circuit 106 buffers up to one cell. The pre-stage buffering circuit 106 buffers cells, and further, the empty signal 11 from the post-stage buffering circuit 107.
When 7 is active, the write signal 115 is activated to buffer the cell through the write cell 116 in the post-stage buffering circuit 107. When the cell is not buffered, the empty signal 114 to the SN read circuit 105 is activated.

The cell counter 122 receives the S of the SN output signal 118 when the initial state notification signal 120 is active.
When N is set as the initial value of the count value and the initial state notification signal 120 is inactive, the cell reception signal 1
The counter is incremented by 1 each time 19 is activated, that is, each time a cell is newly buffered in the pre-stage buffering circuit 106.

The SN storage circuit 121 receives the cell reception signal 11
9 is activated, that is, every time a cell is newly buffered in the front-stage buffering circuit 106, the SN of the cell currently buffered in the rear-stage buffering circuit 107 is output as the accumulated SN output signal 127. To do.

The mis-distributed cell detection circuit 123 does not perform the detection operation when the initial state notification signal 120 is active. Whenever the initial state notification signal 120 becomes inactive and the cell reception signal 119 becomes active, the input S
Based on the N output signal 118, the accumulated SN output signal 127, and the count value output signal 128 of the cell counter 122, it is detected whether the cell buffered in the post-stage buffering circuit 107 is a mis-distributed cell.

The detection method is as follows. Based on the input SN output signal 118 and the count value output signal 128, when the count value of the cell counter 122 is 1 larger than the SN of the cell buffered in the pre-stage buffering circuit 106, the post-stage buffering circuit 10
It is detected that the cell buffered in 7 is a mis-distributed cell. The signal 42 shown in FIG. 4 will be described as an example. The cell of SN = 2 is buffered in the front stage buffering circuit 106, and the rear stage buffering circuit 10
When the cell with SN = 10 is buffered in 7, the SN of the cell in the previous stage buffering circuit 106 is 2
However, the corresponding value of the count value 43 is 3. Therefore, since the count value is 1 larger than SN, the cell in the post-stage buffering circuit 107, that is, the cell with SN = 10 is a mis-distributed cell. Signal 44 is signal 4
This is the result of removing the mis-distributed cells for No. 2.

When the mis-distributed cell detection circuit 123 detects a mis-distributed cell, the one-cell removal signal 130 to the subsequent buffering circuit 107 is activated. Then, by the count value setting signal 129 to the cell counter 122, the count value of the cell counter 122 is decreased by one,
The value is set to be equal to the SN of the cell buffered in the pre-stage buffering circuit 106. Signal 42 shown in FIG.
Then, the value corresponding to the cell of SN = 2 of the count value 43 is set from 3 to 2.

The cell discard detection circuit 124 does not operate when the initial state notification signal 120 is active. Each time the initial state notification signal 120 becomes inactive and the cell reception signal 119 becomes active, the input SN output signal 118, accumulated SN output signal 127, and cell counter 1 are input.
It is detected based on the count value output signal 128 of 22 whether or not cell discard has occurred in front of the cell buffered in the subsequent buffering circuit 107.

Next, the cell discard detection method of the cell discard detection circuit 124 will be described with reference to FIG. The SN continuous detection circuit 201 detects the SN of the cells buffered in the preceding buffering circuit 106 indicated by the SN output signal 118.
Based on the count value indicated by the count value output signal 128, it is checked whether SN is equal to the count value or a value obtained by subtracting 1 from the count value. If they are not equal, this time, the SN of the cell buffered in the subsequent buffering circuit 107 indicated by the accumulated SN output signal 127 and the SN of the cell buffered in the previous buffering circuit 106 are compared, and both are consecutive. That is, the value obtained by adding 1 to the SN of the cell in the post-stage buffering circuit 107 is the S of the cell in the pre-stage buffering circuit 106.
Check if equal to N. When both are continuous, the SN continuous detection signal 206 is activated.

SN-cell count value difference output circuit 202
Based on the SN of the cell buffered in the pre-stage buffering circuit 106 indicated by the SN output signal 118 and the count value indicated by the count value output signal 128, a value obtained by subtracting SN from the count value is output as the difference output signal 207. To do.

The SN discontinuity detection circuit 203 detects the SN of the cells buffered in the preceding buffering circuit 106 indicated by the SN output signal 118 and the accumulated SN output signal 12.
7 based on the SN of the cell buffered in the post-stage buffering circuit 107 and the count value of the cell counter 122 indicated by the count value output signal 128, the SN of the cell buffered in the pre-stage buffering circuit 106. Is equal to the count value or a value obtained by subtracting 1 from the count value, and the SN of the cell buffered in the subsequent buffering circuit 107 and the value obtained by subtracting 1 from the count value or the value obtained by subtracting 2 from the count value are Check if they are equal. If they are not equal, the SN of the cell buffered by the subsequent buffering circuit 107 indicated by the accumulated SN output signal 127 and the SN of the cell buffered by the preceding buffering circuit 106 indicated by the SN output signal 118. And whether or not they are continuous, that is, the value obtained by adding 1 to the SN of the cell buffered in the post-stage buffering circuit 107 is equal to the SN of the cell buffered in the pre-stage buffering circuit 106. To see if If both are discontinuous, SN
The discontinuity detection signal 208 is activated.

The SN-cell count value difference minimum value output circuit 204 outputs the SN of the cell buffered in the front stage buffering circuit 106 indicated by the SN output signal 118 and the rear stage buffering circuit 107 indicated by the accumulated SN output signal 127. Based on the SN of the cell being buffered and the count value of the cell counter 122 indicated by the count value output signal 128, the value obtained by subtracting the count value from the SN of the cell buffered in the pre-stage buffering circuit 106 and the post-stage buffer The smallest value among the values obtained by subtracting 1 from the SN of the cells buffered in the ring circuit 107 and adding 1 to the difference minimum output signal 20
Output as 9.

The output control circuit 205 outputs the cell reception signal 11
Each time 9 is activated, the SN continuous detection signal 206 and the SN discontinuous detection signal 208 are examined. Cell loss occurs when either of the two is active. First, when the SN continuous detection signal 206 is more active, the differential output signal 207 is directly output to the dummy cell output circuit 126 as the dummy cell output number notification signal 132, and the dummy cell output circuit 126 outputs the number indicated by the dummy cell output number notification signal 132. After outputting the dummy cell of, the cell read signal 131 is activated. Further, the count value is incremented by the counter value setting signal 129 to the cell counter 122 by the number indicated by the dummy cell output number notification signal 132, and the SN of the cells buffered in the pre-stage buffering circuit 106 is made equal to the count value. Let Next, the SN discontinuity detection signal 20
8 is active, the differential minimum output signal 20
9 is directly output to the dummy cell output circuit 126 as the dummy cell output number notification signal 132, and after the dummy cell output circuit 126 outputs the number of dummy cells indicated by the dummy cell output number notification signal 132, the cell read signal 131 is activated. Further, the count value is incremented by the counter value setting signal 129 to the cell counter 122 by the number indicated by the dummy cell output number notification signal 132, and the SN of the cells buffered in the pre-stage buffering circuit 106 is made equal to the count value. Let

When both the SN continuous detection signal 206 and the SN discontinuous detection signal 208 are inactive, the cell read signal 131 is made inactive and 0 is output to the dummy cell output number notification signal 132. On the other hand, when the cell reception signal 119 is inactive, the cell reading signal 131 is made inactive regardless of the input signal,
0 is output to the dummy cell output number notification signal 132.

The above-mentioned cell loss detection method will be described by taking the signal 45 shown in FIG. 4 as an example. The cell of SN = 5 is buffered in the front stage buffering circuit 106, and the cell of SN = 3 is buffered in the rear stage buffering circuit 107. At this time, the SN of the cell in the front-stage buffering circuit 106 is 5, whereas the corresponding value of the count value 46 is 3, and the SN of the cell in the rear-stage buffering circuit 107 is 3. On the other hand, since the corresponding value of the count value 46 is 2, neither SN is equal to the corresponding count value or the value obtained by subtracting 1 from the count value. Furthermore, both SNs
Is not continuous with 5,3. Therefore, cell discard occurs before the cell in the subsequent buffering circuit 107, that is, the cell with SN = 3, and the discarded cell is the cell with SN = 2. The number of dummy cells to be output is the smaller of the differences between the count values corresponding to both SNs, and is 1 here. The signal 47 is a result of the cell discard compensation for the signal 45 by inserting a dummy cell.

The dummy cell transmission circuit 126 outputs the number of dummy cells indicated by the dummy cell output number notification signal 132 to the output line 102 through the dummy cell output signal 133. If the value of the dummy cell output number notification signal 132 is 0, no operation is performed.

The normal cell detection circuit 125 outputs the cell read signal 131 when the cell buffered in the post-stage buffering circuit 107 is not a mis-distributed cell and cell discard has not occurred before the cell. To activate.

The post-stage buffering circuit 107 removes the buffering cell when the 1-cell removal signal 130 is active, and outputs the buffering cell to the output line 102 when the cell read signal 131 is active. To do. When not buffering cells,
Empty signal 11 to the pre-stage buffering circuit 106
Activate 7

The former-stage buffering circuit 106 buffers cells, and the latter-stage buffering circuit 107.
When the empty signal 117 from is active,
The pre-stage buffering circuit 106 buffers the cells in the post-stage buffering circuit 107 and activates the empty signal 114 to the SN reading circuit 105. The SN read circuit 105 outputs the empty signal 114.
Is active and the empty signal 112 from the input side buffer 104 is inactive, the cell is read from the input side buffer 104, and the above-described operation is repeated.

As described above, according to the above-described embodiment, when the SN discontinuity detection circuit 203 detects the SN discontinuity of the cells buffered in the pre-stage buffering circuit 106 and the post-stage buffering circuit 107, SN- It is possible to output dummy cells to the output line 102 by the number of minimum difference outputs 209 output by the cell count value minimum difference output circuit 204, and then output cells from the subsequent buffering circuit 107 to the output line 102. Output line 10
It is possible to perform cell discard compensation and erroneously distributed cell removal without shifting the timing of outputting to the second cell.

[0071]

As is apparent from the above embodiments, according to the present invention, the cell counter at the time when the SN of the cell buffered in the preceding buffering circuit is buffered in the preceding buffering circuit. Is not equal to either the value obtained by subtracting 1 or the value obtained by subtracting 2 from the output value of, and the SN of the cell buffered in the subsequent buffering circuit is at the time when the cell is buffered in the previous buffering circuit. When it is detected that the SN of both cells is discontinuous when the output value of the cell counter or the value obtained by subtracting 1 from the output value is not equal, the SN of the cell in the preceding buffering circuit and the cell counter of the cell counter are detected. The difference between the output value and the value obtained by subtracting 1 from the SN of the cell in the subsequent buffering circuit and the output value of the cell counter. The smaller number of dummy cells out of the difference is output to the output line, and then the cells are output to the output line from the subsequent buffering circuit, so cell discard compensation is performed without shifting the timing of outputting each cell to the output line. Excellent cell disposal that can remove mis-distributed cells
The misdelivery detection device can be realized.

[Brief description of drawings]

FIG. 1 is a block diagram of a cell discard / mis-delivery detection device according to an embodiment of the present invention.

FIG. 2 is a block diagram of a cell discard detection circuit in the same embodiment.

FIG. 3 is a data structure diagram showing a cell format.

FIG. 4 is a signal diagram for explaining a cell discard and misdelivery detection method according to the present invention.

FIG. 5: Block diagram of conventional cell discard / mis-delivery detection device

FIG. 6 is a block diagram of a cell discard detection circuit in the device.

FIG. 7 is a data structure diagram showing a cell format.

FIG. 8 is a signal diagram for explaining a conventional cell discard and misdistribution detection method.

[Explanation of symbols]

 101 input line 102 output line 104 input side buffer 105 SN read circuit 106 front stage buffering circuit 107 rear stage buffering circuit 118 SN output signal 121 SN storage circuit 122 cell counter 123 mis-distributed cell detection circuit 124 cell discard detection circuit 125 normal cell Detection circuit 126 Dummy cell transmission circuit 128 Count value output signal 203 SN Discontinuity detection circuit 204 SN-Cell count value difference minimum value output circuit

Claims (1)

[Claims] 1. A front-stage buffering means for buffering up to one cell input from an input line, a rear-stage buffering means for buffering up to one cell output from the front-stage buffering means, and the front-stage buffering. SN reading means for outputting the SN (sequence number) of the cell buffered to the means, SN output means for outputting the SN of the cell buffered to the latter-stage buffering means, and the preceding-stage buffering means Cell count value output means for counting up and outputting a count value each time a cell is newly buffered, and the SN of each cell buffered in the front-stage buffering means and the rear-stage buffering means. SN discontinuity detection means for detecting continuity,
The difference between the SN of the cell buffered in the pre-stage buffering means and the count value output from the cell count value output means at the time when the cell is buffered in the pre-stage buffering means and the post-stage buffering means. S of cells buffered in
SN-cell count value difference minimum value that obtains the difference between N and the count value output from the cell count value output means at the time when the cell is buffered in the preceding buffering means, and outputs the smaller value Output means and dummy cell output means for outputting the notified dummy cells to the output line, wherein the SN discontinuity detection means
The SN of the cell buffered in the pre-stage buffering means is the count value of the cell count value output means at the time when the cell is buffered in the pre-stage buffering means or a value obtained by subtracting 1 from the count value. The SN of the cell which is not equal to any of the cells and is buffered in the latter-stage buffering means is more than the count value or the count value of the cell count value output means at the time when the cell is buffered in the previous-stage buffering means. When it is detected that the SNs of both cells are discontinuous when none of the values obtained by subtracting 1 is detected, cell discard occurs before the cell buffered in the latter-stage buffering means. If the above determination is made, the SN-cell count value difference maximum is determined. By outputting the dummy cells of the number of values output from the value output means to the output line from the dummy cell output means, and then outputting the cells to the output line from the latter-stage buffering means, the cells are correct according to the order indicated by SN. A cell discard / mis-delivery detection device capable of outputting to the output line at the timing and outputting the required number of dummy cells for cell discard compensation to the output line at the correct timing.