JPH05335959A - Semiconductor integrated circuit device - Google Patents

Abstract

PURPOSE:To provide a semiconductor integrated circuit device capable of automatically adjusting an electronic device. CONSTITUTION:A semiconductor chip 1 is provided with plural D/A converter 2, a memory 3 and a transfer control circuit section 4. The memory 3 is provided with a storage area 3a storing digital data in at least one D/A converter 2 provided in the semiconductor chip 1 and a redundant storage area 3b storing digital data for D/A converters 6 provided in other semiconductor chip 5. The transfer control circuit section 4 transfers the digital data stored in the storage area 3a to the D/A converter 2 of the semiconductor chip 1 and the digital data stored in the redundant storage area 3b are transferred to the D/A converter 6 of the other semiconductor chip 5.

Description

Detailed Description of the Invention

[0001]

BACKGROUND OF THE INVENTION 1. Field of the Invention The present invention relates to a semiconductor device, and more particularly to a device for controlling an analog voltage output from each D / A converter by controlling a plurality of D / A converters.

In recent years, in electronic equipment, the number of adjustment points (voltage adjustment, time constant adjustment, etc.) on the circuit has increased with the increase in functionality, and it is necessary to adjust each adjustment point with high accuracy. Is becoming Further, in order to simplify the manufacturing process, it is required that the device itself automatically adjusts. Further, in order to reduce the size and cost of the electronic device, a simple and inexpensive adjusting device is required.

[0003]

2. Description of the Related Art Conventionally, as shown in FIG. 6, adjustment of a semiconductor integrated circuit requires a semi-fixed resistor R externally attached to an integrated circuit 61.
Was manually adjusted at the manufacturing stage by a human or an automatic machine. However, with the miniaturization of electronic devices, it has been necessary to reduce the space for externally attaching the semi-fixed resistor R. Also, in order to simplify the manufacturing process,
It has become necessary to omit adjustment work at the manufacturing stage.

Therefore, as shown in FIG. 7, it has been considered to use the ON resistance of the MOS transistor 62 instead of the semi-fixed resistance R. That is, the MOS transistor 62
Are manufactured in the integrated circuit 61 by the same process as the internal circuit 63. Then, the gate voltage of the MOS transistor 62 corresponding to the ON resistance is obtained by empirically finding the value of the ON resistance of the MOS transistor 62 necessary for adjusting the internal circuit 63. next,
Digital data obtained by A / D converting the gate voltage is converted into E
It is stored in the non-volatile memory 64 which is a P-ROM or an EEP-ROM. Then, during the operation of the integrated circuit 61, the digital data read from the non-volatile memory 64 is D / A converted by the D / A converter 65, and the analog voltage as the D / A converted value (the gate voltage obtained by the above experiment is ) Is applied to the gate of the MOS transistor 62. Then, the ON resistance of the MOS transistor 62 becomes the resistance value required for the adjustment of the internal circuit 63 obtained by the experiment. As a result, the internal circuit 63 is automatically adjusted.

[0005]

By the way, if the D / A converter 65 and the non-volatile memory 64 are incorporated in different integrated circuits, there arises a problem that miniaturization of electronic equipment is hindered. Therefore, as shown in FIG. 8, the D / A converter 6
5 and the non-volatile memory 64 may be replaced with a D / A converter 66 having the non-volatile memory 64 built therein.

However, the D / A converter 66 is more expensive than the D / A converter 65 alone because the nonvolatile memory 64 is built therein. Further, in recent years, the number of adjustment points has increased as the functionality of electronic devices has increased. Therefore, providing the D / A converter 66 at each adjustment location causes a problem of significantly increasing the cost.

The present invention has been made to solve the above problems, and an object thereof is to provide a simple and inexpensive semiconductor integrated circuit device capable of automatically adjusting an electronic device. is there.

[0008]

FIG. 1 illustrates the principle of the present invention. The semiconductor chip 1 is provided with a plurality of D / A converters 2, a memory 3, and a transfer control circuit unit 4. The memory 3 is provided with a storage area 3a in which digital data of at least one D / A converter 2 of the plurality of D / A converters 2 provided in the semiconductor chip 1 is stored. Further, the memory 3 is also provided with a redundant storage area 3b in which digital data for the D / A converter 6 provided in another semiconductor chip 5 is stored.

Further, the transfer control circuit section 4 transfers the digital data stored in the storage area 3a of the memory 3 to the D / A converter 2 provided in the semiconductor chip 1. Further, the transfer control circuit unit 4 includes a redundant storage area 3b of the memory 3.
The digital data stored in the memory is transferred to the D / A converter 6 provided in another semiconductor chip 5 via the data bus.

[0010]

According to the present invention, by the transfer control circuit unit 4,
The digital data stored in the redundant storage area 3b of the memory 3 is transferred to the D / A converter 6 provided in another semiconductor chip 5. Then, the D / A converter 6 outputs an analog voltage based on the digital data.

Therefore, it is not necessary to provide another semiconductor chip 5 with a memory for storing digital data input to the D / A converter 6 provided in its own chip.

[0012]

(First Embodiment) A first embodiment of the present invention will be described below with reference to FIGS.

As shown in FIG. 2, three semiconductor integrated circuits (semiconductor chips) 24 to 26 are provided in the electronic equipment, and each D / A converter group 21 to 23 has a different integrated circuit 24 to 26. 26. And
The D / A converter group 21 of the integrated circuit 24 becomes the master side, and the D / A converter groups 22 of the integrated circuits 25 and 26 are
23 is controlled as a slave side. That master side D
The / A converter group 21 is connected to the slave side D / A converter groups 22 and 23 via a data bus DB and control signal lines CS1 and CS2. Eight D / A converters 31 are provided in each of the D / A converter groups 21 to 23, and adjustment MOS transistors (not shown) provided in the internal circuits (not shown) of the integrated circuits 24 to 26 are provided. An analog voltage is applied to the gate (not shown).

FIG. 3 shows a master side D / A converter group 21.
The internal circuit of is shown. Master side D / A converter group 21
Is composed of eight D / A converters 31, an 11-bit shift register 32, a non-volatile memory 33, and a control circuit 34 as a transfer control circuit.

The slave side D / A converter group 22,
23 is composed of only eight D / A converters 31. The shift register 32 stores 11-bit serial data input from an external device (not shown) such as a microcomputer. The serial data is control data D11 to D8 including the upper 4-bit address data.
And lower-order 8-bit converter data D7 to D0.

The non-volatile memory 33 is composed of three storage areas 33a to 33c of 8 bits × 8 words. Then, the nonvolatile memory 33 stores the converter data D7 to D0 stored in the shift register 32 in the data bus DB.
Via each of the storage areas 33a to
It is stored in 33c.

The control circuit 34 controls the nonvolatile memory 33 and each D / A converter 31 in each D / A converter group 21-23 based on the control data D11-D8 stored in the shift register 32. ..

That is, the control circuit 34 uses the control data D11 to D8 to control the storage areas 33a to 33d.
One of the storage areas 33a to 33c is selected from among the storage areas 33a to 33c.
The converter data D7 to D0 stored in c are output to the data bus DB.

When the storage area 33a is selected,
Based on the control data D11 to D8, the control circuit 34 opens the input gate of any D / A converter 31 in the D / A converter group 21 and inputs the converter data D7 to D0 of the data bus DB. In addition, the storage area 3
When 3b is selected, the control circuit 34 determines the D / A converter group 2 based on the control data D11 to D8.
The input gate of any D / A converter 31 in 2 is opened to input converter data D7 to D0 of the data bus DB. Further, when the memory area 33c is selected, the control circuit 34 opens the input gate of any D / A converter 31 in the D / A converter group 23 based on the control data D11 to D8, and via the data bus DB. Input converter data D7 to D0.

Each D to which converter data D7 to D0 is input
The / A converter 31 uses the converter data D7 to D0.
The analog voltage obtained by D / A conversion is applied to the gate of each adjustment MOS transistor.

Next, the operation of this embodiment configured as described above will be described. First, the value of the on-resistance of each MOS transistor necessary for adjusting the internal circuits of the integrated circuits 24 to 26 is obtained by an experiment, and the gate voltage of each MOS transistor corresponding to the on-resistance is obtained. Then, each gate voltage is A / D converted with 8 bits to obtain converter data D7 to D0. Also, number each MOS transistor so that they can be distinguished, and assign each number to 4
A / D conversion is performed by bits to determine control data D11 to D8. Then, the corresponding control data D11 to D8 and the converter data D7 to D0 are combined to generate 11-bit serial data.

The external device temporarily stores the serial data in the shift register 32. Non-volatile memory 33
Reads the converter data D7 to D0 stored in the shift register 32 via the data bus DB and stores them in the respective storage areas 33a to 33c.

When the power of the electronic device is turned on, the control data D11 ...
Based on D8, the control circuit 34 determines that each storage area 33
a to 33c are selected in order, and their storage areas 33a to 33c are selected.
The converter data D7 to D0 stored in is output to the data bus DB.

First, when the memory area 33a is selected, the control circuit 34 opens the input gate of an arbitrary D / A converter 31 in the D / A converter group 21 based on the control data D11 to D8 to open the data bus. Input DB converter data D7 to D0.

D / with the converter data D7-D0 input
The A converter 31 applies an analog voltage obtained by D / A converting the converter data D7 to D0 to the gate of the adjusting MOS transistor. Then, the on-resistance of the MOS transistor becomes a resistance value required for adjusting the internal circuit of the integrated circuit 24 obtained by the experiment. As a result, the internal circuit of the integrated circuit 24 is optimally adjusted.

Next, when the storage area 33b is selected, the control circuit 34 opens the input gate of an arbitrary D / A converter 31 in the D / A converter group 22 based on the control data D11 to D8, and the data is written. Input the converter data D7 to D0 of the bus DB.

D / to which converter data D7 to D0 are input
The A converter 31 applies an analog voltage obtained by D / A converting the converter data D7 to D0 to the gate of the adjusting MOS transistor. Then, the on-resistance of the MOS transistor becomes a resistance value required for adjusting the internal circuit of the integrated circuit 25 obtained by the experiment. As a result, the internal circuit of the integrated circuit 25 is optimally adjusted.

When the storage area 33c is selected,
The internal circuit of the integrated circuit 26 is optimally adjusted by operating in the same manner as when the storage area 33b is selected. As described above, in this embodiment, the master side D / A converter group 21 having the non-volatile memory 33 built therein allows each slave side D / A converter group 2 not having the non-volatile memory built-in.
2 and 23 are controlled. When the power is turned on, the D / A converter groups 21 to 23 operate in sequence,
By appropriately adjusting the gate voltage of each MOS transistor for adjusting the internal circuit of each integrated circuit 24-26,
The internal circuits of each integrated circuit 24-26 can be adjusted automatically.

The unit price of the non-volatile memory is not so different even if the storage capacity is increased several times. That is, the non-volatile memory 33 is composed of three storage areas 33a to 33c, but the unit price does not change much even if it is composed of only one storage area 33a. In other words, in the nonvolatile memory 33, each slave side D /
The areas 33b and 33c in which the converter data D7 to D0 corresponding to the A converter groups 22 and 23 are stored are the areas in which the converter data D7 to D0 corresponding to the master side D / A converter group 21 are stored. It can be said that the remaining area, that is, the redundant storage area.

Therefore, the D having the nonvolatile memory 64 built-in
Compared to the conventional example in which the A / A converter 66 is provided for each MOS transistor, a total of 24 D / A in each D / A converter group 21 to 23 for one nonvolatile memory 33.
In the present embodiment in which the converter 31 is provided, the number of non-volatile memories can be reduced, so that the cost can be significantly reduced.

However, in this embodiment, the master side D / A
It is necessary to provide the shift register 32 and the control circuit 34 in the converter group 21, which increases the cost accordingly. However, since the cost reduction due to the reduction in the number of non-volatile memories is much larger, the cost of the entire device can be reduced.

(Second Embodiment) Next, a second embodiment of the present invention will be described with reference to FIGS. In this embodiment, the same components as those in the first embodiment are designated by the same reference numerals, and detailed description thereof will be omitted.

As shown in FIG. 4, three semiconductor integrated circuits (semiconductor chips) 41 to 43 are provided in the electronic equipment, and the master side D / A converter group 44 is integrated circuit 4.
1, the slave side D / A converter group 45 is integrated circuit 4
2. Microcomputer (hereinafter abbreviated as microcomputer)
46 are respectively incorporated in the integrated circuit 43.

Eight D / A converters are provided in each D / A converter group 44, 45, and each adjustment MOS provided in the internal circuit (not shown) of each integrated circuit 41, 42. An analog voltage is applied to the gate of a transistor (not shown).

Further, the clock CLK output from the microcomputer 46 is input to both D / A converter groups 44 and 45. Furthermore, an external control signal output from the microcomputer 46
CS, external digital data Da, and external load signal LD1
Is input to the master side D / A converter group 44. On the other hand, the external load signal LD2 output from the microcomputer 46 is input to the slave side D / A converter group 45.

FIG. 5 shows the master side D / A converter group 44.
The internal circuit of is shown. Master side D / A converter group 44
Includes eight D / A converters 31, a latch circuit 51, an address decoder 52, a shift register 32, a non-volatile memory 53, an address decoder 54, a memory control circuit 55, a control circuit 56, and internal buses 57-5.
It is composed of 9.

The shift register 32 inputs and stores the external digital data Da, which is 11-bit serial data output from the microcomputer 46. The external digital data Da is composed of control data D11 to D8 including upper 4-bit address data and lower 8-bit converter data D7 to D0. Then, the shift register 32
Whenever the clock CLK is output from the microcomputer 46,
The stored external digital data Da is shifted bit by bit and output as external digital data Db. Under the control of the control circuit 56, the shift register 32 reads the converter data D7 to D0 of the stored external digital data Da to the internal bus 57 and the control data D11 to D8 to the internal bus 58.

Under the control of the control circuit 56, the memory control circuit 55 outputs the converter data D7 to D0 read via the internal bus 57 to the non-volatile memory 53 and reads via the internal bus 58. The control data D11 to D8 are output to the address decoder 54. In addition, the memory control circuit 55 includes the control circuit 5
Under the control of No. 6, the converter data D7 to D0 output from the non-volatile memory 53 are read to the internal bus 57, and the control data D11 to D8 output from the address decoder 54 are read to the internal bus 58.

The non-volatile memory 53 is composed of two storage areas 53a and 53b of 8 bits × 8 words. The address decoder 54 is the address decoder of the non-volatile memory 53.

That is, the address decoder 54 controls the control data D1 input via the memory control circuit 55.
Based on 1 to D8, the converter data D7 to D0 input via the memory control circuit 55 are stored in the storage areas 53a and 53b of the nonvolatile memory 53. Further, the address decoder 54, based on the control data D11 to D8, stores the storage areas 53a and 53 in the nonvolatile memory 53.
The memory control circuit 55 is caused to output the converter data D7 to D0 stored in b.

The control circuit 56 controls the shift register 32 and the memory control circuit 55 based on the external control signal CS output from the microcomputer 46. The address decoder 52 reads the control data D11 to D8 via the internal bus 58 based on the external load signal LD1 output from the microcomputer 46. Then, the address decoder 52 selects each latch circuit 51 based on the read control data D11 to D8 and outputs the selection signal to each latch circuit 51 via the internal bus 59.

Each latch circuit 51 selected by the address decoder 52 reads and latches the converter data D7 to D0 via the internal bus 57. Then, each latch circuit 51 outputs the latched converter data D7 to D0 to the corresponding D / A converter 31.

On the other hand, slave side D / A converter group 45
The internal circuit of the master side D / A converter group 44 is
From the nonvolatile memory 53, the address decoder 54, the memory control circuit 55, the control circuit 56, and the internal bus 57.

That is, the slave side D / A converter group 45 includes eight D / A converters 31 and a latch circuit 51.
The address decoder 52, the shift register 32, and the internal buses 58 and 59.

However, the slave side D / A converter group 45
The shift register 32 of 1 inputs and stores the external digital data Db output from the shift register 32 of the master side D / A converter group 44.

Further, the slave side D / A converter group 45
Address decoder 52 operates in the same manner as the address decoder 52 of the master side D / A converter group 44 based on the external load signal LD2 output from the microcomputer 46.

The rest of the configuration of the slave side D / A converter group 45 is the same as that of the master side D / A converter group 44, and a description thereof will be omitted. Next, the operation of this embodiment configured as described above will be described.

Similar to the first embodiment, each integrated circuit 24-2
The value of the on-resistance of each MOS transistor necessary for adjusting the internal circuit of 6 is obtained by experiment, and the gate voltage of each MOS transistor corresponding to the on-resistance is obtained. next,
Each of the gate voltages is A / D converted with 8 bits to obtain converter data D7 to D0. Further, the storage areas 53a and 53 of the MOS transistors and the nonvolatile memory 53 are
Number them so that they can be distinguished, and renumber them to the combination of each number. Each renumbered number is A / D converted by 4 bits to determine control data D11 to D8. Then, corresponding control data D11 to D8 and converter data D7 to D0, respectively.
To generate external digital data Da which is 11-bit serial data.

Then, the microcomputer 46 stores the master side D / A converter group 4 in the storage area 53a of the non-volatile memory 53.
External digital data Da for each D / A converter 31 of 4
The slave side D / in the storage area 53b.
The external digital data Da for each D / A converter 31 of the A converter group 45 is stored.

That is, the microcomputer 46 outputs the external control signal CS corresponding to the write operation and the external digital data Da. Then, first, the shift register 32 inputs and stores the external digital data Da. Also,
The control circuit 56 outputs the converter data D7 to D0 of the shift register 32 to the nonvolatile memory 53 via the internal data bus 57 and the memory control circuit 55 based on the external control signal CS. At the same time, the control circuit 56 controls the shift register 32 based on the external control signal CS.
Control data D11 to D8 of the internal data bus 58
And the address decoder 5 via the memory control circuit 55.
Output to 4.

The address decoder 54 stores the converter data D7 to D0 in the storage areas 53a and 53b of the non-volatile memory 53 based on the control data D11 to D8.

Next, when the power of the electronic device is turned on, the microcomputer 46 causes the external control signal CS corresponding to the read operation.
And the external load signals LD1 and LD2 and the clock CLK.

Then, the control circuit 56 causes the storage area 53 of the non-volatile memory 53 based on the external control signal CS.
The converter data D7 to D0 stored in a are read out to the internal data bus 57 via the memory control circuit 55.

Further, the control circuit 56 reads out the control data D11 to D8 output from the address decoder 54 to the internal data bus 58 via the memory control circuit 55 based on the external control signal CS.

The address decoder 52 uses the internal bus 5 based on the external load signal LD1 output from the microcomputer 46.
Control data D11 to D8 are read via 8. Then, the address decoder 52 selects each latch circuit 51 based on the read control data D11 to D8 and outputs the selection signal to each latch circuit 51 via the internal bus 59.

Each latch circuit 51 selected by the address decoder 52 reads and latches the converter data D7 to D0 via the internal bus 57. Then, each latch circuit 51 outputs the latched converter data D7 to D0 to the corresponding D / A converter 31.

D / with the converter data D7-D0 input
The A converter 31 applies an analog voltage obtained by D / A converting the converter data D7 to D0 to the gate of the adjusting MOS transistor. Then, the on-resistance of the MOS transistor becomes a resistance value necessary for adjusting the internal circuit of the integrated circuit 41 obtained by the experiment. As a result, the internal circuit of the integrated circuit 41 is optimally adjusted.

Next, the control circuit 56, based on the external control signal CS, stores in the storage area 53b of the non-volatile memory 53.
The converter data D7 to D0 stored in the memory are read to the shift register 32 via the memory control circuit 55 and the internal data bus 57. Further, the control circuit 56 reads the control data D11 to D8 output from the address decoder 54 to the shift register 32 via the memory control circuit 55 and the internal data bus 58 based on the external control signal CS.

Therefore, in the shift register 32, each D / A converter 31 of the slave side D / A converter group 45 stored in the storage area 53b of the non-volatile memory 53.
The external digital data Da for is read and stored.

The external digital data Da stored in the shift register 32 is shifted by one bit each time the clock CLK is output from the microcomputer 46 and output as external digital data Db.

Then, the slave side D / A converter group 4
The shift register 32 of 5 clocks from the microcomputer 46.
Each time CLK is output, the external digital data Db is input and stored bit by bit.

The converter data D7 to D0 of the external digital data Db are read out to the internal data bus 57 of the slave side D / A converter group 45. Also, slave side D
The address decoder 52 of the A / A converter group 45, based on the external load signal LD2 output from the microcomputer 46,
The control data D11 to D8 are read via the internal bus 58. Since the subsequent operation is the same as that of the master side D / A converter group 44, its explanation is omitted.

As described above, this embodiment differs from the first embodiment in that the microcomputer 46 controls each D / A converter group 44, 45. However, the nonvolatile memory 53 is provided on the master side D / A.
This is the same as the first embodiment in that only the converter group 44 is provided and the slave D / A converter group 45 is not provided. Therefore, also in this embodiment, the number of nonvolatile memories can be reduced as in the first embodiment.

The present invention is not limited to the above embodiment, but may be carried out as follows. 1) The control circuit 34 of the first embodiment is replaced with a microcomputer which is an external device.

2) Each D / A converter 31 is not a 8-bit D / A converter but an arbitrary number of bits. 3) Convert digital data sent from the external device and the microcomputer 46 into parallel data instead of serial data.

4) The integrated circuits 24 to 26 and 41 to 43 are integrated into one integrated circuit. 5) The number of D / A converters 31 in each D / A converter group 21-23, 44, 45 is changed to an appropriate number instead of eight.

6) The storage areas 33a to 33c, 53a, 53b constituting the non-volatile memories 33, 53 are changed to an arbitrary number instead of three. In this case, as many slave D / A converter groups as the storage areas can be provided.

7) The nonvolatile memories 33 and 53 are set to EP-R.
It is configured by EEP-ROM instead of OM. 8) The non-volatile memories 33 and 53 are composed of RAM or ROM.

9) Replace the MOS transistor with an element capable of controlling the on-resistance such as a bipolar transistor, SIT or junction FET. 10) Rather than controlling the on-resistance of the transistor,
It is used in a device that controls a plurality of D / A converters and controls an analog voltage output from the D / A converters, such as a circuit that generates an appropriate reference voltage.

[0070]

As described above in detail, according to the present invention, it is possible to provide a semiconductor integrated circuit device which can automatically adjust an electronic device and which is simple and inexpensive. There is.

[Brief description of drawings]

FIG. 1 is a diagram illustrating the principle of the present invention.

FIG. 2 is a block circuit diagram of an embodiment embodying the present invention.

FIG. 3 is a block circuit diagram of an embodiment embodying the present invention.

FIG. 4 is a block circuit diagram of another embodiment embodying the present invention.

FIG. 5 is a block circuit diagram of another embodiment embodying the present invention.

FIG. 6 is a block circuit diagram of a conventional example.

FIG. 7 is a block circuit diagram of a conventional example.

FIG. 8 is a block circuit diagram of a conventional example.

[Explanation of symbols]

 1 semiconductor chip 2,6 D / A converter 3 memory 3a storage area 3b redundant storage area 4 transfer control circuit 5 other semiconductor chip

 ─────────────────────────────────────────────────── ─── Continuation of the front page (72) Inventor Hitoshi Takahashi 2-1844-2 Kozoji-cho, Kasugai-shi, Aichi Prefecture

Claims (5)

[Claims] 1. A plurality of D / A converters (2) for converting digital data into analog voltages, and digital data of at least one D / A converter (2) for the plurality of D / A converters (2). And a memory (3) having a memory area (3a) in which the memory is stored. The memory (3) includes a semiconductor chip other than the semiconductor chip (1) of the semiconductor integrated circuit device. The redundant storage area (3b) in which digital data for the D / A converter (6) provided in (5) is stored is provided, and the digital data stored in the redundant storage area (3b) is also provided. D / A of data to other semiconductor integrated circuit device (5)
A semiconductor integrated circuit device comprising a transfer control circuit (4) for transferring to a converter (6). 2. The semiconductor integrated circuit device according to claim 1, wherein the memory (3) is a non-volatile memory. 3. The D / A converters (2, 6) provided in the semiconductor integrated circuit device are each provided with a latch circuit for latching transferred digital data. , 2 semiconductor integrated circuit device. 4. A shift register is provided in the semiconductor integrated circuit device, and an external device inputs the digital data and address data of a storage area of a memory for storing the digital data to the register, and the transfer control circuit ( 4. The semiconductor integrated circuit device according to claim 1, wherein 4) has a writing function for writing digital data in a predetermined storage area based on the address data. 5. An analog voltage output from each D / A converter (2, 6) is applied to the gate or base of a transistor to control the on-resistance of the transistor, and the semiconductors are each based on the on-resistance. Chip (1,
5. The internal circuit of 5) is adjusted.
~ 4 semiconductor integrated circuit device.