JPH05335747A - Ceramic multilayer board - Google Patents

Abstract

PURPOSE:To simplify management of reflow processes for solder bumps by means of a ceramic multilayer board on which semiconductor elements that can be used for every electronic equipment such as a computer, a video and a TV, or the like, are mounted in the manner of a flip-chip, and to obtain a ceramic multilayer board which enables a high density of packaging to be realized by reducing pitches between terminals. CONSTITUTION:In a ceramic multilayer board, no interconnection electrode is disposed at least at the area, where a flip-chip is to be mounted, of vias 1 on the uppermost layer and vias 2 on the lowermost layer. Only the via at this area is constituted of Al2O3-free material that solely contains Cu. The other vias are composed of a composite material containing 10-20wt.% Al2O3 with the balance being Cu.

Description

Detailed Description of the Invention

[0001]

BACKGROUND OF THE INVENTION The present invention relates to a computer, video,
The present invention relates to a ceramic multilayer substrate that can be used in various electronic devices such as televisions.

[0002]

2. Description of the Related Art In recent years, demands for portability and convenience of electronic devices such as computers have become stronger and stronger, and electronic devices such as more portable and high-performance computers are expected to appear. Among them, the flip-chip mounting method using a protruding electrode such as a solder bump has attracted attention as a high-performance and high-density mounting method.

Flip-chip mounting is a method of directly bonding a semiconductor element having a protruding electrode such as a solder bump to a wiring electrode of a ceramic multilayer substrate. At this time, generally, as shown in FIG. 3, the wiring electrode 9 of the ceramic multilayer substrate has a pattern printed with a material such as Cu on at least one of the uppermost layer via 10 and the lowermost layer via 11. Formed by firing. Top and bottom vias 10,
11 is 10 to 2 to match the shrinkage of the via material and the base material.
It is formed of a composite material of 0 wt% Al ₂ O ₃ and the balance Cu. The middle layer via 12 is also the top and bottom vias.
Like 10 and 11, it is made of a composite material of 10 to 20 wt% Al ₂ O ₃ and the balance Cu. Then, the solder bumps 14 formed on the semiconductor element 13 are fixed on the wiring electrodes 9 and reflowed to bond the solder bumps 14 to the wiring electrodes 9.

[0004]

However, in the conventional flip chip technology, since the wiring electrodes 9 of the ceramic multilayer substrate are flat, when the solder bumps 14 are reflowed to be joined, the shape of the solder bumps is likely to collapse. There's a problem. Therefore, the reflow condition of the solder bump 14 is very strict, and it is difficult to stably reflow, and
The collapse of the shape of the solder bump means that it is easy to short-circuit with the adjacent terminal, so that there is a problem that it is difficult to reduce the pitch between the terminals.

The object of the present invention is to solve the above problems, to simplify the management of the solder bump reflow process and to reduce the pitch between terminals when flip chip mounting a semiconductor element. It is intended to provide a densified ceramic multilayer substrate.

[0006]

In order to achieve the above object, the present invention provides a ceramic multi-layer substrate in which a semiconductor element is directly bonded to a ceramic multi-layer substrate via solder bumps, and at least a flip between the uppermost layer via and the lowermost layer via. Wiring electrodes are not provided in the part where the chip is mounted, only the vias in this part are made of a Cu-only material that does not contain Al ₂ O ₃ , and the other intermediate layer vias are 10 to 20 wt%.
Was used as a ceramic multilayer substrate composed of a composite material of Al ₂ O ₃ and the balance Cu.

[0007]

According to the present invention, a wiring electrode is not provided in at least the flip-chip mounting portion of the vias in the uppermost layer and the lowermost layer, and only the vias in this portion are made of a Cu-only material containing no Al ₂ O _3. Therefore, Cu has a larger shrinkage than the glass-ceramic of the base material, and is a via with a depression. Then, it is used as an extraction electrode for the solder bump of the semiconductor element mounting the via itself. Therefore, the spherical solder bumps are fixed so as to be completely covered in the depressions, and the shape of the solder bumps is unlikely to collapse. By doing so, the range of reflow conditions for the solder bumps can be widened, and the reflow of the solder bumps can be facilitated. In addition, since the solder bump does not go out from the recess of the via, the pitch between the terminals can be basically reduced by decreasing the pitch of the via.

[0008]

DETAILED DESCRIPTION OF THE PREFERRED EMBODIMENTS A ceramic multilayer substrate according to an embodiment of the present invention will be described below with reference to the drawings. Figure 1
FIG. 4 is a cross-sectional view of a ceramic substrate used in this example, which has a structure in which there are no 7-layer vias, 6-layer inner layer lines, and wiring electrodes in the uppermost and lowermost layers. 1 is the top layer via, 2 is the bottom layer via, A
A Cu-only material containing no l ₂ O ₃ is used. Reference numeral 3 denotes an intermediate layer via, and this intermediate layer via 3 (2 layer to 6 layer vias) is a composite material of 10 to ₂₀ wt% Al ₂ O ₃ and the balance Cu in order to match the shrinkage of the via material and the ceramic substrate. It is composed of. The uppermost via 1 and the lowermost via 2 are vias having the recesses 4 by utilizing the fact that Cu shrinks more than the glass-ceramic of the ceramic base material. No wiring electrodes are provided on the uppermost layer via 1 and the lowermost layer via 2 as in the prior art, and the vias 1 and 2 themselves are used as lead electrodes for solder bumps of a semiconductor element on which they are mounted. Reference numeral 5 denotes an inner layer line, which is made of only Cu. Reference numeral 6 is a base material, which is a glass-alumina substrate.

FIG. 2 shows a cross-sectional view of a semiconductor element for continuity test having solder bumps formed thereon, which is flip-chip mounted on the ceramic multilayer substrate of the present invention. The numbers 1 to 6 in the figure are the same as those in FIG. 7 is a solder bump, and the pitch of this solder bump is 150μ.
m. Reference numeral 8 represents a semiconductor element. In this way, the mounting structure flip-chip mounted on the ceramic multilayer substrate,
In order to secure the moisture resistance, after filling the resin in the gap between the semiconductor element and the circuit board and hardening it, heat shock test, THB
When a test, a high temperature holding test and a low temperature holding test were performed,
In all the tests, the conduction resistance of the connection portion by the solder bumps was as stable as several mΩ, and no conduction failure was observed in all terminals, and good results were obtained.

[0010]

According to the present invention, since the depressions of the vias of the uppermost layer and the lowermost layer are directly used as the extraction electrodes, the shape of the solder bumps is not easily deformed, the reflow condition range of the solder bumps is wide, and the reflow is easy. Become. This simplifies the management of the reflow process, which leads to cost reduction, and because the solder bumps do not go out from the recesses of the vias, the pitch between the terminals can also be made smaller and the packaging density can be increased. Has come to be realized.

[Brief description of drawings]

FIG. 1 is a sectional view of a ceramic multilayer substrate showing an embodiment of the present invention.

FIG. 2 is a sectional view of a mounting structure flip-chip mounted on a ceramic multilayer substrate showing an embodiment of the present invention.

FIG. 3 is a cross-sectional view of a mounting structure that is flip-chip mounted on a conventional ceramic multilayer substrate.

[Explanation of symbols]

 1 Top layer via 2 Bottom layer via 3 Intermediate layer via 7 Solder bump 8 Semiconductor element

Claims (1)

[Claims] 1. In a ceramic multi-layer substrate in which a semiconductor element is directly bonded to a ceramic multi-layer substrate via solder bumps, a wiring electrode is not provided in at least a flip chip mounting portion of the uppermost layer via and the lowermost layer via. Only part of the vias is made of a Cu-only material that does not contain Al ₂ O ₃ , and the other intermediate vias are 10 to 20 wt.
% Of Al ₂ O ₃ and the balance Cu made of a composite material.