JPH05334197A - Instruction ram updating circuit - Google Patents

Abstract

PURPOSE:To update an instruction RAM in the normal operation with a simple circuitry. CONSTITUTION:The circuit consists of a normal operation address register 12, updating address register 11, selector 13 selecting two types of address registers, and selector 14 switching the RAM output and the NOP code. In updating the RAM, the register 12 holds the former value and the value of the updating address register 11 is selected as the RAM address. As an instruction, the NOP code is selected instead of the RAM output.

Description

Detailed Description of the Invention

[0001]

The present invention relates to instruction RA
A circuit with M.

[0002]

2. Description of the Related Art Conventionally, an instruction RAM is normally booted after resetting after power-on, and is not updated during operation.

[0003]

[Problems to be Solved by the Invention] Instruction R
Data may be overwritten in AM due to noise or the like. In that case, the program must be reset and booted again, and the continuity of processing is lost.

The present invention solves the above-mentioned problems, and by regularly updating the program during operation, it is possible to prevent loss of continuity of processing due to resetting even if data is accidentally destroyed. Instruction RA
An object is to provide an M update circuit.

[0005]

In order to achieve this object, the instruction RAM updating circuit of the present invention comprises two instruction RAMs, a first address generating circuit for updating, and a second address generating circuit for normal operation. Circuit,
A selector that switches the address of each RAM,
It is composed of a circuit for controlling writing and reading.

As another means for achieving the above object, the second instruction RAM updating circuit of the present invention is usually provided with one instruction RAM, a first address generating circuit for updating, and a function of holding a previous value. It is composed of a second address generating circuit for operation, a selector for switching an address, and a selector for switching between RAM output and NOP code.

[0007]

According to the present invention, since the program can be periodically updated during operation, stable processing can be performed without losing continuity of processing even if the instruction RAM is easily destroyed in an environment. ..

[0008]

FIG. 2 shows one embodiment of the present invention. 1 is a first address generating circuit having a function of incrementing an instruction every time one word is written after inputting an address to start updating the instruction RAM as an initial value, 2 is a second address performing a normal operation address operation other than updating Address generating circuits, 3 to 4 are selectors for switching addresses between two RAMs at the time of updating and other than updating, 5 to 6 are instruction RAMs, 7 is a circuit for controlling writing and reading of two RAMs,
20 is write data of instruction RAM, 2
1 is an address for starting the update of the instruction RAM, 22 is a write signal, 23 is a switching signal, and 24 is an instruction.

The operation of the instruction RAM updating circuit of this embodiment constructed as above will be described below. First, 5 RAMs are allocated for updating, and 6 RAMs are allocated for normal operation. At this time, the RAM 5 address is input from the 1 address generation circuit, and the 6 RAM address is input from the 2 address generation circuit. An address (initial address) for starting the update is input to the address generating circuit of No. 1. RA of 5 by write signal
Data is written in the initial address of M, and the address generation circuit of 1 increments the address data. By repeating this, n is continuously input from the initial address of the RAM 5.
Update word. During the update period, the RAM 5 is write-only and not read. The RAM 6 is read-only, and the data written here is output as an instruction. When the update is completed, the RAM 5 is switched to the normal operation and the RAM 6 is switched to the update by the switching signal 23. The RAM 5 address is input from the 2 address generation circuit, and the 6 RAM address is input from the 1 address generation circuit. An address (initial address) for starting the updating of the RAM 6 is input to the address generating circuit 1 1. The RAM 6 is sequentially updated from the initial address according to the write signal. At this time, RAM 6 is write-only,
RAM 5 is read-only. In this way, the instruction RAM in operation can be updated. However, this circuit requires two RAMs and the circuit scale becomes large.

FIG. 1 shows another embodiment of the present invention.
Reference numeral 11 denotes a first address generation circuit having a function of incrementing an instruction every time one word is written after inputting an address for starting the update of the instruction RAM as an initial value, and 12 denotes other than the update having a function of holding the previous value. A second address generating circuit for performing an address operation of normal operation, 13 is a selector for switching an address at the time of writing to the RAM and at other times, and 14 is any operation as a RAM output and an instruction at the time of writing to the instruction RAM and at other times. Selector for switching codes that do not reach (abbreviated as NOP code), 15
Is an instruction RAM, 20 is write data of the instruction RAM, 21 is an address for starting the update of the instruction RAM, 22 is a write signal, 24 is an instruction, and 25 is a NOP code.

The operation of the instruction RAM updating circuit of this embodiment having the above configuration will be described below. Writing to the instruction RAM is performed in one machine cycle. When not writing to the instruction RAM, the output of 12 address generation circuits is selected as the address, and the RAM output is selected as the instruction. At the time of writing to the RAM, the 12 address generation circuits hold the previous value, and the output of the 11 address generation circuit is selected as the address of the instruction RAM. At the same time, the instruction from RAM output is N
Switch to OP code. The address generator circuit 11 increments the address data every time one word of instruction is written after inputting the initial data. Figure 3
Is a timing chart for this embodiment. When updating the instruction RAM, the address m to be updated is input as the address of the RAM instead of the address n in the normal operation. After that, the address n, which should be originally input, is input. Looking at the instructions, the NOP is inserted in the normal instruction flow. In this figure, I (n) represents the instruction RAM output for address n.

[0012]

According to the present invention, the instruction RAM can be updated by an extremely simple circuit, and the RAM is regularly updated to prepare for data destruction, or a part of the program is rewritten during operation. Will be able to.

[Brief description of drawings]

FIG. 1 is a circuit diagram of an instruction RAM updating circuit according to an embodiment of the present invention.

FIG. 2 is a circuit diagram of an instruction RAM updating circuit according to another embodiment of the present invention.

FIG. 3 is a timing chart of the embodiment of FIG.

[Explanation of symbols]

 1 First Address Generation Circuit 2 Second Address Generation Circuit 3, 4 Selector 5, 6 Instruction RAM 7 Read / Write Control Circuit 11 First Address Generation Circuit 12 Second Address Generation Circuit 13, 14 Selector 15 Instruction RAM 20 input data 21 initial address 22 write signal 23 switching signal 24 instruction 25 NOP code

Claims (2)

[Claims] 1. An instruction RAM comprising two instruction RAMs, a first address generation circuit having a function of incrementing an instruction every time one word is written after inputting an address for starting the update of the instruction RAM as an initial value, and normal other than update. A second address generating circuit for performing an address operation of the operation; a selector for switching the address between the two RAMs at the time of updating and at a time other than updating;
A circuit for controlling writing and reading of two RAMs is provided. First, an address is input to the first RAM from the first address generation circuit, writing is performed according to a write signal, and reading is not performed and used for updating.
An address is input to the RAM of the second address generation circuit, only reading is performed and used for normal operation. After the update is completed, the first RAM is switched to normal operation and the second RAM is switched to update, which are alternated. An instruction RAM updating circuit characterized by repeatedly updating the instruction RAM during normal operation. 2. An instruction RAM, a first address generation circuit having a function of incrementing an instruction every time one word is written after inputting an address for starting update of the instruction RAM as an initial value, and holding a previous value. A second address generating circuit for performing an address operation of a normal operation other than updating, which has a function of
A selector is provided for switching the address at the time of writing the instruction RAM and at other times, and a selector for switching the RAM output and a code (hereinafter abbreviated as NOP code) having no effect as the instruction output at the time of writing the instruction RAM and at other times, When writing data to the instruction RAM,
The second address generation circuit holds the previous value, selects the output of the first address generation circuit as the RAM address, selects the NOP code instead of the output of the RAM as the instruction, and updates the instruction RAM during normal operation. Instruction RAM update circuit characterized by the above.