JPH03252996A - Scan-in system - Google Patents

Abstract

PURPOSE:To increase the processing speed by providing a flag clear means which clears flags of a flag storage means and a flag set means which sets the flag of the flag storage means selected by a first address setting means at the time of writing data for scan-in. CONSTITUTION:When the scan operation is started, data corresponding to the scan address is outputted from a data memory 2 to a selector 3 bit by bit by the indication of an address counter 5. When a corresponding flag is '1', data from the data memory 2 is scanned into a circuit 1 by the selector 3; but otherwise, it is not scanned in and data scanned out from the circuit 1 is scanned in as it is. Consequently, it is unnecessary to preliminarily scan out all flip flops, and only one scan operation is required. Thus, the scan-in processing speed is increased.

Description

[Detailed Description of the Invention] [Field of Industrial Application] The present invention relates to a scan-in method, in particular, a scan method in which data is written by operating a plurality of flip-flops addressed in bit units as a shift register using a shift clock.・In method % expression % [Prior art] In this type of conventional scan-in method, in order to scan in multiple registers in one scan-in operation, all flip-flops must be The data is scanned out to a randomly accessible storage device, and then the target data is rewritten and scanned in.

[Problem to be solved by the invention]

In the conventional scan-in method described above, it is necessary to stop the device and scan out all registers each time, especially when it is necessary to perform scan-ins frequently while the device is operating. As a result, it is necessary to perform at least two scan operations. This poses a problem in that the apparatus stop time increases in the processing time spent on scanning operations.

[Means to solve the problem]

The method of the present invention is a scan-in method in which a plurality of flip-flops addressed bit by bit are operated as a shift register using a shift clock to write data. data storage means for storing bit-by-bit data inputted for the purpose of the shift; first address setting means for giving an address for storing the data to the data storage means; a second address setting means which updates the address each time the data is completed and provides an address of the data to be scanned into the data storage means; A flag storage means corresponds one-to-one with the storage means, and during a shift operation, the data shifted from the last flip-flop and the data from the data storage means are switched and scanned according to the state of the flag of the flag storage means. - Data selection means to be data; and after outputting data of the area selected by the second address setting means in the data storage means to the data selection means during the shift operation, the second address setting means a flag clearing means for clearing the flag of the flag storage means selected by the flag storage means; and a flag clearing means for clearing the flag of the flag storage means selected by the flag storage means; It is characterized by comprising a flag setting means for setting the flag in the flag storage means selected by the first address setting means.

〔Example〕

Next, one embodiment of the present invention will be specifically described with reference to the drawings.

FIG. 1 is a diagram showing the configuration of an embodiment of the present invention.

In FIG. 1, a circuit 1 has a serial scan function. Data memory 2 stores data to be updated for scan-in to circuit 1.

The data scanned out from the circuit 1 and the output from the data memory 2 are input to the selector 3.
The output is scanned into circuit 1.

Shift clock 4 is output for every 1 bit shift during scan operation. The address counter 5 outputs an address to the data memory 2 and flag memory 6 during a scan operation, and is configured to indicate the scan address corresponding to the data input to the selector 3 every 1 bit shift.

The flag memory 6 is connected to the data in the data memory 2.
It has a flag corresponding to pair 1 and is configured so that it is always accessed by the same address.
”, and when writing set data 8, set “l” as a flag.
It operates to write to the memory 6.

The selector 7 outputs the output of the address counter 5 during the scan operation, and outputs the set address 9 corresponding to the scan address of the update data to the data memory 2 and the flag when writing the set data 8, which is data to be scanned in. - Operates to match the address of memory 6.

When the output from the flag memory 10 is "0", the selector 3 selects the data scanned out from the circuit 1, and when the output from the flag memory 10 is "1".
”, the output from the data memory 2 is sent to the circuit 1.

In the above configuration, first, when a plurality of set data 8 are input, flags corresponding to scan addresses to be data updated are set by starting a scan operation. (However, it is assumed that all flags are cleared in the initial state.) Next, when the scan operation is started, the data corresponding to the scan address is transferred from the data memory 2 by the instruction of the address counter 5 bit by bit. It is output to selector 3. When the flag corresponding to the address is "1", the data from the data memory 2 is scanned in to the circuit 1 by the selector 3, but when it is "0", the data is not scanned in. Instead, the data scanned out from circuit 1 is scanned in as is.

Also, at this time, the corresponding flag is set to "0" by the selector 3 every time one bit of data is scanned in. Due to these operations, the flag is set to 1 at the end of the scan operation.
” only the flip-flop corresponding to the data is updated and all flags are cleared to “0”.

〔Effect of the invention〕

As explained above, according to the present invention, when performing scan-in to multiple flip-flops, there is no need to scan out all flip-flops in advance, and as a result, only one scan operation is required. .

This has the effect of improving the processing speed of scan-in processing.

[Brief explanation of drawings]

FIG. 1 shows the present invention. 1 is a diagram showing the configuration of an embodiment; 1... circuit; 2... data memory;
3,7゜10... Selector, 4... Shift clock, 5... Address counter, 6...
... Flag memory, 8 ... Set data, 9 ... Set address.

Claims (1)

[Claims] In a scan-in method in which a plurality of flip-flops addressed in bits are operated as a shift register using a shift clock and data is written, for scan-in before the shift operation is executed, a data storage means for storing input bit-by-bit data; a first address setting means for giving an address for storing the data to the data storage means; and a first address setting means for giving an address for storing the data to the data storage means; a second address setting means for updating an address in the data storage means and providing an address of data to be scanned into the data storage means; a flag storage means having a one-to-one correspondence with the flag storage means; and scan-in data for switching the data shifted from the last flip-flop and the data from the data storage means according to the state of the flag of the flag storage means during a shift operation. data selection means for outputting data in an area selected by the second address setting means in the data storage means to the data selection means during the shift operation; a flag clearing means for clearing a flag of the flag storage means that has been set, and a flag clearing means for clearing a flag of the flag storage means that has been set in the flag storage means; and a flag setting means for setting the flag in the flag storage means selected by the address setting means.
In method.