JPH05333316A - Liquid crystal display device and method therefor - Google Patents

Liquid crystal display device and method therefor

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Publication number
JPH05333316A
JPH05333316A JP14031892A JP14031892A JPH05333316A JP H05333316 A JPH05333316 A JP H05333316A JP 14031892 A JP14031892 A JP 14031892A JP 14031892 A JP14031892 A JP 14031892A JP H05333316 A JPH05333316 A JP H05333316A
Authority
JP
Japan
Prior art keywords
liquid crystal
thin film
tft
display device
electrode
Prior art date
Legal status (The legal status is an assumption and is not a legal conclusion. Google has not performed a legal analysis and makes no representation as to the accuracy of the status listed.)
Pending
Application number
JP14031892A
Other languages
Japanese (ja)
Inventor
Yojiro Matsueda
洋二郎 松枝
Current Assignee (The listed assignees may be inaccurate. Google has not performed a legal analysis and makes no representation or warranty as to the accuracy of the list.)
Seiko Epson Corp
Original Assignee
Seiko Epson Corp
Priority date (The priority date is an assumption and is not a legal conclusion. Google has not performed a legal analysis and makes no representation as to the accuracy of the date listed.)
Filing date
Publication date
Application filed by Seiko Epson Corp filed Critical Seiko Epson Corp
Priority to JP14031892A priority Critical patent/JPH05333316A/en
Publication of JPH05333316A publication Critical patent/JPH05333316A/en
Pending legal-status Critical Current

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  • Liquid Crystal (AREA)
  • Liquid Crystal Display Device Control (AREA)
  • Devices For Indicating Variable Information By Combining Individual Elements (AREA)

Abstract

PURPOSE:To realize a uniform picture having no high contrast and no crosstalk by optimizing the structure, picture element circuit and driving method of a TFT and impressing a driving voltage sufficient for liquid crystal. CONSTITUTION:A TFT 3 is arranged at the intersection of a signal line 1 and a scanning line 2 which are arranged in a grid-shape and the TFT 3 is used as a switch and writes image signals in a liquid crystal capacitor and holding capacitor 6. At the TFT 3, resistor parts 4 are provided between a drain electrode D and the signal line 1 and between a source electrode S and a picture element electrode, and the pressure resistance of the TFT 3 is improved by decreasing this resistance value so as to decrease a leak current. Namely, two inequalities are established among a resistance value RT between the source and drain of the TFT 3 in the ON state, resistance value RL of the resistor parts 4, resistance value RO of a liquid crystal layer, capacity value C0, holding capacity Cs, one horizontal period TH and one vertical period T.

Description

【発明の詳細な説明】Detailed Description of the Invention

【0001】[0001]

【産業上の利用分野】本発明はアクティブマトリクス型
の液晶表示装置及びその駆動方法に関する。
BACKGROUND OF THE INVENTION 1. Field of the Invention The present invention relates to an active matrix type liquid crystal display device and a driving method thereof.

【0002】[0002]

【従来の技術】従来の、多くのアクティブマトリクス方
式の液晶表示装置に用いられているTN型の液晶は、偏
光板が2枚必要なため画面が暗く、視角が狭いという欠
点がある。そこで、偏光板を用いない高分子分散型液晶
や視角依存性の少ないゲスト・ホスト型液晶を用いる試
みもなされている。高分子分散型液晶を用いたアクティ
ブマトリクス方式の液晶表示装置の例としては、「SI
D(エス・アイ・ディ)90 ダイジェスト、p.22
7−230、クニギタ他」等がある。図2はその画素部
分の等価回路であり、信号線21と走査線22の交点に
TFT23、液晶25及び保持容量26が配置されてい
る。
2. Description of the Related Art The conventional TN type liquid crystal used in many active matrix type liquid crystal display devices has the drawbacks that the screen is dark and the viewing angle is narrow because two polarizing plates are required. Therefore, attempts have been made to use polymer-dispersed liquid crystals that do not use polarizing plates or guest-host liquid crystals that have little viewing angle dependence. An example of an active matrix type liquid crystal display device using polymer dispersed liquid crystal is “SI
D (S.I.D.) 90 digest, p. 22
7-230, Kunigita and others ”. FIG. 2 is an equivalent circuit of the pixel portion, in which a TFT 23, a liquid crystal 25, and a storage capacitor 26 are arranged at the intersection of the signal line 21 and the scanning line 22.

【0003】[0003]

【発明が解決しようとする課題】しかし、前述の従来技
術には以下に述べるような課題がある。一般に、高分子
分散型液晶やゲスト・ホスト型の液晶は、TN型の液晶
に比べてしきい値電圧が高く、印加電圧に対する透過率
の変化が小さいため、高いコントラスト比を得るために
はTN型の数倍の電圧を印加しなければならない。とこ
ろが、TFTの耐圧はあまり大きくないため、信頼性を
確保するためには印加電圧に上限がある。また、駆動電
圧が大きいと液晶やTFTのリーク電流が増大し、コン
トラストの低下やクロストークなどの問題を生じる。
However, the above-mentioned prior art has the following problems. Generally, polymer-dispersed liquid crystals and guest-host liquid crystals have a higher threshold voltage and a smaller change in transmittance with respect to applied voltage than TN liquid crystals. A voltage that is several times that of the mold must be applied. However, since the withstand voltage of the TFT is not so large, the applied voltage has an upper limit in order to ensure reliability. Further, when the driving voltage is high, the leak current of the liquid crystal or the TFT increases, which causes problems such as deterioration of contrast and crosstalk.

【0004】本発明の液晶表示装置はこの様な課題を解
決するものであり、その目的とするところは、高分子分
散型液晶やゲスト・ホスト型の液晶を用いたアクティブ
マトリクス型の液晶表示装置で高いコントラストとクロ
ストークな無い均一な画面を実現することにある。
The liquid crystal display device of the present invention solves such a problem, and an object thereof is to provide an active matrix liquid crystal display device using polymer dispersed liquid crystal or guest-host liquid crystal. Is to realize a high contrast and a uniform screen without crosstalk.

【0005】[0005]

【課題を解決するための手段】本発明の液晶表示装置
は、薄膜トランジスタのチャネル部とドレイン電極間及
びチャネル部とソース電極間に半導体薄膜からなる抵抗
部を備え、薄膜トランジスタのON状態のチャネル部の
抵抗値RT、抵抗部の抵抗値RL、画素電極と対向電極
間の液晶層の抵抗値R0、容量値C0、保持容量Cs、
1水平走査期間TH、及び1垂直走査期間Tの間に次の
2つの式が成り立つことを特徴とする。
A liquid crystal display device of the present invention is provided with a resistance portion made of a semiconductor thin film between a channel portion and a drain electrode of a thin film transistor and between a channel portion and a source electrode of the thin film transistor, and Resistance value RT, resistance value RL of resistance part, resistance value R0 of liquid crystal layer between pixel electrode and counter electrode, capacitance value C0, storage capacitance Cs,
It is characterized in that the following two expressions are established during one horizontal scanning period TH and one vertical scanning period T.

【0006】(RT+2・RL)×(Cs+C0)<T
H (C0+Cs)×R0>T また、対向電極に2つの電位を1水平走査期間の整数倍
または1垂直走査期間を半周期として繰り返し印加し、
2つの電位差Vcが液晶層のスレッショルド電圧Vth
と信号線に印加される画像信号電圧範囲Vidの間に下
式が成り立つことを特徴とする。
(RT + 2 · RL) × (Cs + C0) <T
H (C0 + Cs) × R0> T Further, two potentials are repeatedly applied to the counter electrode with an integral multiple of one horizontal scanning period or one vertical scanning period as a half cycle,
The two potential difference Vc is the threshold voltage Vth of the liquid crystal layer.
And the image signal voltage range Vid applied to the signal line, the following expression is established.

【0007】2Vth+Vid>Vc>2Vth2Vth + Vid> Vc> 2Vth

【0008】[0008]

【実施例】本実施例を以下図面に基づいて説明する。DESCRIPTION OF THE PREFERRED EMBODIMENTS This embodiment will be described below with reference to the drawings.

【0009】図4は、液晶表示装置の透過率の印加電圧
依存性を示したものである。TN型液晶は低電圧で高い
コントラスト比を得ることができるため、大部分のTF
T液晶表示装置で用いられている。しかし、この液晶は
偏光板を2枚必要とするため、透過率が低く、視角が狭
いという問題もある。これに対し、高分子分散型液晶は
偏光板を用いないため、TN型の2倍以上の明るさを得
ることができる。ただし光の散乱を用いるため、透過型
で用いる場合には液晶プロジェクターのライトバルブの
ように平行光を光源にしなければ高いコントラスト比は
得られない。また、2色性色素を用いたゲスト・ホスト
型液晶は透過率はTN型と同等だが、非常に広い視野角
で高いコントラスト比を得ることができ、直視型の表示
装置として優れている。特に、複数の人に同時に情報を
伝えるのには最適である。
FIG. 4 shows the applied voltage dependence of the transmittance of the liquid crystal display device. Since the TN type liquid crystal can obtain a high contrast ratio at a low voltage, most TF
Used in T liquid crystal display devices. However, since this liquid crystal requires two polarizing plates, there is a problem that the transmittance is low and the viewing angle is narrow. On the other hand, since the polymer dispersed liquid crystal does not use a polarizing plate, it is possible to obtain the brightness twice or more that of the TN liquid crystal. However, since the scattering of light is used, a high contrast ratio cannot be obtained unless a parallel light source is used as a light valve of a light valve of a liquid crystal projector when used in a transmission type. Although the guest-host type liquid crystal using the dichroic dye has the same transmittance as the TN type, it can obtain a high contrast ratio in a very wide viewing angle and is excellent as a direct-view display device. In particular, it is best suited to convey information to multiple people at the same time.

【0010】一般に、高分子分散型液晶やゲスト・ホス
ト型液晶はTN型の2倍以上の駆動電圧が必要だが、こ
の電圧を下げるのは極めて困難である。たとえば、高分
子分散型液晶では誘電異方性を増加させればスレッショ
ルド電圧が低下するが、液晶の比抵抗も低下して保持動
作ができなくなってしまう。ゲスト・ホスト型液晶の場
合も色素の量を増加させればスレッショルド電圧が低下
するが、液晶の比抵抗も低下して保持動作ができなくな
ってしまう。そこで、本願ではTFTの構造、画素回路
およびその駆動方法を最適化し、液晶に十分な駆動電圧
を印加できるように工夫した。
Generally, polymer-dispersed liquid crystals and guest-host liquid crystals require a driving voltage that is more than twice that of the TN liquid crystal, but it is extremely difficult to lower this voltage. For example, in a polymer dispersed liquid crystal, increasing the dielectric anisotropy lowers the threshold voltage, but also lowers the specific resistance of the liquid crystal, making the holding operation impossible. In the case of guest-host type liquid crystal, if the amount of the dye is increased, the threshold voltage decreases, but the specific resistance of the liquid crystal also decreases, and the holding operation becomes impossible. Therefore, in the present application, the structure of the TFT, the pixel circuit and the driving method thereof are optimized so that a sufficient driving voltage can be applied to the liquid crystal.

【0011】図1は本発明の液晶表示装置の等価回路図
の例である。格子状に配置された信号線1と走査線2の
交点にはTFT3が配置され、ドレイン電極(D)は信
号線に、ゲート電極(G)は走査線に、ソース電極
(S)は画素電極にそれぞれ接続されている。画素電極
と対向電極の間には液晶5があり、この液晶の容量をC
0、抵抗をR0とする。ここではTFTはスイッチとし
て用いられ、画像信号を液晶容量及び保持容量6に書き
込む働きをする。保持容量には本図のように前段の走査
線に付加する付加容量方式と、独立した容量線との間に
作り込む蓄積容量方式の2種類がある。本実施例のTF
Tではドレイン電極と信号線の間、及びソース電極と画
素電極との間に抵抗部4がある。この抵抗値を最適化す
ることによりTFTの耐圧を向上させ、リーク電流を減
少させることができる。具体的には、TFTがON状態
におけるソース・ドレイン間の抵抗値をRT、抵抗部4
の抵抗値をRLとすると、 (RT+2・RL)×(Cs+C0)<TH ......(1) でなければならない。ここでTHは1水平走査期間であ
り、たとえば95%以上の電圧を書き込むためには
(1)式の左辺は少なくともTHの1/3以下でなけれ
ばならない。一方、RLがあまり小さいと、TFTがO
FF状態においてドレイン部の電界強度を低減させるこ
とができなくなりリーク電流を抑える効果が無くなって
しまう。そこでRLの大きさは通常はRTの数十分の1
から数倍程度の範囲が実用的である。
FIG. 1 is an example of an equivalent circuit diagram of the liquid crystal display device of the present invention. TFTs 3 are arranged at the intersections of the signal lines 1 and the scanning lines 2 arranged in a lattice, the drain electrodes (D) are the signal lines, the gate electrodes (G) are the scanning lines, and the source electrodes (S) are the pixel electrodes. Respectively connected to. There is a liquid crystal 5 between the pixel electrode and the counter electrode, and the capacitance of this liquid crystal is C
0 and resistance is R0. Here, the TFT is used as a switch and has a function of writing an image signal in the liquid crystal capacitance and the storage capacitance 6. There are two types of storage capacitors, an additional capacitance system that is added to the preceding scanning line as shown in the figure, and a storage capacitance system that is created between independent storage lines. TF of this embodiment
At T, there is a resistance portion 4 between the drain electrode and the signal line and between the source electrode and the pixel electrode. By optimizing this resistance value, the breakdown voltage of the TFT can be improved and the leak current can be reduced. Specifically, when the TFT is in the ON state, the resistance value between the source and the drain is RT, and the resistance unit 4
If the resistance value of RL is RL, then (RT + 2 · RL) × (Cs + C0) <TH (1). Here, TH is one horizontal scanning period, and for example, in order to write a voltage of 95% or more, the left side of expression (1) must be at least 1/3 or less of TH. On the other hand, if RL is too small, the TFT becomes O
In the FF state, the electric field strength of the drain part cannot be reduced, and the effect of suppressing the leak current is lost. Therefore, the size of RL is usually one tenths of that of RT.
It is practical to have a range of from several times.

【0012】一般に、高分子分散型液晶やゲスト・ホス
ト型液晶はTN型液晶より比抵抗が小さく、十分な保持
容量を付加しなければ書き込まれた電圧を保持すること
ができない。しかし、保持容量の増大は開口率の低下を
招き、画面の明るさを減少させるため、必要最低限の大
きさにすべきである。コントラスト比を低下させること
なく、しかも明るさを損なわないための条件としては、 (C0+Cs)×R0>T ......(2) であればよい。ここで、Tは1垂直走査期間であり、こ
の式は液晶に書き込まれた電圧が6割以上保持されるこ
とを意味し、実効値としては7割以上の電圧が液晶に印
加されることになる。
In general, polymer-dispersed liquid crystals and guest-host liquid crystals have a smaller specific resistance than TN liquid crystals and cannot hold a written voltage unless a sufficient storage capacitance is added. However, the increase of the storage capacity leads to a decrease of the aperture ratio and the brightness of the screen is reduced, and therefore the size should be set to the minimum necessary. (C0 + Cs) × R0> T (2) may be satisfied as a condition for reducing the contrast ratio and not impairing the brightness. Here, T is one vertical scanning period, and this expression means that the voltage written in the liquid crystal is held at 60% or more, and the effective value is that 70% or more of the voltage is applied to the liquid crystal. Become.

【0013】図3は、より開口率を向上させるためにT
FTの片側だけに抵抗部を設けた場合の画素部分の等価
回路の例である。一般に、抵抗部34はTFT33のド
レイン側につけることによってリーク電流低減の効果が
ある。したがって、交流駆動が前提となる液晶表示装置
においては厳密には図1のように両側に付けなければな
らないが、このように信号線側のみに付けてもかなりの
効果がある。これはTFTの寄生容量と液晶容量・保持
容量間の容量結合によって生じる電圧により、実際には
信号線31の平均電位は画素電極の平均電位より高いた
めである。
FIG. 3 shows T in order to further improve the aperture ratio.
It is an example of an equivalent circuit of a pixel portion when a resistance portion is provided only on one side of an FT. In general, the resistance portion 34 is provided on the drain side of the TFT 33 to reduce the leak current. Therefore, strictly speaking, in a liquid crystal display device that is premised on AC driving, it must be attached to both sides as shown in FIG. 1, but even if it is attached only to the signal line side in this way, there is a considerable effect. This is because the average potential of the signal line 31 is actually higher than the average potential of the pixel electrode due to the voltage generated by the parasitic capacitance of the TFT and the capacitive coupling between the liquid crystal capacitance and the storage capacitance.

【0014】次に、実際のTFTの構造例を説明する。
図5は代表的なLDD構造のTFTである。絶縁基板上
に堆積された半導体薄膜は、不純物の注入濃度で3つの
領域に分けられる。すなわち、真性半導体領域51、低
濃度不純物注入領域52及び高濃度不純物注入領域53
である。このうち、真性半導体領域51はTFTのチャ
ネル領域であり、ゲート電極55をマスクとしてゲート
絶縁膜54を通してイオン注入することで、セルフアラ
インで低濃度不純物注入領域52と真性半導体領域51
とに分けられる。チャネル部にはこのように真性半導体
層を用いる場合と低濃度の不純物を注入しておく場合と
がある。また、本図における低濃度不純物領域52をチ
ャネル部と同じ真性半導体の状態にしておけばオフセッ
トゲートのTFTとなる。高濃度不純物注入領域53は
半導体薄膜と透明導電膜58及び金属薄膜57とオーミ
ックコンタクトをとるために十分低抵抗化する必要があ
る。高濃度不純物領域53とチャネル部間の距離が必要
以上に離れるのは(1)式のRLを増大させるほか、開
口率の低下にもつながるため、セルフアラインで必要最
低限の距離に制御することが望ましい。具体的な方法と
しては、ゲート電極に堆積された絶縁膜の側壁部をマス
クとして利用する方法や、ゲート電極を不純物注入後に
オーバーエッチする方法などがある。透明導電膜58は
画素電極を構成し、金属薄膜57は信号線を構成し、こ
れらは層間絶縁膜56によってゲート電極55と絶縁さ
れている。
Next, an example of the structure of an actual TFT will be described.
FIG. 5 shows a typical TFT having an LDD structure. The semiconductor thin film deposited on the insulating substrate is divided into three regions according to the impurity implantation concentration. That is, the intrinsic semiconductor region 51, the low concentration impurity implantation region 52 and the high concentration impurity implantation region 53.
Is. Of these, the intrinsic semiconductor region 51 is a channel region of the TFT, and by ion-implanting through the gate insulating film 54 using the gate electrode 55 as a mask, the low-concentration impurity implantation region 52 and the intrinsic semiconductor region 51 are self-aligned.
Is divided into There are cases where an intrinsic semiconductor layer is used as described above and cases where a low-concentration impurity is implanted in the channel portion. Further, if the low-concentration impurity region 52 in this figure is in the same intrinsic semiconductor state as that of the channel portion, it becomes an offset gate TFT. The high-concentration impurity-implanted region 53 needs to have a sufficiently low resistance in order to make ohmic contact with the semiconductor thin film, the transparent conductive film 58, and the metal thin film 57. If the distance between the high-concentration impurity region 53 and the channel portion is unnecessarily large, not only the RL of the formula (1) is increased but also the aperture ratio is lowered. Therefore, the self-alignment should be controlled to the minimum required distance. Is desirable. As a specific method, there is a method of using the side wall portion of the insulating film deposited on the gate electrode as a mask, a method of over-etching the gate electrode after implanting impurities, and the like. The transparent conductive film 58 constitutes a pixel electrode, the metal thin film 57 constitutes a signal line, and these are insulated from the gate electrode 55 by the interlayer insulating film 56.

【0015】図6は他のTFTの構造例を示す図であ
る。この例では、TFTのコンタクト部の抵抗を下げる
ためにあらかじめ不純物半導体薄膜63を堆積してお
き、次に薄い半導体薄膜を堆積して、チャネル部となる
真性半導体領域63及び低濃度不純物注入領域62を形
成する。この方法は、チャネル部の膜厚を薄くすること
ができTFTの電気的な特性を向上させることができ
る。
FIG. 6 is a diagram showing an example of the structure of another TFT. In this example, an impurity semiconductor thin film 63 is deposited in advance in order to reduce the resistance of the contact portion of the TFT, and then a thin semiconductor thin film is deposited to form an intrinsic semiconductor region 63 and a low concentration impurity implantation region 62 to be a channel portion. To form. According to this method, the thickness of the channel portion can be reduced and the electrical characteristics of the TFT can be improved.

【0016】最後に、この液晶表示装置の駆動方法を説
明する。図7は、小さな画像入力信号振幅で液晶に十分
な電圧を印加するための駆動波形のタイミングチャート
の例である。一般に液晶は交流駆動をする必要があるた
め、この例では対向電極の電位73を1フィールドごと
にVC1とVC2の2つのレベルで切り換えている。こ
れによって信号線の電位72は、正極性で書き込む場合
にも負極性で書き込む場合にもほとんど同じ電圧範囲に
することができる。走査線の電位71は、各フィールド
で1回ずつ1水平走査期間分の選択パルスが与えられ、
TFTをONさせるのに必要な電位VHに保たれる。非
選択期間は対向電極と同期して2つの電位VL1とVL
2を交互に繰り返す。これは保持容量が前段ゲートに付
加されている場合の駆動方法で、独立した容量線に付加
する蓄積容量方式の場合にはその容量線に対向電極と同
じ電位を与えればよい。画素電極の電位74は選択期間
中は信号線の電位と等しくなり、非選択期間は(2)式
の左辺で定義される時定数で対向電極の電位に近づいて
いく。実際に液晶に印加される電圧はこの画素電極の電
位74と対向電極の電位73の電位差であり、この電圧
が正負両極性で対称となるように対向電極の電位73は
設定される。これはフリッカーを防ぐためである。信号
線の電位72の平均電位と対向電極電位73の平均値を
比較するとNチャネルのTFTの場合には後者は前者よ
りある電圧だけ低く設定しなければならない。これはT
FTがOFFする際、TFTの寄生容量と液晶容量及び
保持容量の間の容量結合によって画素電極電位がシフト
するため、このシフト電圧分を補う必要があるからであ
る。
Finally, a method of driving this liquid crystal display device will be described. FIG. 7 is an example of a timing chart of drive waveforms for applying a sufficient voltage to the liquid crystal with a small image input signal amplitude. In general, since the liquid crystal needs to be driven by an alternating current, in this example, the potential 73 of the counter electrode is switched between two levels VC1 and VC2 for each field. As a result, the potential 72 of the signal line can be set to almost the same voltage range when writing with positive polarity and writing with negative polarity. The potential 71 of the scanning line is given a selection pulse for one horizontal scanning period once in each field,
The potential VH required to turn on the TFT is maintained. In the non-selection period, two potentials VL1 and VL are synchronized with the counter electrode.
Repeat 2 alternately. This is a driving method in the case where a storage capacitor is added to the previous stage gate, and in the case of a storage capacitance method in which it is added to an independent capacitance line, the same potential as that of the counter electrode may be applied to that capacitance line. The potential 74 of the pixel electrode becomes equal to the potential of the signal line during the selection period, and approaches the potential of the counter electrode with the time constant defined by the left side of the equation (2) during the non-selection period. The voltage actually applied to the liquid crystal is the potential difference between this pixel electrode potential 74 and the counter electrode potential 73, and the counter electrode potential 73 is set so that this voltage is symmetrical in both positive and negative polarities. This is to prevent flicker. Comparing the average potential of the signal line potential 72 and the average value of the counter electrode potential 73, in the case of an N-channel TFT, the latter must be set lower than the former by a certain voltage. This is T
This is because when the FT is turned off, the pixel electrode potential shifts due to capacitive coupling between the parasitic capacitance of the TFT and the liquid crystal capacitance and the storage capacitance, and it is necessary to compensate for this shift voltage.

【0017】一般に、中間調を含む画像信号振幅を増幅
し低インピーダンスで信号線を駆動するのは、外部回路
の負担を増大させ消費電力も増大させることになる。そ
こで、画像信号振幅を必要最低限に抑え液晶には十分な
電圧を印加するために、本実施例では下式を満たすよう
に駆動電圧を設定する。
In general, driving the signal line with low impedance by amplifying the image signal amplitude including halftone increases the load on the external circuit and increases the power consumption. Therefore, in order to suppress the image signal amplitude to a necessary minimum and apply a sufficient voltage to the liquid crystal, the driving voltage is set so as to satisfy the following expression in this embodiment.

【0018】 2Vth+Vid>VC1−VC2>2Vth ......(3) ここでVidは信号線に印加される画像信号振幅であ
り、Vthは液晶層のスレッショルド電圧である。この
条件であれば、正極性と負極性の信号線の画像信号のレ
ベルが重なり合うことになり、信号線の駆動回路のダイ
ナミックレンジを最小に抑えることができ、駆動回路の
小型・低消費電力・低コスト化が可能である。
2Vth + Vid>VC1-VC2> 2Vth (3) where Vid is the amplitude of the image signal applied to the signal line, and Vth is the threshold voltage of the liquid crystal layer. Under this condition, the levels of the image signals of the positive and negative signal lines overlap each other, the dynamic range of the signal line drive circuit can be minimized, and the drive circuit can be made compact and have low power consumption. Cost reduction is possible.

【0019】なお、図7においては1垂直走査期間ごと
に画像信号の極性が反転しているが、この周期は1水平
走査期間あるいはその整数倍にすることもできる。この
場合には画素の約半分が常に逆の極性で液晶を駆動する
ことになり、フリッカーとクロストークの抑制効果があ
る。
Although the polarity of the image signal is inverted every one vertical scanning period in FIG. 7, this period may be one horizontal scanning period or an integral multiple thereof. In this case, about half of the pixels always drive the liquid crystal with opposite polarities, which has the effect of suppressing flicker and crosstalk.

【0020】本発明の駆動方法は、非単結晶Si薄膜や
化合物半導体薄膜から成るTFTや単結晶Si基板上に
形成されたMOSFET等、走査線に選択パルスを印加
してオン・オフさせる全ての素子を用いたアクティブマ
トリクス型の液晶表示装置に適用できる。
In the driving method of the present invention, a TFT made of a non-single-crystal Si thin film or a compound semiconductor thin film, a MOSFET formed on a single-crystal Si substrate, or the like is applied to all scanning lines to turn them on and off. It can be applied to an active matrix type liquid crystal display device using an element.

【0021】[0021]

【発明の効果】以上述べたように本発明の液晶表示装置
は、高分子分散型液晶を用いて非常に明るい液晶プロジ
ェクターを実現したり、ゲスト・ホスト型液晶を用いて
視角の広い直視型のディスプレイを実現できる。しか
も、TN型と同等のコストで実現でき、消費電力もTN
型並でありるため、実用的な液晶表示装置となる。また
表示品質に関しても、十分な駆動電圧を印加できるため
高コントラスト比が得られ、リーク電流は極めて少ない
ためクロストークも無く、最高品質の画像が得られる。
As described above, the liquid crystal display device of the present invention realizes a very bright liquid crystal projector by using polymer dispersion type liquid crystal, and a direct view type of wide viewing angle by using guest-host type liquid crystal. A display can be realized. Moreover, it can be realized at the same cost as the TN type and consumes less power than the TN type.
Since it is similar to a mold, it becomes a practical liquid crystal display device. As for display quality, a high contrast ratio can be obtained because a sufficient drive voltage can be applied, and since leakage current is extremely small, crosstalk does not occur and an image of the highest quality can be obtained.

【図面の簡単な説明】[Brief description of drawings]

【図1】 液晶表示装置の画素部分の等価回路図。FIG. 1 is an equivalent circuit diagram of a pixel portion of a liquid crystal display device.

【図2】 従来の液晶表示装置の画素部分の等価回路
図。
FIG. 2 is an equivalent circuit diagram of a pixel portion of a conventional liquid crystal display device.

【図3】 液晶表示装置の画素部分の等価回路図。FIG. 3 is an equivalent circuit diagram of a pixel portion of a liquid crystal display device.

【図4】 液晶表示装置の透過率の印加電圧依存性を示
す図。
FIG. 4 is a diagram showing applied voltage dependency of transmittance of a liquid crystal display device.

【図5】 TFTの断面図。FIG. 5 is a cross-sectional view of a TFT.

【図6】 TFTの断面図。FIG. 6 is a cross-sectional view of a TFT.

【図7】 液晶表示装置の駆動方法を示すタイミングチ
ャート。
FIG. 7 is a timing chart showing a driving method of a liquid crystal display device.

【符号の説明】[Explanation of symbols]

1、21、31 信号線 2、22、32 走査線 3、23、33 TFT 4、34 抵抗部 5、25、35 液晶 6、26、36 保持容量 51、61 真性半導体領域 52、62 低濃度不純物注入領域 53 高濃度不純物注入領域 63 不純物半導体薄膜 54、64 ゲート絶縁膜 55、65 ゲート電極 56、66 層間絶縁膜 57、67 金属薄膜 58、68 透明導電膜 71 走査線の電位 72 信号線の電位 73 対向電極の電位 74 画素電極の電位 1, 21, 31 Signal line 2, 22, 32 Scan line 3, 23, 33 TFT 4, 34 Resistor part 5, 25, 35 Liquid crystal 6, 26, 36 Storage capacitor 51, 61 Intrinsic semiconductor region 52, 62 Low concentration impurity Injection region 53 High-concentration impurity injection region 63 Impurity semiconductor thin film 54, 64 Gate insulating film 55, 65 Gate electrode 56, 66 Interlayer insulating film 57, 67 Metal thin film 58, 68 Transparent conductive film 71 Scan line potential 72 Signal line potential 73 potential of counter electrode 74 potential of pixel electrode

Claims (3)

【特許請求の範囲】[Claims] 【請求項1】 第1の基板上に複数の走査線及び信号
線、前記信号線にドレイン電極が接続され前記走査線に
ゲート電極が接続された薄膜トランジスタ、及び前記薄
膜トランジスタのソース電極に接続された画素電極と保
持容量を備え、第2の基板上には対向電極を備え、前記
第1の基板と前記第2の基板を対向させた空間に高分子
分散型またはゲスト・ホスト型液晶を挟持して成る液晶
表示装置において、前記薄膜トランジスタのチャネル部
とドレイン電極間及びチャネル部とソース電極間に半導
体薄膜からなる抵抗部を備え、前記薄膜トランジスタの
ON状態のチャネル部の抵抗値RT、前記抵抗部の抵抗
値RL、前記画素電極と前記対向電極間の液晶層の抵抗
値R0、容量値C0、前記保持容量Cs、1水平走査期
間TH、及び1垂直走査期間Tの間に次の2つの式が成
り立つことを特徴とする液晶表示装置。 (RT+2・RL)×(Cs+C0)<TH (C0+Cs)×R0>T
1. A plurality of scanning lines and signal lines on a first substrate, a thin film transistor having a drain electrode connected to the signal line and a gate electrode connected to the scanning line, and a source electrode of the thin film transistor. A pixel electrode and a storage capacitor are provided, a counter electrode is provided on a second substrate, and a polymer-dispersed or guest-host liquid crystal is sandwiched in a space where the first substrate and the second substrate face each other. A liquid crystal display device comprising: a thin film transistor, wherein a resistance portion made of a semiconductor thin film is provided between the channel portion and the drain electrode and between the channel portion and the source electrode of the thin film transistor, and the resistance value RT of the ON state channel portion of the thin film transistor, Resistance value RL, resistance value R0 of the liquid crystal layer between the pixel electrode and the counter electrode, capacitance value C0, the storage capacitance Cs, 1 horizontal scanning period TH, and 1 vertical scan. A liquid crystal display device characterized in that the following two expressions are established during a check period T. (RT + 2 · RL) × (Cs + C0) <TH (C0 + Cs) × R0> T
【請求項2】 前記半導体薄膜からなる抵抗部が、前記
薄膜トランジスタのチャネル部とドレイン電極間にのみ
存在することを特徴とする請求項1記載の液晶表示装
置。
2. The liquid crystal display device according to claim 1, wherein the resistance portion formed of the semiconductor thin film exists only between the channel portion and the drain electrode of the thin film transistor.
【請求項3】 第1の基板上に複数の走査線及び信号
線、及び前記信号線と前記走査線の交点に配置される薄
膜トランジスタ、及び薄膜トランジスタに接続された画
素電極とを備え、第2の基板上には対向電極を備え、前
記第1の基板と前記第2の基板を対向させた空間に高分
子分散型またはゲスト・ホスト型液晶を挟持して成る液
晶表示装置の駆動方法において、前記対向電極に2つの
電位を1水平走査期間の整数倍または1垂直走査期間を
半周期として繰り返し印加し、前記2つの電位差Vc、
前記液晶層のスレッショルド電圧Vth、及び前記信号
線に印加される画像信号電圧範囲Vidの間に下式が成
り立つことを特徴とする液晶表示装置の駆動方法。 2Vth+Vid>Vc>2Vth
3. A plurality of scanning lines and signal lines, a thin film transistor arranged at an intersection of the signal line and the scanning line, and a pixel electrode connected to the thin film transistor are provided on a first substrate, and a second electrode is provided. A method for driving a liquid crystal display device, comprising a counter electrode on a substrate, and sandwiching a polymer-dispersed type or guest-host type liquid crystal in a space in which the first substrate and the second substrate face each other. Two potentials are repeatedly applied to the counter electrode with an integral multiple of one horizontal scanning period or one vertical scanning period as a half cycle, and the two potential differences Vc,
A method of driving a liquid crystal display device, wherein the following formula is established between a threshold voltage Vth of the liquid crystal layer and an image signal voltage range Vid applied to the signal line. 2Vth + Vid>Vc> 2Vth
JP14031892A 1992-06-01 1992-06-01 Liquid crystal display device and method therefor Pending JPH05333316A (en)

Priority Applications (1)

Application Number Priority Date Filing Date Title
JP14031892A JPH05333316A (en) 1992-06-01 1992-06-01 Liquid crystal display device and method therefor

Applications Claiming Priority (1)

Application Number Priority Date Filing Date Title
JP14031892A JPH05333316A (en) 1992-06-01 1992-06-01 Liquid crystal display device and method therefor

Publications (1)

Publication Number Publication Date
JPH05333316A true JPH05333316A (en) 1993-12-17

Family

ID=15266026

Family Applications (1)

Application Number Title Priority Date Filing Date
JP14031892A Pending JPH05333316A (en) 1992-06-01 1992-06-01 Liquid crystal display device and method therefor

Country Status (1)

Country Link
JP (1) JPH05333316A (en)

Cited By (2)

* Cited by examiner, † Cited by third party
Publication number Priority date Publication date Assignee Title
JP2006195455A (en) * 2004-12-24 2006-07-27 Samsung Electronics Co Ltd Thin-film transistor display panel
JP2012252355A (en) * 2012-08-07 2012-12-20 Semiconductor Energy Lab Co Ltd Display device

Cited By (2)

* Cited by examiner, † Cited by third party
Publication number Priority date Publication date Assignee Title
JP2006195455A (en) * 2004-12-24 2006-07-27 Samsung Electronics Co Ltd Thin-film transistor display panel
JP2012252355A (en) * 2012-08-07 2012-12-20 Semiconductor Energy Lab Co Ltd Display device

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