JPH11337963A - Vertical alignment type liquid crystal display device - Google Patents

Vertical alignment type liquid crystal display device

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Publication number
JPH11337963A
JPH11337963A JP10146331A JP14633198A JPH11337963A JP H11337963 A JPH11337963 A JP H11337963A JP 10146331 A JP10146331 A JP 10146331A JP 14633198 A JP14633198 A JP 14633198A JP H11337963 A JPH11337963 A JP H11337963A
Authority
JP
Japan
Prior art keywords
liquid crystal
capacitance
clc
csc
auxiliary capacitance
Prior art date
Legal status (The legal status is an assumption and is not a legal conclusion. Google has not performed a legal analysis and makes no representation as to the accuracy of the status listed.)
Pending
Application number
JP10146331A
Other languages
Japanese (ja)
Inventor
Tokuo Koma
徳夫 小間
Kiyoshi Yoneda
清 米田
Current Assignee (The listed assignees may be inaccurate. Google has not performed a legal analysis and makes no representation or warranty as to the accuracy of the list.)
Sanyo Electric Co Ltd
Original Assignee
Sanyo Electric Co Ltd
Priority date (The priority date is an assumption and is not a legal conclusion. Google has not performed a legal analysis and makes no representation as to the accuracy of the date listed.)
Filing date
Publication date
Application filed by Sanyo Electric Co Ltd filed Critical Sanyo Electric Co Ltd
Priority to JP10146331A priority Critical patent/JPH11337963A/en
Publication of JPH11337963A publication Critical patent/JPH11337963A/en
Pending legal-status Critical Current

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Abstract

PROBLEM TO BE SOLVED: To suppress unevenness of residual DC component in AC driving and prevent a display from getting burnt by letting liquid crystal capacitance and auxiliary capacitance satisfy a specific relation. SOLUTION: Liquid crystal capacitance CLC in which initial alignment of liquid crystal is controlled vertically to a substrate for each picture element and auxiliary capacitance connected with the liquid crystal capacitance CLC in parallel are formed. The auxiliary capacitance CSC consisting of a p-Si film 14, an auxiliary capacitance electrode 12, and a gate insulating film 13 is set so as to satisfy a relation, 0.61×CLC<=CSC<=2.0×CLC, with the liquid crystal capacitance CLC consisting of picture element electrode 20, common electrode 33, and liquid crystal 40. Thus, in a vertical alignment type, resultant capacitance of the liquid crystal capacitance CLC and the auxiliary capacitance CSC becomes sufficiently large by making the auxiliary capacitance CSC 0.61 times as large as the liquid crystal capacitance CLC or more. Therefore, burning phenomenon is prevented from occurring even if ON-OFF ratio of the liquid crystal capacitance becomes large.

Description

【発明の詳細な説明】DETAILED DESCRIPTION OF THE INVENTION

【0001】[0001]

【発明の属する技術分野】本発明は、垂直配向型の液晶
表示装置(LCD)に関する。
The present invention relates to a vertical alignment type liquid crystal display (LCD).

【0002】[0002]

【従来の技術】近年、LCD、有機エレクトロルミネッ
センス(EL)ディスプレイ、プラズマディスプレイ
等、のフラットパネルディスプレイの開発が盛んに行わ
れ、実用化が進められている。中でも、LCDは薄型、
低消費電力などの点で優れており、既にOA機器、AV
機器の分野で主流となっている。特に、各画素に画素情
報の書き換えタイミングを制御するスイッチング素子と
してTFTを配したアクティブマトリクス型LCDは、
大画面、高精細の動画表示が可能となるため、各種テレ
ビジョン、パーソナルコンピュータ、更には、携帯コン
ピュータ、デジタルスチルカメラ、ビデオカメラ等のモ
ニターに多く用いられている。
2. Description of the Related Art In recent years, flat panel displays such as LCDs, organic electroluminescence (EL) displays, and plasma displays have been actively developed and put to practical use. Among them, LCD is thin,
Excellent in terms of low power consumption, etc.
It has become mainstream in the field of equipment. In particular, an active matrix type LCD in which a TFT is arranged in each pixel as a switching element for controlling the timing of rewriting pixel information,
Since a large screen and high-definition moving image can be displayed, it is widely used for various televisions, personal computers, and monitors of portable computers, digital still cameras, video cameras, and the like.

【0003】図2はこのようなLCDの等価回路図であ
る。ゲートライン(1)とドレインライン(2)とが交
差して配置され、その交差部には、スイッチング素子で
ある薄膜トランジスタ(TFT)(3)と、容量電極の
一方をTFT(3)に接続した液晶容量(4)と補助容
量(5)、液晶容量(4)及び補助容量(5)の容量電
極の他方に接続された対極ライン(6)を有する。対極
ライン(6)は、全ての液晶容量(4)及び補助容量
(5)に共通となっている。TFT(3)と、液晶容量
(4)の一方、及び補助容量(5)は同一の基板上に形
成され、液晶容量(4)の他方は、別の基板上に形成さ
れている。LCDは、これらの基板間に液晶を挟み込む
ことにより成り立っている。
FIG. 2 is an equivalent circuit diagram of such an LCD. The gate line (1) and the drain line (2) are arranged so as to intersect. At the intersection, a thin film transistor (TFT) (3) as a switching element and one of the capacitance electrodes are connected to the TFT (3). It has a liquid crystal capacitor (4) and an auxiliary capacitor (5), and a counter electrode line (6) connected to the other of the capacitor electrodes of the liquid crystal capacitor (4) and the auxiliary capacitor (5). The counter electrode line (6) is common to all the liquid crystal capacitors (4) and the auxiliary capacitors (5). The TFT (3), one of the liquid crystal capacitors (4), and the auxiliary capacitor (5) are formed on the same substrate, and the other of the liquid crystal capacitors (4) is formed on another substrate. An LCD is formed by sandwiching a liquid crystal between these substrates.

【0004】ゲートライン(1)には走査信号電圧が印
加され、フィールド毎にTFT(3)を所定期間オンす
るハイレベルが到来する。この期間中、ドレインライン
(2)に印加された表示信号電圧が液晶容量(4)及び
補助容量(5)に与えられる。一方、対極ライン(6)
には対極電圧が印加され、これら表示信号電圧と対極電
圧との電圧の差が液晶の駆動電圧として印加され、表示
画面を形作るべく所望の透過率に制御される。この表示
状態は、TFTのオフ抵抗により、液晶容量(4)及び
補助容量(5)に印加された駆動電圧が保持され、1フ
ィールド期間継続される。
A scanning signal voltage is applied to the gate line (1), and a high level for turning on the TFT (3) for a predetermined period arrives for each field. During this period, the display signal voltage applied to the drain line (2) is given to the liquid crystal capacitance (4) and the auxiliary capacitance (5). On the other hand, counter electrode line (6)
Is applied with a counter voltage, and a difference between the display signal voltage and the counter voltage is applied as a driving voltage of the liquid crystal, and is controlled to a desired transmittance to form a display screen. In this display state, the drive voltage applied to the liquid crystal capacitance (4) and the auxiliary capacitance (5) is held by the off-resistance of the TFT, and is continued for one field period.

【0005】補助容量(5)は液晶容量(4)に並列接
続されているが、このように合成容量を大きくすること
により、電圧の保持率を高め、1フィールド期間にわた
って一定の表示を行えるように設けられている。
The auxiliary capacitance (5) is connected in parallel with the liquid crystal capacitance (4). By increasing the combined capacitance in this way, the voltage holding ratio is increased and a constant display can be performed over one field period. It is provided in.

【0006】また、ゲート電圧がハイレベルからロウレ
ベルに立ち下がる瞬間、TFT内部の寄生容量のため
に、いったん液晶容量(4)へ保持された電圧VLCがゲ
ート電圧の立ち下がりに伴って、下式により表される分
だけ降下する現象が生ずる。
Further, at the moment when the gate voltage falls from the high level to the low level, the voltage VLC once held in the liquid crystal capacitance (4) is reduced by the following equation due to the fall of the gate voltage due to the parasitic capacitance inside the TFT. Phenomena of falling by the amount represented by.

【0007】[0007]

【数2】 ここで、VGはゲート電圧、CGSは寄生容量、CSCは補
助容量、CLCは液晶容量である。このように、補助容量
(5)を設けることにより、ゲート電圧の変化幅ΔVG
に対する液晶容量(3)の降下量ΔVLCを小さくしてい
る。更に、LCDでは通常、液晶の劣化を抑える目的で
液晶容量(4)へ印加する電圧の極性を所定期間毎に反
転した、いわゆる交流駆動が行われる。しかしながら、
(2)式のΔVLCは、正極性期間においては、液晶に印
加される電圧をより小さくする方向に、負極性期間にお
いては、液晶に印加される電圧をより大きくする方向に
生じるので、残留直流成分として、常時、液晶へ印加さ
れる続けることとなり、いわゆる焼き付きを招いてしま
う。このため、対極電圧をあらかじめΔVLC分だけ、降
下したレベルに設定することで、正極性期間と負極性期
間とで、液晶へ印加される電圧を等しくし、焼き付き現
象を防止するようにされている。
(Equation 2) Here, VG is a gate voltage, CGS is a parasitic capacitance, CSC is an auxiliary capacitance, and CLC is a liquid crystal capacitance. Thus, by providing the auxiliary capacitance (5), the change width ΔVG of the gate voltage can be obtained.
Of the liquid crystal capacitance (3) with respect to. Further, in the LCD, so-called AC driving is generally performed in which the polarity of the voltage applied to the liquid crystal capacitor (4) is inverted every predetermined period in order to suppress the deterioration of the liquid crystal. However,
ΔVLC in the equation (2) is generated in the direction of decreasing the voltage applied to the liquid crystal during the positive polarity period and in the direction of increasing the voltage applied to the liquid crystal during the negative polarity period. As a component, it is always applied to the liquid crystal, which causes so-called burn-in. For this reason, by setting the counter electrode voltage to a level lowered by ΔVLC in advance, the voltage applied to the liquid crystal is made equal between the positive polarity period and the negative polarity period, thereby preventing the burn-in phenomenon. .

【0008】[0008]

【発明が解決しようとする課題】従来、正の誘電率異方
性を有する液晶を用いたTN型LCDにおいては、補助
容量CSCは、液晶容量CLCの0.2倍程度に設定されて
いる。しかしながら、これと同じ設計で、液晶として負
の誘電率異方性を有したものを用いた垂直配向型LCD
では、焼き付き現象が見られる問題があった。
Conventionally, in a TN type LCD using a liquid crystal having a positive dielectric anisotropy, the auxiliary capacitance CSC is set to be about 0.2 times the liquid crystal capacitance CLC. However, a vertical alignment type LCD using a liquid crystal having the same design and a negative dielectric anisotropy is used.
Then, there was a problem that a seizure phenomenon was observed.

【0009】[0009]

【課題を解決するための手段】本発明はこの課題を解決
するために成され、対向面に液晶駆動用の電極が形成さ
れた一対の基板間に液晶が封入され、画素毎に液晶の初
期配向を基板に対して垂直方向に制御した液晶容量と、
該液晶容量に並列に接続された補助容量が形成されてな
る垂直配向型液晶表示装置において、前記液晶容量CLC
と補助容量CSCとは、
SUMMARY OF THE INVENTION The present invention has been made to solve this problem, and a liquid crystal is sealed between a pair of substrates having electrodes for driving a liquid crystal formed on opposing surfaces, and an initial liquid crystal is provided for each pixel. A liquid crystal capacitor whose orientation is controlled in a direction perpendicular to the substrate,
In a vertical alignment type liquid crystal display device having an auxiliary capacitance connected in parallel with the liquid crystal capacitance, the liquid crystal capacitance CLC
And the auxiliary capacity CSC

【0010】[0010]

【数3】 の関係を満たす構成である。(Equation 3) It satisfies the relationship of

【0011】[0011]

【発明の実施の形態】図1は、本発明の実施の形態にか
かるLCDの表示画素部の断面図である。基板(10)
上に、Cr、Ti、Ta等からなるTFTのゲート電極
(11)、及び、補助容量を構成する補助容量電極(1
2)が形成され、これを覆ってゲート絶縁膜(13)が
形成されている。ゲート絶縁膜(13)上には、p−S
i膜(14)が、ゲート電極(11)の上方を通過する
ように、TFTの島状に形成されている。p−Si膜
(14)は、ゲート電極(11)の直上領域がノンドー
プのチャンネル領域(CH)とされ、チャンネル領域
(CH)の両側は、燐等のN型不純物が低濃度にドーピ
ングされた低濃度領域(LD)、更にその外側は、同じ
不純物が高濃度にドーピングされたソース領域(NS)
及びドレイン領域(ND)となっており、LDD(ligh
tly doped drain)構造とされている。p−Si膜(1
4)のソース領域(NS)はTFT領域のみならず、ゲ
ート絶縁膜(13)上を延在されて補助容量電極(1
2)の上方に重畳され、補助容量を構成している。
FIG. 1 is a sectional view of a display pixel portion of an LCD according to an embodiment of the present invention. Substrate (10)
A gate electrode (11) of a TFT made of Cr, Ti, Ta or the like, and an auxiliary capacitance electrode (1
2) is formed, and a gate insulating film (13) is formed to cover this. On the gate insulating film (13), p-S
The i film (14) is formed in an island shape of the TFT so as to pass above the gate electrode (11). In the p-Si film (14), a region immediately above the gate electrode (11) is a non-doped channel region (CH), and both sides of the channel region (CH) are lightly doped with N-type impurities such as phosphorus. A low concentration region (LD), and further outside, a source region (NS) doped with the same impurity at a high concentration.
And the drain region (ND), and the LDD (ligh
tly doped drain) structure. p-Si film (1
The source region (NS) of (4) extends not only in the TFT region but also on the gate insulating film (13) to form the auxiliary capacitance electrode (1).
It overlaps above 2) to form an auxiliary capacitance.

【0012】チャンネル領域(CH)の上には、低濃度
領域(LD)を形成する際に、イオン注入時のマスクと
して用いられた注入ストッパー(15)が残されてい
る。p−Si膜(14)を覆ってシリコン窒化膜、シリ
コン酸化膜等の層間絶縁膜(16)が形成され、層間絶
縁膜(16)上にはAl/Mo等のドレイン電極(1
7)及びソース電極(18)が形成され、各々層間絶縁
膜(16)に開口されたコンタクトホールを介して、p
−Si膜(14)のドレイン領域(ND)及びソース領
域(NS)に接続されている。これらドレイン電極(1
7)およびソース電極(18)を覆って、SOG、BP
SG、アクリル樹脂等の平坦化絶縁膜(19)が形成さ
れ、この平坦化絶縁膜(19)上にはITO(indium t
in oxide)、あるいは、Alからなる画素電極(20)
が形成され、平坦化絶縁膜(19)に開口されたコンタ
クトホールを介してソース電極(18)に接続されてい
る。この上には、ポリイミド等の垂直配向膜(45)が
形成されている。以上で、TFT基板が構成されてい
る。
On the channel region (CH), an implantation stopper (15) used as a mask for ion implantation when forming the low concentration region (LD) is left. An interlayer insulating film (16) such as a silicon nitride film or a silicon oxide film is formed so as to cover the p-Si film (14), and a drain electrode (1) such as Al / Mo is formed on the interlayer insulating film (16).
7) and a source electrode (18) are formed. Each of the source electrodes (18) is formed through a contact hole opened in the interlayer insulating film (16).
-Connected to the drain region (ND) and the source region (NS) of the Si film (14). These drain electrodes (1
7) and over the source electrode (18), SOG, BP
A flattening insulating film (19) made of SG, acrylic resin or the like is formed, and ITO (indium tint) is formed on the flattening insulating film (19).
in oxide) or pixel electrode made of Al (20)
Is formed and connected to the source electrode (18) via a contact hole opened in the planarization insulating film (19). On this, a vertical alignment film (45) such as polyimide is formed. Thus, the TFT substrate is configured.

【0013】このTFT基板(10)に対向する位置に
は、対向基板となる基板(30)が配置され、この基板
(30)上には、フィルムレジストからなるR、G、B
のカラーフィルター(31)が形成され、各々の画素電
極(20)に対応する位置に設けられている。また、カ
ラーフィルター(31)の間隙領域には、不透光性のフ
ィルムレジストからなるブラックマトリクス(32)が
設けられている。これらカラーフィルター(31)及び
ブラックマトリクス(32)の層上には、ITO等の共
通電極(33)が形成されている。共通電極(33)中
には、ITOの不在領域として形成された配向制御窓
(34)が設けられている。共通電極(33)上には、
基板(10)側と同じ垂直配向膜(46)が設けられて
いる。以上で、対向基板が構成されている。
At a position facing the TFT substrate (10), a substrate (30) serving as a counter substrate is arranged. On the substrate (30), R, G, and B made of a film resist are provided.
Are formed and provided at positions corresponding to the respective pixel electrodes (20). In the gap region of the color filter (31), a black matrix (32) made of an opaque film resist is provided. A common electrode (33) such as ITO is formed on the layers of the color filter (31) and the black matrix (32). In the common electrode (33), there is provided an orientation control window (34) formed as a region where no ITO exists. On the common electrode (33),
The same vertical alignment film (46) as the substrate (10) side is provided. Thus, the counter substrate is configured.

【0014】これらTFT基板(10)と対向基板(3
0)間には、負の誘電率異方性を有する液晶(40)が
装填されている。
The TFT substrate (10) and the counter substrate (3
Between 0), a liquid crystal (40) having a negative dielectric anisotropy is loaded.

【0015】この例において、共通電極(33)に設け
られた配向制御窓(34)は、初期状態即ち電圧無印加
時において、垂直配向された液晶分子(41)が、電圧
印加により傾斜する方角を分割する働きを有する。即
ち、画素電極(20)のエッジにおいて、斜め方向に生
ずる電界(42)に抗する方角に連続的に傾斜した液晶
分子(41)の境界が、配向制御窓(34)における弱
電界及び斜め電界(41)により固定されるものであ
る。また、TFT基板側の平坦化絶縁膜(19)は、画
素電極(20)の下地として平坦性を高める働きをし、
液晶(40)との界面の凹凸により、液晶分子(41)
の配向が乱れることを防ぎ、斜め電界(41)及び配向
制御窓(34)による制御性を有効にするものである。
In this example, the alignment control window (34) provided in the common electrode (33) has a direction in which the liquid crystal molecules (41) which are vertically aligned in the initial state, ie, when no voltage is applied, are inclined by the voltage application. Has the function of dividing That is, at the edge of the pixel electrode (20), the boundary of the liquid crystal molecules (41) continuously inclined in a direction against the electric field (42) generated in the oblique direction is formed by the weak electric field and the oblique electric field in the alignment control window (34). This is fixed by (41). Further, the flattening insulating film (19) on the TFT substrate side serves as a base for the pixel electrode (20) to enhance flatness,
Due to the unevenness of the interface with the liquid crystal (40), the liquid crystal molecules (41)
Is prevented from being disturbed, and the controllability by the oblique electric field (41) and the orientation control window (34) is made effective.

【0016】本発明では、p−Si膜(14)と補助容
量電極(12)及びゲート絶縁膜(13)からなる補助
容量CSCは、画素電極(20)と共通電極(33)及び
液晶(40)からなる液晶容量CLCとの間で、以下の関
係を満たすように設定される。
In the present invention, the auxiliary capacitance CSC comprising the p-Si film (14), the auxiliary capacitance electrode (12), and the gate insulating film (13) comprises the pixel electrode (20), the common electrode (33) and the liquid crystal (40). ) Are set so as to satisfy the following relationship.

【0017】まず、TN方式において、誘電率(ε⊥,
ε//)が(4.0,8.0)の液晶を用いた場合(誘電
率異方性は、Δε=4.0>0)、電圧無印加時(O
N)及び電圧印加時(OFF)における液晶容量CLC//
の比誘電率(ε(OFF),ε(ON))は(4.0,5.5)
となる。この時、|ε(ON)−ε(OFF)|=1.5であ
る。前述の如く、補助容量CSCは液晶容量CLCの0.2
倍であるので、液晶容量CLC//と補助容量CSCとの合成
容量CCOM//のON/OFF比は、
First, in the TN method, the dielectric constant (ε⊥,
When a liquid crystal having ε // of (4.0, 8.0) is used (dielectric anisotropy is Δε = 4.0> 0), when no voltage is applied (O
N) and the liquid crystal capacitance CLC // when voltage is applied (OFF)
Has a relative dielectric constant (ε (OFF), ε (ON)) of (4.0, 5.5)
Becomes At this time, | ε (ON) −ε (OFF) | = 1.5. As described above, the auxiliary capacitance CSC is 0.2% of the liquid crystal capacitance CLC.
Therefore, the ON / OFF ratio of the combined capacitance CCOM // of the liquid crystal capacitance CLC // and the auxiliary capacitance CSC is:

【0018】[0018]

【数4】 となる。(Equation 4) Becomes

【0019】液晶容量CLCがON時とOFF時とで異な
っていると、(2)式におけるΔVLCも異なる。例え
ば、(2)式における液晶容量CLCとして、CLC(ON)を
採用した時のΔVLCに基づいて対極電圧レベルを設定し
た場合、OFF期間において、ΔVLCは異なったものと
なるので、そのように対極電圧を設定しても、直流成分
を完全に消去することができない。しかしながら、補助
容量CSCを十分に大きく、合成容量のON/OFF比C
COM(ON)/CCOM(OFF)を(3)式により得られる程度の
小さな値にすれば、実際には、目立つほどの焼き付き現
象が発生することは防がれる。
If the liquid crystal capacitance CLC is different between ON and OFF, ΔVLC in equation (2) also differs. For example, when the counter electrode voltage level is set based on ΔVLC when CLC (ON) is adopted as the liquid crystal capacitance CLC in the equation (2), ΔVLC becomes different during the OFF period. Even if the voltage is set, the DC component cannot be completely eliminated. However, the auxiliary capacitance CSC is sufficiently large, and the ON / OFF ratio C
If COM (ON) / CCOM (OFF) is set to a value small enough to be obtained by the expression (3), a noticeable burn-in phenomenon can be prevented from actually occurring.

【0020】これに対して、本発明の垂直配向型LCD
において、液晶(40)として、誘電率(ε⊥,ε//)
が(8.0,4.0)で、誘電率異方性(Δε=−4.
0)が負のものを用いた場合、電圧印加時(ON)及び
電圧無印加時(OFF)における液晶容量CLC⊥の比誘
電率(ε(ON),ε(OFF))は(6.0,4.0)とな
る。この時、|ε(ON)−ε(OFF)|=2.0であり、T
Nの場合よりも大きい。このため、TNの場合と同様、
補助容量CSCが液晶容量CLCの0.2倍の設定のままだ
と、合成容量CCOM⊥のON/OFF比は、
On the other hand, the vertical alignment type LCD of the present invention
, The dielectric constant (ε⊥, ε //) as the liquid crystal (40)
Is (8.0, 4.0) and the dielectric anisotropy (Δε = −4.
When 0) is negative, the relative dielectric constant (ε (ON), ε (OFF)) of the liquid crystal capacitance CLC⊥ when a voltage is applied (ON) and when no voltage is applied (OFF) is (6.0). , 4.0). At this time, | ε (ON) −ε (OFF) | = 2.0, and T
It is larger than N. For this reason, as in the case of TN,
If the auxiliary capacitance CSC is set to be 0.2 times the liquid crystal capacitance CLC, the ON / OFF ratio of the combined capacitance CCOM # becomes

【0021】[0021]

【数5】 となり、TNの場合よりも大きくなる。この結果、
(2)式において、ON時とOFF時とで液晶容量CLC
の値の差が許容範囲を越えてしまい、ΔVLCのばらつき
が大きく、対極電圧レベルを調整しても、大きな残留直
流成分が生じ、焼き付き現象が発生する。
(Equation 5) And becomes larger than in the case of TN. As a result,
In the equation (2), the liquid crystal capacitance CLC between ON and OFF is calculated.
Is out of the permissible range, the variation in ΔVLC is large, and even if the counter electrode voltage level is adjusted, a large residual DC component is generated, and the burn-in phenomenon occurs.

【0022】このように、液晶の誘電率異方性Δεが同
じであるにも関わらず、TN型と垂直配向型とで違いが
生じるのは、|ε(ON)−ε(OFF)|値が、TN型と垂直
配向型とで異なることに起因する。しかしながら、垂直
配向型においても、合成容量CCOMのON/OFF比
が、TN型におけると同様、1.31、あるいは、それ
以下であることが好ましいことには変わりはない。従っ
て、補助容量CSCと液晶容量CLCとの比を以下の如く、
再設定することができる。
As described above, although the dielectric anisotropy Δε of the liquid crystal is the same, the difference between the TN type and the vertical alignment type is caused by the | ε (ON) −ε (OFF) | value. Is different between the TN type and the vertical alignment type. However, even in the vertical alignment type, the ON / OFF ratio of the combined capacitor CCOM is preferably 1.31 or less as in the TN type. Therefore, the ratio between the auxiliary capacitance CSC and the liquid crystal capacitance CLC is calculated as follows:
Can be reset.

【0023】[0023]

【数6】 が要求される。CLC⊥(OFF):CSC=1:Xとして、
(5)式を変形していくと、
(Equation 6) Is required. CLC⊥ (OFF): Assuming that CSC = 1: X
By transforming equation (5),

【0024】[0024]

【数7】 となり、これを解いて、(Equation 7) And solve this,

【0025】[0025]

【数8】 が得られる。(Equation 8) Is obtained.

【0026】このように、垂直配向型においては、補助
容量CSCを液晶容量CLC⊥(OFF)の0.61倍、あるい
は、それ以上とすることにより、液晶容量CLC⊥と補助
容量CSCの合成容量CCOMが十分りに大きくなるので、
液晶容量CLC⊥のON/OFF比が大きくなっても、Δ
VLCの変動幅が許容範囲内に収まるので、焼き付き現象
が生じることが防がれる。ただし、補助容量CSCが大き
くなると、合成容量CCOMが大きくなり、この結果、時
定数が大きくなって書き込みに要する時間が長くなる。
経験上、補助容量CSCの上限は、液晶容量CLC⊥の2倍
程度が適当である。従って、垂直配向型LCDにおける
補助容量CSCと液晶容量CLC⊥の関係は、
As described above, in the vertical alignment type, by setting the auxiliary capacitance CSC to be 0.61 times or more of the liquid crystal capacitance CLC⊥ (OFF) or more, the combined capacitance of the liquid crystal capacitance CLC⊥ and the auxiliary capacitance CSC is obtained. Because CCOM is big enough,
Even if the ON / OFF ratio of the liquid crystal capacitor CLC⊥ increases, Δ
Since the fluctuation range of VLC falls within the allowable range, the occurrence of the burn-in phenomenon is prevented. However, when the auxiliary capacitance CSC increases, the combined capacitance CCOM increases, and as a result, the time constant increases and the time required for writing increases.
From experience, it is appropriate that the upper limit of the auxiliary capacitance CSC is about twice the liquid crystal capacitance CLC #. Therefore, the relationship between the auxiliary capacitance CSC and the liquid crystal capacitance CLC # in the vertical alignment type LCD is as follows.

【0027】[0027]

【数9】 (Equation 9)

【0028】[0028]

【発明の効果】以上の説明から明らかな如く、本発明に
より、垂直配向型液晶表示装置の補助容量を、電圧無印
加時の液晶容量の0.61倍以上に設定することによ
り、交流駆動における残留直流成分のばらつきを抑え、
焼き付きを防止することができた。
As is apparent from the above description, according to the present invention, by setting the auxiliary capacitance of the vertical alignment type liquid crystal display device to be 0.61 times or more of the liquid crystal capacitance when no voltage is applied, it is possible to reduce the AC driving. Reduces the variation of the residual DC component,
Seizure could be prevented.

【図面の簡単な説明】[Brief description of the drawings]

【図1】本発明の実施の形態かかる垂直配向型液晶表示
装置の断面図である。
FIG. 1 is a sectional view of a vertical alignment type liquid crystal display device according to an embodiment of the present invention.

【図2】液晶表示装置の等価回路図である。FIG. 2 is an equivalent circuit diagram of the liquid crystal display device.

【符号の説明】[Explanation of symbols]

1 ゲートライン 2 ドレインライン 3 TFT 4 液晶容量 5 補助容量 10,30 基板 11 ゲート電極 13 p−Si 17 ドレイン電極 18 ソース電極 19 平坦化絶縁膜 20 画素電極 31 カラーフィルター 33 共通電極 34 配向制御電極 40 液晶層 41 液晶分子 42 電界 45,46 垂直配向膜 DESCRIPTION OF SYMBOLS 1 Gate line 2 Drain line 3 TFT 4 Liquid crystal capacitance 5 Auxiliary capacitance 10, 30 Substrate 11 Gate electrode 13 p-Si 17 Drain electrode 18 Source electrode 19 Flattening insulating film 20 Pixel electrode 31 Color filter 33 Common electrode 34 Alignment control electrode 40 Liquid crystal layer 41 Liquid crystal molecules 42 Electric field 45, 46 Vertical alignment film

Claims (1)

【特許請求の範囲】[Claims] 【請求項1】 対向面に液晶駆動用の電極が形成された
一対の基板間に液晶が封入され、画素毎に液晶の初期配
向を基板に対して垂直方向に制御した液晶容量と、該液
晶容量に並列に接続された補助容量が形成されてなる垂
直配向型液晶表示装置において、 前記液晶容量CLCと補助容量CSCとは、 【数1】 の関係を満たすことを特徴とする垂直配向型液晶表示装
置。
A liquid crystal is sealed between a pair of substrates having liquid crystal driving electrodes formed on opposing surfaces, and a liquid crystal capacitor in which initial alignment of liquid crystal is controlled in a direction perpendicular to the substrate for each pixel; In a vertical alignment type liquid crystal display device in which an auxiliary capacitance connected in parallel with a capacitance is formed, the liquid crystal capacitance CLC and the auxiliary capacitance CSC are expressed as follows. A vertical alignment type liquid crystal display device characterized by satisfying the following relationship:
JP10146331A 1998-05-27 1998-05-27 Vertical alignment type liquid crystal display device Pending JPH11337963A (en)

Priority Applications (1)

Application Number Priority Date Filing Date Title
JP10146331A JPH11337963A (en) 1998-05-27 1998-05-27 Vertical alignment type liquid crystal display device

Applications Claiming Priority (1)

Application Number Priority Date Filing Date Title
JP10146331A JPH11337963A (en) 1998-05-27 1998-05-27 Vertical alignment type liquid crystal display device

Publications (1)

Publication Number Publication Date
JPH11337963A true JPH11337963A (en) 1999-12-10

Family

ID=15405279

Family Applications (1)

Application Number Title Priority Date Filing Date
JP10146331A Pending JPH11337963A (en) 1998-05-27 1998-05-27 Vertical alignment type liquid crystal display device

Country Status (1)

Country Link
JP (1) JPH11337963A (en)

Cited By (4)

* Cited by examiner, † Cited by third party
Publication number Priority date Publication date Assignee Title
US7847907B2 (en) 2006-05-24 2010-12-07 Samsung Electronics Co., Ltd. Display substrate, method of fabricating the same, and liquid crystal display device having the same
US8134669B2 (en) * 2005-03-31 2012-03-13 Sharp Kabushiki Kaisha Liquid crystal display device
JPWO2013061929A1 (en) * 2011-10-27 2015-04-02 シャープ株式会社 Liquid crystal display element and liquid crystal display device
JP2020013155A (en) * 2010-03-26 2020-01-23 株式会社半導体エネルギー研究所 Liquid crystal display

Citations (3)

* Cited by examiner, † Cited by third party
Publication number Priority date Publication date Assignee Title
JPH05203994A (en) * 1991-09-24 1993-08-13 Toshiba Corp Liquid crystal display device
JPH07120786A (en) * 1993-10-25 1995-05-12 Oki Electric Ind Co Ltd Active matrix type liquid crystal panel
JPH11212107A (en) * 1998-01-26 1999-08-06 Matsushita Electric Ind Co Ltd Active matrix type liquid crystal display device, its driving method and manufacture

Patent Citations (3)

* Cited by examiner, † Cited by third party
Publication number Priority date Publication date Assignee Title
JPH05203994A (en) * 1991-09-24 1993-08-13 Toshiba Corp Liquid crystal display device
JPH07120786A (en) * 1993-10-25 1995-05-12 Oki Electric Ind Co Ltd Active matrix type liquid crystal panel
JPH11212107A (en) * 1998-01-26 1999-08-06 Matsushita Electric Ind Co Ltd Active matrix type liquid crystal display device, its driving method and manufacture

Cited By (4)

* Cited by examiner, † Cited by third party
Publication number Priority date Publication date Assignee Title
US8134669B2 (en) * 2005-03-31 2012-03-13 Sharp Kabushiki Kaisha Liquid crystal display device
US7847907B2 (en) 2006-05-24 2010-12-07 Samsung Electronics Co., Ltd. Display substrate, method of fabricating the same, and liquid crystal display device having the same
JP2020013155A (en) * 2010-03-26 2020-01-23 株式会社半導体エネルギー研究所 Liquid crystal display
JPWO2013061929A1 (en) * 2011-10-27 2015-04-02 シャープ株式会社 Liquid crystal display element and liquid crystal display device

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