JPH05328163A - Display device - Google Patents

Display device

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Publication number
JPH05328163A
JPH05328163A JP13468692A JP13468692A JPH05328163A JP H05328163 A JPH05328163 A JP H05328163A JP 13468692 A JP13468692 A JP 13468692A JP 13468692 A JP13468692 A JP 13468692A JP H05328163 A JPH05328163 A JP H05328163A
Authority
JP
Japan
Prior art keywords
circuit
output
display device
counting
period
Prior art date
Legal status (The legal status is an assumption and is not a legal conclusion. Google has not performed a legal analysis and makes no representation as to the accuracy of the status listed.)
Pending
Application number
JP13468692A
Other languages
Japanese (ja)
Inventor
Yoshikazu Fukuhara
義和 福原
Yasunori Okita
康範 沖田
Current Assignee (The listed assignees may be inaccurate. Google has not performed a legal analysis and makes no representation or warranty as to the accuracy of the list.)
Panasonic Holdings Corp
Original Assignee
Matsushita Electric Industrial Co Ltd
Priority date (The priority date is an assumption and is not a legal conclusion. Google has not performed a legal analysis and makes no representation as to the accuracy of the date listed.)
Filing date
Publication date
Application filed by Matsushita Electric Industrial Co Ltd filed Critical Matsushita Electric Industrial Co Ltd
Priority to JP13468692A priority Critical patent/JPH05328163A/en
Publication of JPH05328163A publication Critical patent/JPH05328163A/en
Pending legal-status Critical Current

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Abstract

PURPOSE:To obtain the display device in which a digital trapezoidal distortion correction circuit is adopted to improve the accuracy, the circuit is integrated through the adoption of gate arrays and the control by key operation is attained. CONSTITUTION:The display device is made up of a period discrimination circuit 21 counting 0 to M-1 of a vertical synchronizing signal based on a reference clock to discriminate the period, a period/N generating circuit 22 generating a 2nd clock being 1/N division of the period of the period discrimination circuit 21, a fixed counter circuit 23 counting 0 to N-1 by the 2nd clock, D/A converter circuits 25, 26 converting an output of the fixed counter circuit 23 into an analog signal to correct trapezoidal distortion with high accuracy by digital control. As a result, the accuracy is improved by digital processing and the key operation control is implemented and the circuit is integrated by adoption of gate arrays and then the cost is reduced.

Description

【発明の詳細な説明】Detailed Description of the Invention

【0001】[0001]

【産業上の利用分野】本発明は、テレビやディスプレイ
等のモニター受像機に有効な台形歪み補正を行うことの
できる表示装置に関するものである。
BACKGROUND OF THE INVENTION 1. Field of the Invention The present invention relates to a display device capable of performing trapezoidal distortion correction effective for monitor receivers such as televisions and displays.

【0002】[0002]

【従来の技術】ディスプレイ等の表示装置において、撮
像管内の電気像を走査したり、受像管の蛍光面を走査し
てラスターを作るには、受像管の電子ビームを水平及び
垂直方向に偏向させる為のコイルを設け、これに図4
(a)に示すようなのこぎり波電流を流して電磁偏向を
行っている。
2. Description of the Related Art In a display device such as a display, in order to scan an electric image in an image pickup tube or a fluorescent surface of a picture tube to form a raster, an electron beam of the picture tube is deflected in horizontal and vertical directions. A coil for
A sawtooth wave current as shown in (a) is passed to perform electromagnetic deflection.

【0003】この電流は図4(b)に示すように、垂直
方向の偏向電流が画面を上下に走査する期間に、水平方
向の偏向電流は画面の水平方向の振幅が左右方向全て一
定になるように垂直偏向の周期でパラボラ波状の振幅変
調が行なわれ図4(c)に示すような画面が得られる。
しかしながら、垂直偏向コイルの磁界分布が不均衡であ
ったり、電子ビームの機何学的中心点がずれていると、
図4(d)に示すような画面の状態となり台形歪みが発
生する。
As shown in FIG. 4B, the horizontal deflection current has a constant horizontal amplitude in the horizontal direction while the vertical deflection current scans the screen vertically. As described above, the parabolic wave-like amplitude modulation is performed in the vertical deflection cycle, and a screen as shown in FIG. 4C is obtained.
However, if the magnetic field distribution of the vertical deflection coil is unbalanced or the mechanical center point of the electron beam is deviated,
The screen becomes as shown in FIG. 4D, and trapezoidal distortion occurs.

【0004】この台形歪みを補正する為、従来は、図5
に示されるような回路が用いられていた。図5におい
て、51は水平偏向電源回路、52は水平偏向出力回
路、53は水平偏向コイル、54は極性が異なる垂直の
こぎり波電圧の両波形を加算する加算回路、55は垂直
のこぎり波電圧の極性を変え、利得を可変する利得可変
反転回路、56は垂直偏向出力回路、57は垂直偏向コ
イル、58は結合コンデンサ、59は垂直のこぎり波電
圧波形をとりだす為の抵抗である。
Conventionally, in order to correct this trapezoidal distortion, FIG.
The circuit shown in was used. In FIG. 5, reference numeral 51 is a horizontal deflection power supply circuit, 52 is a horizontal deflection output circuit, 53 is a horizontal deflection coil, 54 is an adder circuit for adding both waveforms of vertical sawtooth wave voltages having different polarities, and 55 is the polarity of the vertical sawtooth wave voltage. , 56 is a vertical deflection output circuit, 57 is a vertical deflection coil, 58 is a coupling capacitor, and 59 is a resistor for extracting a vertical sawtooth wave voltage waveform.

【0005】以上のように構成された表示装置のアナロ
グの台形歪み補正制御回路について、その動作を説明す
る。まず、垂直偏向出力回路56が動作すると、垂直の
こぎり波電流が垂直偏向コイル57に流れ、抵抗59に
は垂直偏向のこぎり波電圧が得られる。その垂直偏向の
こぎり波電圧を加算回路54によって、極性の異なり、
かつ出力振幅が可変可能な利得可変反転回路55ののこ
ぎり波出力と加算する。この時、利得可変反転回路55
の出力振幅は振幅及び位相を図6(a)に示すようにコ
ントロールする。そして、水平偏向電源回路51の電源
電圧を図6(b)に示すように加算回路54の出力波形
で変調し、水平偏向電流を図6(c)に示すように変調
させる。この結果、垂直偏向コイル57の磁界分布の不
均衡や電子ビームの幾何学中心がずれていることにより
発生する図4(d)に示すような画面の台形歪みが補正
され、図4(c)に示すような歪みのない画面が得られ
る。
The operation of the analog trapezoidal distortion correction control circuit of the display device configured as described above will be described. First, when the vertical deflection output circuit 56 operates, a vertical sawtooth wave current flows through the vertical deflection coil 57, and a vertical deflection sawtooth wave voltage is obtained at the resistor 59. The vertical deflection sawtooth wave voltage is added by the adder circuit 54 with different polarities,
In addition, the output is added to the sawtooth wave output of the variable gain inverting circuit 55 whose output amplitude is variable. At this time, the variable gain inverting circuit 55
The output amplitude of is controlled in amplitude and phase as shown in FIG. 6 (a). Then, the power supply voltage of the horizontal deflection power supply circuit 51 is modulated by the output waveform of the adder circuit 54 as shown in FIG. 6B, and the horizontal deflection current is modulated as shown in FIG. 6C. As a result, the trapezoidal distortion of the screen as shown in FIG. 4D caused by the imbalance of the magnetic field distribution of the vertical deflection coil 57 and the deviation of the geometric center of the electron beam is corrected, and FIG. A distortion-free screen as shown in is obtained.

【0006】しかしながら、この様な従来の補正方法で
は、垂直偏向のこぎり波電流が受像管の蛍光面での画像
の直線性が確保される様動作するため、抵抗59の両端
電圧波形は、実際には図7(b)に示すように直線性が
損なわれている。従って、水平偏向電流及び画面は、図
7(c)に示すような状態となり、完全な台形歪み補正
が行なわれていない。
However, in such a conventional correction method, since the sawtooth wave current of vertical deflection operates so as to ensure the linearity of the image on the fluorescent screen of the picture tube, the voltage waveform across the resistor 59 is actually Has impaired linearity as shown in FIG. Therefore, the horizontal deflection current and the screen are in a state as shown in FIG. 7C, and complete trapezoidal distortion correction is not performed.

【0007】この図7(b)のように波形の直線性が損
なわれている理由は、図7(a)に示すように、受像管
のほぼ平面上の蛍光面において、同じ偏向角度θに対し
て管面中心部分より周辺部分のほうが電子ビーム移動量
が大きく、この歪みを補正し、画像の直線性を確保する
為に、図7(b)に示すように管面周辺での偏向量を少
なくするようなS字補正の垂直偏向電流を流しているか
らである。
The reason why the linearity of the waveform is impaired as shown in FIG. 7B is that, as shown in FIG. 7A, the same deflection angle .theta. On the other hand, the amount of electron beam movement in the peripheral portion is larger than that in the central portion of the tube surface, and in order to correct this distortion and ensure the linearity of the image, as shown in FIG. This is because the vertical deflection current for S-shaped correction that reduces

【0008】[0008]

【発明が解決しようとする課題】しかしながら上記従来
の表示装置の台形歪み補正では、垂直偏向出力回路の波
形を抽出して三角波を得て水平偏向を行っているが、こ
の三角波は、理想的な三角波ではなく完全な台形歪み補
正が出来ないと共に、ユーザーコントロールがキー操作
となっているデジタル方式の制御方式には対応が困難で
あった。本発明は上記従来の問題点を解決するもので、
理想的な台形歪み補正を可能にすると共に、デジタル方
式の制御に対応し、ゲートアレイ等のカスタムIcへの
集積化のできる表示装置を提供することを目的とする。
However, in the above-mentioned conventional trapezoidal distortion correction of the display device, the waveform of the vertical deflection output circuit is extracted to obtain a triangular wave for horizontal deflection. This triangular wave is ideal. It was not possible to completely correct the trapezoidal distortion instead of the triangular wave, and it was difficult to support the digital control method in which the user controls were key operations. The present invention solves the above-mentioned conventional problems,
It is an object of the present invention to provide a display device that enables ideal trapezoidal distortion correction, is compatible with digital control, and can be integrated into a custom Ic such as a gate array.

【0009】[0009]

【課題を解決するための手段】この目的を達成するため
に本発明の表示装置は、テレビやディスプレイ等のモニ
ター受像機に入力される同期信号の間隔を基準クロック
でカウントする第1の計数手段と、この第1の計数手段
の出力値をN分割した周期のクロックを発生する分周手
段と、分周手段からの出力を0〜N−1までカウントす
る第2の計数手段と、第2の計数手段の出力値をアナロ
グに変換する変換手段とを備えた。
In order to achieve this object, the display device of the present invention is a first counting means for counting the interval of the synchronizing signal input to a monitor receiver such as a television or a display with a reference clock. A frequency dividing means for generating a clock having a period obtained by dividing the output value of the first counting means by N; a second counting means for counting the output from the frequency dividing means from 0 to N-1; And a conversion means for converting the output value of the counting means into an analog value.

【0010】[0010]

【作用】この構成によって、精度のよい三角波を得るこ
とができ、台形歪み補正用波形の直線性が大幅に向上す
るとともに、ゲートアレイによる回路の集積化も図るこ
とが可能となる。
With this structure, a highly accurate triangular wave can be obtained, the linearity of the trapezoidal distortion correcting waveform is significantly improved, and the circuit can be integrated by the gate array.

【0011】[0011]

【実施例】以下、本発明の一実施例について図面を参照
しながら説明する。
DETAILED DESCRIPTION OF THE PREFERRED EMBODIMENTS An embodiment of the present invention will be described below with reference to the drawings.

【0012】図1は本発明の一実施例における表示装置
の全体を示すブロック図である。図1において、1は
R,G,Bのビデオ信号の振幅や輝度を変化させる事に
より画面の輝度や色を変化させる信号処理回路、2は水
平同期信号(H)、垂直同期信号(V)の同期信号入力
状態を判別、処理し、各ブロックへ送りだす同期信号処
理回路、3は電子ビームを垂直方向に偏向させる為の垂
直のこぎり波電流を発生する垂直偏向回路、4は電子ビ
ームを水平方向に偏向させる為の水平のこぎり波電流を
発生する水平偏向回路、5は台形歪みを補正する為の補
正波形である三角波を発生するデジタル三角波発生回
路、6は電子ビームを発射する電子銃であり、7は電子
ビームを水平及び垂直方向に偏向させる為の偏向コイ
ル、8は、電気信号を光の変化に変えて蛍光面に映し出
すブラウン管である。
FIG. 1 is a block diagram showing an entire display device according to an embodiment of the present invention. In FIG. 1, 1 is a signal processing circuit that changes the brightness and color of the screen by changing the amplitude and brightness of the R, G, and B video signals, and 2 is a horizontal sync signal (H) and a vertical sync signal (V). The synchronous signal processing circuit that determines and processes the input state of the synchronous signal and sends it out to each block. 3 is a vertical deflection circuit that generates a vertical sawtooth current for deflecting the electron beam in the vertical direction. , A horizontal deflection circuit for generating a horizontal sawtooth wave current for deflecting the laser beam, a digital triangular wave generation circuit 5 for generating a triangular wave that is a correction waveform for correcting trapezoidal distortion, and an electron gun 6 for emitting an electron beam, Reference numeral 7 is a deflection coil for deflecting the electron beam in the horizontal and vertical directions, and 8 is a cathode ray tube for converting an electric signal into a change in light and displaying it on a fluorescent screen.

【0013】図2は本発明の一実施例における表示装置
の台形歪みデジタル制御回路の詳細なブロック図であ
る。図2において、21はテレビやディスプレイ等の表
示装置の垂直回路に入力される垂直同期信号の周期を基
準クロックで0〜M−1 までカウントして周期の長さを
判別する周期判別回路、22は周期判別回路21の周期
をN分割した周期の第2のクロックを発生する周期/N
発生回路、23は周期/N発生回路22から出力される
第2のクロックを0〜N−1 までカウントする固定カウ
ンタ回路、24は固定カウンタ回路23の出力を反転す
るインバータ回路、25、26は固定カウンタ回路23
及びインバータ回路24の出力をアナログに変換するD
/A変換回路、27、28はD/A変換回路25及び2
6の出力を増幅する反転増幅回路、29は反転増幅回路
27の増幅度を可変する出力レベルコントロール回路、
30は反転増幅回路27及び28の出力波形を加算する
加算回路、31は水平偏向電源回路、22は水平偏向出
力回路、33は水平偏向コイルである。
FIG. 2 is a detailed block diagram of the trapezoidal distortion digital control circuit of the display device according to the embodiment of the present invention. In FIG. 2, reference numeral 21 denotes a cycle discriminating circuit that discriminates the length of the cycle by counting the cycle of a vertical synchronizing signal input to a vertical circuit of a display device such as a television or a display from 0 to M−1 with a reference clock, and 22. Is the cycle of generating the second clock having a cycle obtained by dividing the cycle of the cycle determination circuit 21 by N / N
A generation circuit, 23 is a fixed counter circuit that counts the second clock output from the cycle / N generation circuit 22 from 0 to N−1, 24 is an inverter circuit that inverts the output of the fixed counter circuit 23, and 25 and 26 are Fixed counter circuit 23
And D for converting the output of the inverter circuit 24 into analog
A / A conversion circuits 27 and 28 are D / A conversion circuits 25 and 2
An inverting amplifier circuit for amplifying the output of 6, an output level control circuit 29 for varying the amplification degree of the inverting amplifier circuit 27,
Reference numeral 30 is an adder circuit for adding the output waveforms of the inverting amplifier circuits 27 and 28, 31 is a horizontal deflection power supply circuit, 22 is a horizontal deflection output circuit, and 33 is a horizontal deflection coil.

【0014】以上のように構成された表示装置の台形歪
みデジタル制御回路について、その動作を説明する。ま
ず、周期判別回路21は、表示装置の同期信号処理回路
2から出力される図3(a)に示すような垂直同期信号
の立下がりエッジでリセットされ、基準クロックにより
垂直同期信号区間を図3(b)に示すように0〜M−1
までカウントし、このカウント値Mをラッチすることに
より垂直同期信号の周期の長さを判別する。次に周期/
N発生回路22において、基準クロックをM/N分周す
ることにより、図3(c)に示すような第2のクロック
を発生させる。固定カウンタ回路23は、垂直同期信号
の立ち下りエッジでリセットされ、周期/N発生回路2
2で発生した第2のクロックを図3(d)に示すように
0〜N−1までカウントする。このカウントされた出力
波形はD/A変換回路25でアナログに変換され、フィ
ルターを通すと、図3(e)に示すようなリニアな三角
波の波形が得られる。同様にして、インバータ回路2
4、D/A変換回路26により逆三角波の波形が得られ
る。
The operation of the trapezoidal distortion digital control circuit of the display device constructed as described above will be described. First, the cycle determining circuit 21 is reset at the falling edge of the vertical synchronizing signal output from the synchronizing signal processing circuit 2 of the display device as shown in FIG. 0 to M-1 as shown in (b)
By counting up to M and latching the count value M, the period length of the vertical synchronizing signal is determined. Next cycle /
In the N generation circuit 22, the reference clock is divided by M / N to generate a second clock as shown in FIG. The fixed counter circuit 23 is reset at the falling edge of the vertical synchronization signal, and the cycle / N generation circuit 2
The second clock generated in 2 is counted from 0 to N-1 as shown in FIG. The counted output waveform is converted into an analog signal by the D / A conversion circuit 25 and filtered to obtain a linear triangular wave waveform as shown in FIG. Similarly, the inverter circuit 2
4, the D / A conversion circuit 26 obtains an inverted triangular waveform.

【0015】このD/A変換回路25とD/A変換回路
26より出力された各々の波形は反転増幅回路27、反
転増幅回路28でそれぞれ反転増幅される。この反転増
幅回路27、反転増幅回路28の増幅率は反転増幅回路
28をA倍とすると、反転増幅回路27は出力レベルコ
ントロール回路29によりDCコントロールされ、0〜
2A倍まで可変することができる。そしてこの反転増幅
回路27、反転増幅回路28の出力は加算回路30で加
算され、この加算回路30からの出力波形は、反転増幅
回路27の増幅率により反転増幅回路28から出力され
る増幅率A倍の出力波形から反転増幅回路27から出力
される増幅率−A倍までの範囲で可変することのできる
三角波が得られる。そして従来と同様に、水平偏向電源
回路31の電源電圧を図6(b)の様に加算回路30の
出力波形で変調し、水平偏向電流を図6(c)の様に変
調させる。この結果、図4(c)の画面状態となる様、
台形歪みを制御することができる。
The respective waveforms output from the D / A conversion circuit 25 and the D / A conversion circuit 26 are inverted and amplified by the inverting amplifier circuit 27 and the inverting amplifier circuit 28, respectively. The amplification factors of the inverting amplification circuit 27 and the inverting amplification circuit 28 are DC-controlled by the output level control circuit 29 when the inverting amplification circuit 28 is multiplied by A times, and 0 to 0
It can be changed up to 2A. The outputs of the inverting amplifier circuit 27 and the inverting amplifier circuit 28 are added by the adder circuit 30, and the output waveform from the adder circuit 30 has an amplification factor A output from the inverting amplification circuit 28 according to the amplification factor of the inverting amplification circuit 27. A triangular wave that can be varied in the range from the double output waveform to the amplification factor −A times output from the inverting amplifier circuit 27 is obtained. Then, as in the conventional case, the power supply voltage of the horizontal deflection power supply circuit 31 is modulated by the output waveform of the adding circuit 30 as shown in FIG. 6B, and the horizontal deflection current is modulated as shown in FIG. 6C. As a result, the screen state of FIG.
The trapezoidal distortion can be controlled.

【0016】この台形歪み補正の精度は、補正波形であ
る三角波の直線性により差が生じる。よってデジタル制
御による三角波図3(e)と従来のアナログ制御による
三角波図7(b)との直線性を比較するとデジタル制御
は従来のアナログ制御に比べ直線性がすぐれていると共
に、デジタル制御では、従来のように他の回路で生じた
三角波を用いるのではなく独立した回路で三角波を得る
ことができるので数段優れた画像を得ることが可能とな
る。
The accuracy of this trapezoidal distortion correction depends on the linearity of the triangular wave which is the correction waveform. Therefore, comparing the linearity of the triangular wave diagram 3 (e) of the digital control with the triangular wave diagram 7 (b) of the conventional analog control, the digital control is superior in linearity to the conventional analog control. Since a triangular wave can be obtained by an independent circuit instead of using a triangular wave generated in another circuit as in the conventional case, it is possible to obtain an image that is several steps superior.

【0017】[0017]

【発明の効果】以上のように本発明は、同期信号の間隔
を基準クロックでカウントする第1の計数手段と、この
第1の計数手段の出力値をN分割する分周手段と、この
分周手段からの出力を0〜N−1 までカウントする第2
の計数手段と、第2の計数手段の出力値をアナログに変
換する変換手段とを備えたことにより、精度の良い三角
波を得ることができ、台形歪み補正用波形の直線性を大
幅に向上させ、画像の歪みをなくすことが可能となると
ともに、ゲートアレイによる回路の集積化を図ることが
できる。
As described above, according to the present invention, the first counting means for counting the interval of the synchronizing signal with the reference clock, the frequency dividing means for dividing the output value of the first counting means into N, and this division. The second that counts the output from the peripheral means from 0 to N-1
By providing the counting means and the converting means for converting the output value of the second counting means to analog, a highly accurate triangular wave can be obtained, and the linearity of the trapezoidal distortion correction waveform is significantly improved. The image distortion can be eliminated, and the circuit can be integrated by the gate array.

【図面の簡単な説明】[Brief description of drawings]

【図1】本発明の一実施例における表示装置の全体を示
すブロック図
FIG. 1 is a block diagram showing an entire display device according to an embodiment of the present invention.

【図2】本発明の一実施例における表示装置の台形歪み
デジタル制御回路のブロック図
FIG. 2 is a block diagram of a trapezoidal distortion digital control circuit of a display device according to an embodiment of the present invention.

【図3】(a)は本発明の一実施例における表示装置の
同期信号処理回路からの出力波形図 (b)は本発明の一実施例における表示装置の同期判別
回路からの出力波形図 (c)は本発明の一実施例における表示装置の周期/N
発生回路からの出力波形図 (d)は本発明の一実施例における表示装置の固定カウ
ンタ回路からの出力波形図 (e)は本発明の一実施例における表示装置のD/A変
換回路からの出力波形図
FIG. 3A is an output waveform diagram from a sync signal processing circuit of a display device according to an embodiment of the present invention. FIG. 3B is an output waveform diagram from a synchronization determination circuit of a display device according to an embodiment of the present invention. c) is the period / N of the display device in one embodiment of the present invention
Output waveform diagram from the generation circuit (d) is an output waveform diagram from the fixed counter circuit of the display device in one embodiment of the present invention. (E) is a D / A conversion circuit of the display device in one embodiment of the present invention. Output waveform diagram

【図4】(a)は表示装置の画面と偏向電流との関係を
示す図 (b)は表示装置の垂直方向の偏向電流と水平方向の偏
向電流との関係を示す図 (c)は表示装置の歪みのない画面の状態を示す図 (d)は表示装置の台形歪みが発生した画面の状態を示
す図
FIG. 4A is a diagram showing the relationship between the screen of the display device and the deflection current. FIG. 4B is a diagram showing the relationship between the vertical deflection current and the horizontal deflection current of the display device. The figure showing the state of the screen without distortion of the device. (D) shows the state of the screen with the trapezoidal distortion of the display device.

【図5】従来の表示装置のアナログの台形歪み補正制御
回路図
FIG. 5 is an analog trapezoidal distortion correction control circuit diagram of a conventional display device.

【図6】(a)は従来の表示装置の利得可変反転回路の
出力波形図 (b)は従来の表示装置の加算回路の出力波形図 (c)は従来の表示装置の水平偏向電流の波形図
6A is an output waveform diagram of a variable gain inverting circuit of a conventional display device, FIG. 6B is an output waveform diagram of an adding circuit of the conventional display device, and FIG. 6C is a waveform of a horizontal deflection current of the conventional display device. Figure

【図7】(a)は従来の表示装置の受像管の偏向角度と
電子ビーム移動量との関係図 (b)は従来の表示装置の垂直のこぎり波電圧波形をと
りだす抵抗の両端電圧波形図 (c)は従来の表示装置の偏向電流と画面との関係を示
す図
FIG. 7A is a relationship diagram between a deflection angle of a picture tube of a conventional display device and an electron beam moving amount. FIG. 7B is a voltage waveform diagram of both ends of a resistor for extracting a vertical sawtooth voltage waveform of the conventional display device. FIG. 3C is a diagram showing the relationship between the deflection current of the conventional display device and the screen.

【符号の説明】 1 信号処理回路 2 同期処理回路 3 垂直偏向回路 4 水平偏向回路 5 デジタル三角波発生回路 6 電子銃 7 偏向コイル 8 ブラウン管 21 周期判別回路 22 周期/N発生回路 23 固定カウンタ回路 24 インバータ回路 25、26 D/A変換回路 27、28 反転増幅回路 29 出力レベルコントロール回路 30 加算回路 31 水平偏向電源回路 32 水平偏向出力回路 33 水平偏向コイル 51 水平偏向電源回路 52 水平偏向出力回路 53 水平偏向コイル 54 加算回路 55 利得可変反転回路 56 垂直偏向出力回路 57 垂直偏向コイル 58 コンデンサ 59 抵抗[Description of symbols] 1 signal processing circuit 2 synchronization processing circuit 3 vertical deflection circuit 4 horizontal deflection circuit 5 digital triangular wave generation circuit 6 electron gun 7 deflection coil 8 cathode ray tube 21 cycle determination circuit 22 cycle / N generation circuit 23 fixed counter circuit 24 inverter Circuits 25, 26 D / A conversion circuits 27, 28 Inversion amplification circuits 29 Output level control circuits 30 Adder circuits 31 Horizontal deflection power supply circuits 32 Horizontal deflection output circuits 33 Horizontal deflection coils 51 Horizontal deflection power supply circuits 52 Horizontal deflection output circuits 53 Horizontal deflection Coil 54 Adder circuit 55 Variable gain inverting circuit 56 Vertical deflection output circuit 57 Vertical deflection coil 58 Capacitor 59 Resistance

Claims (2)

【特許請求の範囲】[Claims] 【請求項1】基準クロックを発生する基準クロック発生
手段と、入力される同期信号を基準とし、前記基準クロ
ック発生手段より出力される基準クロックを次の同期信
号が入力されるまでカウントする第1の計数手段と、こ
の第1の計数手段の出力値を所定の数で分割した周期の
クロックを出力する分周手段と、入力される同期信号を
基準とし前記分周手段からの出力を次の同期信号が入力
されるまでカウントとする第2の計数手段と、前記第2
の計数手段からの出力値をアナログに変換する変換手段
とを備えたことを特徴とする表示装置。
1. A first reference clock generating means for generating a reference clock, and a reference clock output from said reference clock generating means as a reference, counting the reference clock output until the next synchronizing signal is input. Counting means, a frequency dividing means for outputting a clock having a cycle obtained by dividing the output value of the first counting means by a predetermined number, and an output from the frequency dividing means based on the input synchronization signal. Second counting means for counting until a synchronization signal is input;
And a conversion means for converting the output value from the counting means of FIG.
【請求項2】同期信号が垂直同期信号であり、変換手段
から出力された信号を増幅し、水平偏向回路の電源電圧
を変調することを特徴とする請求項1記載の表示装置。
2. The display device according to claim 1, wherein the synchronizing signal is a vertical synchronizing signal, and the signal output from the converting means is amplified to modulate the power supply voltage of the horizontal deflection circuit.
JP13468692A 1992-05-27 1992-05-27 Display device Pending JPH05328163A (en)

Priority Applications (1)

Application Number Priority Date Filing Date Title
JP13468692A JPH05328163A (en) 1992-05-27 1992-05-27 Display device

Applications Claiming Priority (1)

Application Number Priority Date Filing Date Title
JP13468692A JPH05328163A (en) 1992-05-27 1992-05-27 Display device

Publications (1)

Publication Number Publication Date
JPH05328163A true JPH05328163A (en) 1993-12-10

Family

ID=15134207

Family Applications (1)

Application Number Title Priority Date Filing Date
JP13468692A Pending JPH05328163A (en) 1992-05-27 1992-05-27 Display device

Country Status (1)

Country Link
JP (1) JPH05328163A (en)

Cited By (1)

* Cited by examiner, † Cited by third party
Publication number Priority date Publication date Assignee Title
US6424103B2 (en) 2000-05-25 2002-07-23 Mitsubishi Denki Kabushiki Kaisha Deflection-distortion correcting circuit

Cited By (1)

* Cited by examiner, † Cited by third party
Publication number Priority date Publication date Assignee Title
US6424103B2 (en) 2000-05-25 2002-07-23 Mitsubishi Denki Kabushiki Kaisha Deflection-distortion correcting circuit

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