JPS6248431B2 - - Google Patents

Description

[Detailed description of the invention]

The present invention relates to automatic S-correction circuits for use in raster scanning deflection circuits, particularly resonant scanning deflection circuits. Display devices with large and relatively flat screens, such as cathode ray tubes (CRTs), use electromagnetic deflection means to deflect the electron beam emitted from the electron gun before it reaches the phosphor screen. Use a yoke. To deflect the electron beam,
A relatively linear gradient or sawtooth signal is applied to the deflection coil. However, the unit deflection amount of the electron beam on the phosphor screen (face plate) for a unit deflection current value supplied to the deflection coil increases as the deflection angle with respect to the tube axis of the CRT increases. This is because the closer to the periphery of the face plate, the greater the deviation between the spherical surface and the tube surface as viewed from the center of deflection. This tendency is particularly noticeable in the case of CRTs that have a large face plate and a short depth (that is, a large deflection angle). Therefore, as shown in FIG. 1, a nonlinear sawtooth deflection signal is applied to the deflection coil so that the electron beam can be deflected over the entire screen by a uniform unit deflection amount. The deflection signal waveform shown in FIG. 1 resembles a portion of a sinusoidal waveform. The circuit that obtains the desired nonlinear waveform is known as an S-correction circuit, and this circuit has an S-correction capacitor connected in series with the deflection circuit. FIG. 2 is a circuit diagram showing an example of a conventional deflection circuit including an S correction circuit. This circuit is US Patent No.
It is disclosed in No. 4241296 (corresponding to Japanese Patent Application No. 55-70711). In Fig. 2, S correction capacitor 3
6 is connected in series to a deflection coil (yoke) 35, and a switching transistor 32,
A damper diode 37 and a blanking capacitor 40 are each connected in parallel. One end of this parallel circuit is connected to chassis earth, and the other end is connected via primary winding 33 of flyback transformer 34 and terminal 27 to positive voltage source B+. The base of switching transistor 32 is driven by a drive circuit comprising transistors 21, 54, 55, 60 and associated passive components. This drive circuit is controlled by square wave pulses output from an oscillator (eg, a flip-flop circuit) 20. Darlington connection transistor 55
The collector of is connected to a positive voltage source via a terminal 66, and the emitter of the other Darlington connected transistor 60 is connected to a capacitor 62 and a rectifier diode 6.
7. Secondary winding 61 of flyback transformer 34
connected to a negative voltage source with a Note that the pair of Darlington connected transistors 55 and 60 constitute a complementary transistor amplifier. Next, the operation of the circuit shown in FIG. 2 will be explained. In the negative cycle of the output of the oscillator 20, the transistor 21
and 54 are off and on, respectively, transistor 60 is saturated and transistor 55 is off.
Switching transistor 32 turns off rapidly during the negative half cycle. On the other hand, oscillator 2
In the positive half cycle of 0 output, transistor 2
1 and 54 turn on and off, respectively, turning transistors 55 and 60 on and off, respectively. Darlington connected transistor 55 provides base drive current to switching transistor 32 via resistor 56. When transistor 32 is turned on, current flows through switching transistor 32 into primary winding 33 of flyback transformer 34. Therefore, a negative voltage appears on the secondary winding 61 of the flyback transformer 34, charging the capacitor 62 through the rectifier diode 67 and generating the negative supply voltage necessary to drive the Darlington connected transistor 60. Series resonant circuit 35-36
The energy stored in is released through the transistor 32, causing a deflection current to flow in a predetermined direction through the deflection coil 35. This deflection current is substantially sinusoidal due to the reactance component. Oscillator 20
When the output of is in the negative half cycle, transistor 32 turns off and blocks current flowing through primary winding 33, creating a negative voltage spike that turns damper diode 37 on. Next, a deflection current flows from the positive voltage source B+ to the deflection coil 35 in a direction opposite to the above-mentioned predetermined direction. This deflection current also flows through the capacitor 3 connected in series to the deflection coil 35.
6, so it is a substantially sinusoidal current. The capacitance of the S correction capacitor 36 is determined by the deflection coil 3 so that the optimum S correction can be performed depending on the application.
5 in consideration of the inductance and scanning speed. In some television receivers, graphical or alphanumeric display devices, or graphical and alphanumeric display devices, it is desirable to be able to operate at different or continuously controllable scanning speeds. but,
Since it was necessary to switch the capacitance of the S-correction capacitor to an optimum value or to continuously control the capacitance to an optimum value, no one had previously attempted to design a deflection circuit that could operate at different scanning speeds. SUMMARY OF THE INVENTION Accordingly, it is an object of the present invention to provide an automatic S-correction circuit that can automatically control the capacitance of an S-correction capacitor. Another object of the present invention is to provide a deflection circuit whose characteristics can be controlled depending on the application. Yet another object of the invention is to provide a method for selecting the capacitance required for optimal S correction. The present invention will now be described with reference to the accompanying drawings. FIG. 3 is a block diagram showing a preferred embodiment of the automatic S correction circuit according to the present invention. Input terminal 7
The synchronizing pulse applied to 2 is applied to a resonant scanning deflection circuit 74. As the resonant scanning deflection circuit 74, the conventionally designed circuit shown in FIG. 2, for example, may be used. An S correction circuit 76 is connected to the deflection circuit 74, and the S correction circuit 76 includes a plurality of S correction capacitors having different capacitances and the deflection circuit 74.
The switching matrix has a switching matrix connected in series with the deflection coils. Although not shown, switching
The matrix can be composed of electronic switches such as bipolar transistors or FETs (field effect transistors), or electromechanical switches such as reed relays, since one end of each switch can be grounded, as can be seen in FIG. The S correction circuit 76 is controlled by control means responsive to the S correction capacitor terminal voltage of the S correction circuit 76. In the embodiment shown in FIG. 2, this control means includes a V _P which detects the peak voltage (V _P ) and the peak-to-peak voltage (V _PP ) appearing at the terminals of the S correction capacitor, respectively.
It has a peak detection circuit 78 and a _VPP detection circuit 80. V _P detected by the detection circuits 78 and 80 respectively
and V _PP voltages are applied to a divider circuit 82 to obtain an output signal proportional to the voltage ratio V _P /V _PP .
A signal corresponding to the voltage ratio V _P /V _PP obtained by the divider circuit 82 is applied to a switch control circuit 84 that controls the switching matrix of the S correction circuit 76 . As is clear from FIG. 3 and the above description, the automatic S-correction circuit of the present invention is a closed loop that utilizes the terminal voltage of the S-correction capacitor. The present invention uses a novel algorithm to determine the capacitance of the S correction capacitor necessary to provide a display with good linearity on the display surface of a display device. If there is no capacitor with an appropriate capacitance in the S correction circuit 76, the control circuit 84 increases or decreases the capacitance according to the above algorithm to control the capacitance to the optimum value. When the value reaches , the control circuit 84 stops controlling the capacitance. The algorithm for determining the optimal capacitance is based on the voltage ratio V _P /
It is based on the point that if V _PP is maintained at a constant value, the capacitance of the S correction capacitor can be set to the correct value. The above algorithm will be explained below using mathematical formulas. The deflection current i _D flowing through the deflection coil 35 is as follows (1)
It is given by Eq. i _D = Isinωt ...(1) where I: constant current based on the required peak deflection current

[Formula] (L is the yoke inductance, C is the capacitance of the S correction capacitor) The terminal voltage of the S correction capacitor can be found from equation (2). The peak voltage V _P of the S correction capacitor terminal is t=
0, and the minimum voltage V _M appears at t=t _nax . Note that t _nax indicates the end point of the scanning cycle. Therefore, The voltage ratio V _P /V _PP is given by the following equation (4). ωt=θ, where θ is the phase angle of the sine wave corresponding to the period during which the deflection current flows, so ωt _nax =θ _nax . Therefore, for any combination of CRT and yoke, θ _nax is constant regardless of the amount of deviation of the electron beam scanning the face plate of the CRT, and is independent of the scanning speed of the electron beam. I understand. Therefore, when the scanning speed changes, θ _nax must be a constant value, and θ _n
In order to maintain _ax at a constant value, the voltage ratio V _P /V _P
It turns out that _-P must be constant. still, It is. From equation (5), since L is the inductance of the deflection yoke having a constant value, t _nax ∝√, that is, C
∝t ² _nax . FIG. 4 shows an embodiment of an automatic S correction circuit according to the present invention. The S correction circuit 76 includes a plurality of S correction capacitors 36a, one end of which is commonly connected to the deflection coil of the resonant deflection circuit 74 (FIG. 3) via a line 10.
36b..., 36n included. The other end of the capacitor 36a is directly grounded, and the other ends of the capacitors 36b...36n are electrically selectively grounded via switches 12b...12n, respectively. Each switch 12 may be a relay only, but in the illustrated example, it is constituted by a parallel circuit of electronic switches including a relay SW driven by a transistor _Q1 and transistors _Q1 to _Q3 . The voltage at the terminals of S-correction capacitor 36 is determined by a conventional peak detector 78 including diode D ₂ and capacitor C ₂ and diodes D ₃ , D ₄ and capacitor C 2 .
C ₃ and C ₄ are applied to a conventional peak-to-peak detector 80 to obtain V _P and V _PP respectively. V _P are connected to operational amplifiers 14 through variable voltage dividers R ₂ −R ₃ respectively.
and 16 non-inverting and inverting inputs. V
_PP are voltage dividers R ₆ − R ₇ and R ₄ − with predetermined partial pressure ratios, respectively.
It is applied via R ₅ to the inverting and non-inverting inputs of operational amplifiers 14 and 16. These operational amplifiers 14,
The output of 16 is applied to an oscillator 86 and the output of the latter is applied to the base of transistor _Q5 . The output of the oscillator 86 and the collector output of the transistor _Q5 are respectively connected to the clock terminal CK of the reversible counter 88.
and the count up/down control terminal UP/D. The outputs Q _b to Q _o of the reversible counter 88 are S
The voltage is applied to the control terminals of the switches 12b...12n of the correction circuit 76. In operation, the sine and cosine deflection currents as described above flow through the S-correction capacitor 36, and corresponding voltage peak values V _P and peak-to-peak values V _PP are obtained from detectors 78 and 80, respectively. The variable voltage divider R ₂ -R ₃ is used to select the ratio of V _P /V _PP =K to the desired value (i.e. V _P /K = V _P-
P ). Here, the voltage division ratios of voltage dividers R ₆ -R ₇ and R ₄ -R ₅ are assumed to be a and b, respectively. When aV _PP <V _P /K,
The operational amplifier 14 outputs a positive output, and bV _PP >V _P /
When K, the operational amplifier 16 provides a positive output. Therefore, in the range of bV _PP <V _P /K<aV _PP , neither of the operational amplifiers 14 and 16 operating as a comparator outputs a positive output. Oscillator 86 oscillates at a predetermined low frequency when either amplifier 14 or 16 provides a positive output, and clocks reversible counter 88. Since the counting direction of the reversible counter 88 is reversed by the output of the amplifier 16, the operation of the oscillator 86 remains unchanged depending on whether the amplifier 14 or 16 outputs a positive output.
Only the counting direction of the reversible counter 88 is switched. V
If _P /K is within the above range, the optimal S capacitor has been selected and the circuit maintains this state. The output of reversible counter 88 is normally at a high level, transistors Q ₁ , Q ₂ , Q ₄ are on, Q ₃ is off, and both relay SW and electronic switch Q ₄ are on. However, if, for example, the Q _b output goes low, relay SW and transistor Q ₄ are both turned off, disconnecting capacitor 36b from the circuit. In this case, diode _D1 is also turned off, turning on electronic switch transistor _Q4 for a predetermined period determined by the time constants of capacitor _C1 and resistor _R1 . This prevents variations in V _P and V _PP until oscillator 86 generates the next clock pulse.
Although the circuit details are omitted, each switch 12b...
...12n operates in the same way by the Q _b ... Q _o output from the reversible counter 88, and bV _PP <V _P /K <
The S correction operation is automatically performed so that the output voltage of aV _PP appears on the S capacitor 36. It goes without saying that the number and capacitance of the capacitors 36a...36n can be arbitrarily selected depending on the accuracy desired for correction. As can be seen from the above explanation, the automatic S correction circuit of the present invention detects the peak and peak-to-peak voltage appearing at the terminal of the S correction capacitor, and automatically
Determine the optimal capacitance of the correction capacitor. The automatic S correction circuit of the present invention has an extremely simple and inexpensive structure, and has the feature that the present invention can be implemented using a conventional circuit structure and commercially available circuit elements.
Incidentally, if it is necessary to perform the automatic S correction of the present invention more accurately, digital control may be used.

[Brief explanation of the drawing]

Fig. 1 is a waveform diagram showing the deflection current waveform (solid line) after S correction, Fig. 2 is a circuit diagram of a conventional deflection circuit having an S correction circuit, and Fig. 3 is a block diagram of the automatic S correction circuit of the present invention. , FIG. 4 is a circuit diagram showing an embodiment of the automatic S correction circuit of the present invention. 74... Resonant scanning deflection circuit, 76... S correction capacitor, 78... Peak voltage detector, 80...
...Peak-to-peak voltage detector, 82...Divider,
84...Switch control means.

Claims (1)

[Claims] 1 A controllable S correction capacitor and the peak voltage and peak voltage appearing between the terminals of the correction capacitor.
Voltage detecting means for detecting a peak voltage; and controlling the capacitance of the S correction capacitor based on the detected value of the voltage detecting means so that the peak voltage and the peak-to-peak voltage ratio are within a predetermined range. An automatic S correction circuit for a resonant scanning deflection circuit, characterized in that the automatic S correction circuit comprises: